Change in coreboot[master]: soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104

[Raul Rangel (Code Review)]

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48309 )

Change subject: soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104
......................................................................

soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104

The number at the end actually means the max MiB/s. So 52 MHz clock @ 8x
data width, sampled on each clock edge = 104 MiB/s.

BUG=b:159823235
BRANCH=zork
TEST=build zork

Signed-off-by: Raul E Rangel 
Change-Id: I7818d8cb5ed5974c60a900477a0aa2ecc904db0c
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
M src/soc/amd/picasso/include/soc/platform_descriptors.h
3 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/48309/1

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index a39549e..2a385ce 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -164,7 +164,7 @@
    		SD_EMMC_SD_UHS_I_SDR_104,
    		SD_EMMC_EMMC_SDR_26,
    		SD_EMMC_EMMC_SDR_52,
-			SD_EMMC_EMMC_DDR_52,
+			SD_EMMC_EMMC_DDR_104,
    		SD_EMMC_EMMC_HS200,
    		SD_EMMC_EMMC_HS400,
    		SD_EMMC_EMMC_HS300,
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index 95e691d..fe94061 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -38,8 +38,8 @@
    case SD_EMMC_EMMC_SDR_52:
    	val = EMMC_SDR_52;
    	break;
-	case SD_EMMC_EMMC_DDR_52:
-		val = EMMC_DDR_52;
+	case SD_EMMC_EMMC_DDR_104:
+		val = EMMC_DDR_104;
    	break;
    case SD_EMMC_EMMC_HS200:
    	val = EMMC_HS200;
diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h
index 0ea6f2b..0a77061 100644
--- a/src/soc/amd/picasso/include/soc/platform_descriptors.h
+++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h
@@ -17,7 +17,7 @@
 #define SD_UHS_I_SDR_104	5
 #define EMMC_SDR_26		6
 #define EMMC_SDR_52		7
-#define EMMC_DDR_52		8
+#define EMMC_DDR_104		8
 #define EMMC_HS200		9
 #define EMMC_HS400		10
 #define EMMC_HS300		11

[Rob Barnes (Code Review)]

Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48309 )

Change subject: soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104
......................................................................

Patch Set 1: Code-Review+1

Could you please add a datasheet reference in the commit message or in the comments.

[Raul Rangel (Code Review)]

Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Rob Barnes, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48309

to look at the new patch set (#2).

Change subject: soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104
......................................................................

soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104

The number at the end actually means the max MiB/s. So 52 MHz clock @ 8x
data width, sampled on each clock edge = 104 MiB/s.

According to JEDEC Standard No. 84-B51A (JESD84-B51A), maximum bandwidth
& clock frequency for various MMC bus speed modes are (at x8 bus width):
MMC_Legacy: 26 MB/s at 26 MHz Single Data Rate (SDR)
MMC_HS: 52 MB/s at 52 MHz SDR
MMC_DDR52: 104 MB/s at 52 MHz Dual Data Rate (DDR)
MMC_HS200: 200 MB/s at 200 MHz SDR
MMC_HS400: 400 MB/s at 200 MHz DDR

BUG=b:159823235
BRANCH=zork
TEST=build zork

Signed-off-by: Raul E Rangel 
Change-Id: I7818d8cb5ed5974c60a900477a0aa2ecc904db0c
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
M src/soc/amd/picasso/include/soc/platform_descriptors.h
3 files changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/48309/2

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48309 )

Change subject: soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104
......................................................................

Patch Set 2:
> Patch Set 1: Code-Review+1
>
> Could you please add a datasheet reference in the commit message or in the comments.

Done

[Jason Glenesk (Code Review)]

Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48309 )

Change subject: soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104
......................................................................

Patch Set 2: Code-Review+1

[Marshall Dawson (Code Review)]

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48309 )

Change subject: soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104
......................................................................

Patch Set 2: Code-Review+2

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48309 )

Change subject: soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104
......................................................................

soc/amd/picasso: Rename SD_EMMC_EMMC_DDR_52 to SD_EMMC_EMMC_DDR_104

The number at the end actually means the max MiB/s. So 52 MHz clock @ 8x
data width, sampled on each clock edge = 104 MiB/s.

According to JEDEC Standard No. 84-B51A (JESD84-B51A), maximum bandwidth
& clock frequency for various MMC bus speed modes are (at x8 bus width):
MMC_Legacy: 26 MB/s at 26 MHz Single Data Rate (SDR)
MMC_HS: 52 MB/s at 52 MHz SDR
MMC_DDR52: 104 MB/s at 52 MHz Dual Data Rate (DDR)
MMC_HS200: 200 MB/s at 200 MHz SDR
MMC_HS400: 400 MB/s at 200 MHz DDR

BUG=b:159823235
BRANCH=zork
TEST=build zork

Signed-off-by: Raul E Rangel 
Change-Id: I7818d8cb5ed5974c60a900477a0aa2ecc904db0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48309
Reviewed-by: Jason Glenesk 
Reviewed-by: Marshall Dawson 
Reviewed-by: Rob Barnes 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
M src/soc/amd/picasso/include/soc/platform_descriptors.h
3 files changed, 4 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved
  Rob Barnes: Looks good to me, but someone else must approve
  Jason Glenesk: Looks good to me, but someone else must approve

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 27f1a2a..c0a6457 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -175,7 +175,7 @@
    		SD_EMMC_SD_UHS_I_SDR_104,
    		SD_EMMC_EMMC_SDR_26,
    		SD_EMMC_EMMC_SDR_52,
-			SD_EMMC_EMMC_DDR_52,
+			SD_EMMC_EMMC_DDR_104,
    		SD_EMMC_EMMC_HS200,
    		SD_EMMC_EMMC_HS400,
    		SD_EMMC_EMMC_HS300,
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index a08a209..c7befe4 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -38,8 +38,8 @@
    case SD_EMMC_EMMC_SDR_52:
    	val = EMMC_SDR_52;
    	break;
-	case SD_EMMC_EMMC_DDR_52:
-		val = EMMC_DDR_52;
+	case SD_EMMC_EMMC_DDR_104:
+		val = EMMC_DDR_104;
    	break;
    case SD_EMMC_EMMC_HS200:
    	val = EMMC_HS200;
diff --git a/src/soc/amd/picasso/include/soc/platform_descriptors.h b/src/soc/amd/picasso/include/soc/platform_descriptors.h
index fc7f140..28062b6 100644
--- a/src/soc/amd/picasso/include/soc/platform_descriptors.h
+++ b/src/soc/amd/picasso/include/soc/platform_descriptors.h
@@ -17,7 +17,7 @@
 #define SD_UHS_I_SDR_104	5
 #define EMMC_SDR_26		6
 #define EMMC_SDR_52		7
-#define EMMC_DDR_52		8
+#define EMMC_DDR_104		8
 #define EMMC_HS200		9
 #define EMMC_HS400		10
 #define EMMC_HS300		11