coreboot-gerrit December 2020

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Change in coreboot[master]: mediatek/mt8192: add spmfw loader
by Yidi Lin (Code Review) 10 Dec '20

10 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46389 ) Change subject: mediatek/mt8192: add spmfw loader ...................................................................... mediatek/mt8192: add spmfw loader To support mt8192 power saving during suspend to RAM, this patch loads spmfw to support SPM suspend. SPM needs its own firmware to do these power saving in the right timing under correct conditions. After linux PM suspends, SPM is able to turn off more power saving for the SoC such as DRAM self-refresh mode and turning off 26M crystal. BUG=b:159079649 TEST=Asurada boots up to shell Signed-off-by: Roger Lu <roger.lu(a)mediatek.com> Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371 --- M src/mainboard/google/asurada/mainboard.c M src/soc/mediatek/common/mtcmos.c M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/spm.h A src/soc/mediatek/mt8192/spm.c 5 files changed, 1,551 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46389/1 diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 76a71c7..7b3ef22 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -6,6 +6,7 @@ #include <device/mmio.h> #include <lib.h> #include <soc/gpio_common.h> +#include <soc/spm.h> #include <soc/usb.h> #include "gpio.h" @@ -77,6 +78,9 @@ setup_usb_host(); register_reset_to_bl31(); + + if (spm_init()) + printk(BIOS_ERR, "spm init fail, system suspend may stuck\n"); } static void mainboard_enable(struct device *dev) diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c index cfd148c..0bba19e 100644 --- a/src/soc/mediatek/common/mtcmos.c +++ b/src/soc/mediatek/common/mtcmos.c @@ -23,7 +23,7 @@ static void mtcmos_power_on(const struct power_domain_data *pd) { - write32(&mtk_spm->poweron_config_set, + write32(&mtk_spm->poweron_config_en, (SPM_PROJECT_CODE << 16) | (1U << 0)); setbits32(pd->pwr_con, PWR_ON); diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 891d38a..d417ae2 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -33,6 +33,7 @@ ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += spm.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c @@ -42,6 +43,11 @@ MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 +cbfs-files-y += spm_firmware.bin +spm_firmware.bin-file := $(MT8192_BLOB_DIR)/spm_firmware.bin +spm_firmware.bin-type := raw +spm_firmware.bin-compression := $(CBFS_COMPRESS_FLAG) + DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram $(DRAM_CBFS)-file := $(MT8192_BLOB_DIR)/dram.elf $(DRAM_CBFS)-type := stage diff --git a/src/soc/mediatek/mt8192/include/soc/spm.h b/src/soc/mediatek/mt8192/include/soc/spm.h index 73ef798..53b86e5 100644 --- a/src/soc/mediatek/mt8192/include/soc/spm.h +++ b/src/soc/mediatek/mt8192/include/soc/spm.h @@ -4,10 +4,309 @@ #define SOC_MEDIATEK_MT8192_SPM_H #include <soc/addressmap.h> +#include <stdint.h> #include <types.h> /* SPM READ/WRITE CFG */ -#define SPM_PROJECT_CODE 0xb16 +#define SPM_PROJECT_CODE (0xb16) +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + +/* POWERON_CONFIG_EN (0x10006000+0x000) */ +#define BCLK_CG_EN_LSB (1U << 0) /* 1b */ + +/* SPM_CLK_CON (0x10006000+0x00C) */ +#define REG_SYSCLK1_SRC_MD2_SRCCLKENA (1U << 28) /* 1b */ + +/* PCM_CON0 (0x10006000+0x018) */ +#define PCM_CK_EN_LSB (1U << 2) /* 1b */ +#define PCM_SW_RESET_LSB (1U << 15) /* 1b */ + +/* PCM_CON1 (0x10006000+0x01C) */ +#define RG_IM_SLAVE_LSB (1U << 0) /* 1b */ +#define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */ +#define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */ +#define SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */ +#define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */ +#define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ +#define REG_EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ +#define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ + +/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */ +#define SPM_WAKEUP_EVENT_MASK_BIT0 (1U << 0) /* 1b */ +#define SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B (1U << 24) /* 1b */ + +/* DDR_EN_DBC_CON1 (0x10006000+0x0EC) */ +#define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 0) /* 1b */ + +/* SPM_DVFS_MISC (0x10006000+0x4AC) */ +#define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */ +#define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */ + +/* SPM_SW_FLAG_0 (0x10006000+0x600) */ +#define SPM_FLAG_DISABLE_VCORE_DVS (1U << 3) /* 1b */ +#define SPM_FLAG_DISABLE_VCORE_DFS (1U << 4) /* 1b */ +#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10) /* 1b */ + +/* SYS_TIMER_CON (0x10006000+0x98C) */ +#define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */ + +/* MD32PCM_CFGREG_SW_RSTN (0x10006000+0xA00) */ +#define MD32PCM_CFGREG_SW_RSTN_RESET (1U << 0) /* 1b */ + +/************************************** + * Config and Parameter + **************************************/ +#define POWER_ON_VAL1_DEF (0x80015860) +#define SPM_WAKEUP_EVENT_MASK_DEF (0xefffffff) +#define SPM_ACK_CHK_3_SEL_HW_S1 (0x00350098) +#define SPM_ACK_CHK_3_HW_S1_CNT (0x1) +#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG (0x800) +#define SPM_ACK_CHK_3_CON_EN (0x110) +#define SPM_ACK_CHK_3_CON_CLR_ALL (0x2) +#define SPM_BUS_PROTECT_MASK_B_DEF (0xffffffff) +#define SPM_BUS_PROTECT2_MASK_B_DEF (0xffffffff) +#define MD32PCM_DMA0_CON_VAL (0x0003820e) +#define MD32PCM_DMA0_START_VAL (0x00008000) +#define MD32PCM_CFGREG_SW_RSTN_RUN (0x1) +#define SPM_DVFS_LEVEL_DEF (0x00000001) +#define SPM_DVS_DFS_LEVEL_DEF (0x00010001) +#define SPM_RESOURCE_ACK_CON0_DEF (0x00000000) +#define SPM_RESOURCE_ACK_CON1_DEF (0x00000000) +#define SPM_RESOURCE_ACK_CON2_DEF (0xcccc4e4e) +#define SPM_RESOURCE_ACK_CON3_DEF (0x00000000) +#define ARMPLL_CLK_SEL_DEF (0x3ff) +#define DDR_EN_DBC_CON0_DEF (0x154) +#define SPM_SYSCLK_SETTLE (0x60fe) +#define SPM_INIT_DONE_US (20) +#define PCM_WDT_TIMEOUT (30 * 32768) +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) + +/************************************** + * Define and Declare + **************************************/ +/* SPM_IRQ_MASK */ +#define ISRM_TWAM (1U << 2) +#define ISRM_PCM_RETURN (1U << 3) +#define ISRM_RET_IRQ_AUX (0x3fe00) +#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) +#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) + +/* SPM_IRQ_STA */ +#define ISRS_TWAM (1U << 2) +#define ISRS_PCM_RETURN (1U << 3) +#define ISRC_TWAM ISRS_TWAM +#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN +#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) + +/* PCM_PWR_IO_EN */ +#define PCM_PWRIO_EN_R0 (1U << 0) +#define PCM_PWRIO_EN_R7 (1U << 7) +#define PCM_RF_SYNC_R0 (1U << 16) +#define PCM_RF_SYNC_R6 (1U << 22) +#define PCM_RF_SYNC_R7 (1U << 23) + +/* SPM_SWINT */ +#define PCM_SW_INT_ALL (0x3ff) + +struct pwr_ctrl { + u32 pcm_flags; + u32 pcm_flags_cust; + u32 pcm_flags_cust_set; + u32 pcm_flags_cust_clr; + u32 pcm_flags1; + u32 pcm_flags1_cust; + u32 pcm_flags1_cust_set; + u32 pcm_flags1_cust_clr; + u32 timer_val; + u32 timer_val_cust; + u32 timer_val_ramp_en; + u32 timer_val_ramp_en_sec; + u32 wake_src; + u32 wake_src_cust; + u32 wakelock_timer_val; + u8 wdt_disable; + + /* Auto-gen Start */ + + /* SPM_CLK_CON */ + u8 reg_srcclken0_ctl; + u8 reg_srcclken1_ctl; + u8 reg_spm_lock_infra_dcm; + u8 reg_srcclken_mask; + u8 reg_md1_c32rm_en; + u8 reg_md2_c32rm_en; + u8 reg_clksq0_sel_ctrl; + u8 reg_clksq1_sel_ctrl; + u8 reg_srcclken0_en; + u8 reg_srcclken1_en; + u32 reg_sysclk0_src_mask_b; + u32 reg_sysclk1_src_mask_b; + + /* SPM_AP_STANDBY_CON */ + u8 reg_wfi_op; + u8 reg_wfi_type; + u8 reg_mp0_cputop_idle_mask; + u8 reg_mp1_cputop_idle_mask; + u8 reg_mcusys_idle_mask; + u8 reg_md_apsrc_1_sel; + u8 reg_md_apsrc_0_sel; + u8 reg_conn_apsrc_sel; + + /* SPM_SRC6_MASK */ + u8 reg_dpmaif_srcclkena_mask_b; + u8 reg_dpmaif_infra_req_mask_b; + u8 reg_dpmaif_apsrc_req_mask_b; + u8 reg_dpmaif_vrf18_req_mask_b; + u8 reg_dpmaif_ddr_en_mask_b; + + /* SPM_SRC_REQ */ + u8 reg_spm_apsrc_req; + u8 reg_spm_f26m_req; + u8 reg_spm_infra_req; + u8 reg_spm_vrf18_req; + u8 reg_spm_ddr_en_req; + u8 reg_spm_dvfs_req; + u8 reg_spm_sw_mailbox_req; + u8 reg_spm_sspm_mailbox_req; + u8 reg_spm_adsp_mailbox_req; + u8 reg_spm_scp_mailbox_req; + + /* SPM_SRC_MASK */ + u8 reg_md_srcclkena_0_mask_b; + u8 reg_md_srcclkena2infra_req_0_mask_b; + u8 reg_md_apsrc2infra_req_0_mask_b; + u8 reg_md_apsrc_req_0_mask_b; + u8 reg_md_vrf18_req_0_mask_b; + u8 reg_md_ddr_en_0_mask_b; + u8 reg_md_srcclkena_1_mask_b; + u8 reg_md_srcclkena2infra_req_1_mask_b; + u8 reg_md_apsrc2infra_req_1_mask_b; + u8 reg_md_apsrc_req_1_mask_b; + u8 reg_md_vrf18_req_1_mask_b; + u8 reg_md_ddr_en_1_mask_b; + u8 reg_conn_srcclkena_mask_b; + u8 reg_conn_srcclkenb_mask_b; + u8 reg_conn_infra_req_mask_b; + u8 reg_conn_apsrc_req_mask_b; + u8 reg_conn_vrf18_req_mask_b; + u8 reg_conn_ddr_en_mask_b; + u8 reg_conn_vfe28_mask_b; + u8 reg_srcclkeni0_srcclkena_mask_b; + u8 reg_srcclkeni0_infra_req_mask_b; + u8 reg_srcclkeni1_srcclkena_mask_b; + u8 reg_srcclkeni1_infra_req_mask_b; + u8 reg_srcclkeni2_srcclkena_mask_b; + u8 reg_srcclkeni2_infra_req_mask_b; + u8 reg_infrasys_apsrc_req_mask_b; + u8 reg_infrasys_ddr_en_mask_b; + u8 reg_md32_srcclkena_mask_b; + u8 reg_md32_infra_req_mask_b; + u8 reg_md32_apsrc_req_mask_b; + u8 reg_md32_vrf18_req_mask_b; + u8 reg_md32_ddr_en_mask_b; + + /* SPM_SRC2_MASK */ + u8 reg_scp_srcclkena_mask_b; + u8 reg_scp_infra_req_mask_b; + u8 reg_scp_apsrc_req_mask_b; + u8 reg_scp_vrf18_req_mask_b; + u8 reg_scp_ddr_en_mask_b; + u8 reg_audio_dsp_srcclkena_mask_b; + u8 reg_audio_dsp_infra_req_mask_b; + u8 reg_audio_dsp_apsrc_req_mask_b; + u8 reg_audio_dsp_vrf18_req_mask_b; + u8 reg_audio_dsp_ddr_en_mask_b; + u8 reg_ufs_srcclkena_mask_b; + u8 reg_ufs_infra_req_mask_b; + u8 reg_ufs_apsrc_req_mask_b; + u8 reg_ufs_vrf18_req_mask_b; + u8 reg_ufs_ddr_en_mask_b; + u8 reg_disp0_apsrc_req_mask_b; + u8 reg_disp0_ddr_en_mask_b; + u8 reg_disp1_apsrc_req_mask_b; + u8 reg_disp1_ddr_en_mask_b; + u8 reg_gce_infra_req_mask_b; + u8 reg_gce_apsrc_req_mask_b; + u8 reg_gce_vrf18_req_mask_b; + u8 reg_gce_ddr_en_mask_b; + u8 reg_apu_srcclkena_mask_b; + u8 reg_apu_infra_req_mask_b; + u8 reg_apu_apsrc_req_mask_b; + u8 reg_apu_vrf18_req_mask_b; + u8 reg_apu_ddr_en_mask_b; + u8 reg_cg_check_srcclkena_mask_b; + u8 reg_cg_check_apsrc_req_mask_b; + u8 reg_cg_check_vrf18_req_mask_b; + u8 reg_cg_check_ddr_en_mask_b; + + /* SPM_SRC3_MASK */ + u8 reg_dvfsrc_event_trigger_mask_b; + u8 reg_sw2spm_int0_mask_b; + u8 reg_sw2spm_int1_mask_b; + u8 reg_sw2spm_int2_mask_b; + u8 reg_sw2spm_int3_mask_b; + u8 reg_sc_adsp2spm_wakeup_mask_b; + u8 reg_sc_sspm2spm_wakeup_mask_b; + u8 reg_sc_scp2spm_wakeup_mask_b; + u8 reg_csyspwrreq_mask; + u8 reg_spm_srcclkena_reserved_mask_b; + u8 reg_spm_infra_req_reserved_mask_b; + u8 reg_spm_apsrc_req_reserved_mask_b; + u8 reg_spm_vrf18_req_reserved_mask_b; + u8 reg_spm_ddr_en_reserved_mask_b; + u8 reg_mcupm_srcclkena_mask_b; + u8 reg_mcupm_infra_req_mask_b; + u8 reg_mcupm_apsrc_req_mask_b; + u8 reg_mcupm_vrf18_req_mask_b; + u8 reg_mcupm_ddr_en_mask_b; + u8 reg_msdc0_srcclkena_mask_b; + u8 reg_msdc0_infra_req_mask_b; + u8 reg_msdc0_apsrc_req_mask_b; + u8 reg_msdc0_vrf18_req_mask_b; + u8 reg_msdc0_ddr_en_mask_b; + u8 reg_msdc1_srcclkena_mask_b; + u8 reg_msdc1_infra_req_mask_b; + u8 reg_msdc1_apsrc_req_mask_b; + u8 reg_msdc1_vrf18_req_mask_b; + u8 reg_msdc1_ddr_en_mask_b; + + /* SPM_SRC4_MASK */ + u32 ccif_event_mask_b; + u8 reg_bak_psri_srcclkena_mask_b; + u8 reg_bak_psri_infra_req_mask_b; + u8 reg_bak_psri_apsrc_req_mask_b; + u8 reg_bak_psri_vrf18_req_mask_b; + u8 reg_bak_psri_ddr_en_mask_b; + u8 reg_dramc0_md32_infra_req_mask_b; + u8 reg_dramc0_md32_vrf18_req_mask_b; + u8 reg_dramc1_md32_infra_req_mask_b; + u8 reg_dramc1_md32_vrf18_req_mask_b; + u8 reg_conn_srcclkenb2pwrap_mask_b; + u8 reg_dramc0_md32_wakeup_mask; + u8 reg_dramc1_md32_wakeup_mask; + + /* SPM_SRC5_MASK */ + u32 reg_mcusys_merge_apsrc_req_mask_b; + u32 reg_mcusys_merge_ddr_en_mask_b; + u8 reg_msdc2_srcclkena_mask_b; + u8 reg_msdc2_infra_req_mask_b; + u8 reg_msdc2_apsrc_req_mask_b; + u8 reg_msdc2_vrf18_req_mask_b; + u8 reg_msdc2_ddr_en_mask_b; + u8 reg_pcie_srcclkena_mask_b; + u8 reg_pcie_infra_req_mask_b; + u8 reg_pcie_apsrc_req_mask_b; + u8 reg_pcie_vrf18_req_mask_b; + u8 reg_pcie_ddr_en_mask_b; + + /* SPM_WAKEUP_EVENT_MASK */ + u32 reg_wakeup_event_mask; + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + u32 reg_ext_wakeup_event_mask; + + /* Auto-gen End */ +}; enum { DISP_PWR_STA_MASK = 0x1 << 20, @@ -19,7 +318,7 @@ }; struct mtk_spm_regs { - u32 poweron_config_set; + u32 poweron_config_en; u32 spm_power_on_val0; u32 spm_power_on_val1; u32 spm_clk_con; @@ -34,14 +333,14 @@ u32 pcm_timer_val; u32 pcm_wdt_val; u32 spm_src6_mask; - u32 reserved1[1]; - u32 spm_sw_rst_con; /* 0x0040 */ + u32 reserved0; + u32 spm_sw_rst_con; u32 spm_sw_rst_con_set; u32 spm_sw_rst_con_clr; u32 vs1_psr_mask_b; u32 vs2_psr_mask_b; - u32 reserved2[12]; - u32 md32_clk_con; /* 0x0084 */ + u32 reserved1[12]; + u32 md32_clk_con; u32 spm_sram_rsv_con; u32 spm_swint; u32 spm_swint_set; @@ -77,27 +376,27 @@ u32 pcm_reg6_data; u32 pcm_reg7_data; u32 pcm_reg13_data; - u32 src_req_sta_0; - u32 src_req_sta_1; - u32 src_req_sta_2; + u32 src_req_sta0; + u32 src_req_sta1; + u32 src_req_sta2; u32 pcm_timer_out; u32 pcm_wdt_out; u32 spm_irq_sta; - u32 src_req_sta_4; + u32 src_req_sta4; u32 md32pcm_wakeup_sta; u32 md32pcm_event_sta; u32 spm_wakeup_sta; u32 spm_wakeup_ext_sta; u32 spm_wakeup_misc; u32 mm_dvfs_halt; - u32 reserved3[2]; - u32 bus_protect_rdy; /* 0x0150 */ + u32 reserved2[2]; + u32 bus_protect_rdy; u32 bus_protect1_rdy; u32 bus_protect2_rdy; u32 bus_protect3_rdy; u32 subsys_idle_sta; u32 pcm_sta; - u32 src_req_sta_3; + u32 src_req_sta3; u32 pwr_status; u32 pwr_status_2nd; u32 cpu_pwr_status; @@ -109,15 +408,15 @@ u32 spm_ddren_event_count_sta; u32 md32pcm_sta; u32 md32pcm_pc; - u32 reserved4[3]; - u32 dvfsrc_event_sta; /* 0x01a4 */ + u32 reserved3[3]; + u32 dvfsrc_event_sta; u32 bus_protect4_rdy; u32 bus_protect5_rdy; u32 bus_protect6_rdy; u32 bus_protect7_rdy; u32 bus_protect8_rdy; - u32 reserved5[5]; - u32 spm_twam_last_sta0; /* 0x01d0 */ + u32 reserved4[5]; + u32 spm_twam_last_sta0; u32 spm_twam_last_sta1; u32 spm_twam_last_sta2; u32 spm_twam_last_sta3; @@ -139,8 +438,8 @@ u32 spm_cpu5_pwr_con; u32 spm_cpu6_pwr_con; u32 spm_cpu7_pwr_con; - u32 reserved6[1]; - u32 armpll_clk_con; /* 0x022c */ + u32 reserved5; + u32 armpll_clk_con; u32 mcusys_idle_sta; u32 gic_wakeup_sta; u32 cpu_spare_con; @@ -150,8 +449,8 @@ u32 ext_int_wakeup_req; u32 ext_int_wakeup_req_set; u32 ext_int_wakeup_req_clr; - u32 reserved7[3]; - u32 mp0_cpu0_irq_mask; /* 0x0260 */ + u32 reserved6[3]; + u32 mp0_cpu0_irq_mask; u32 mp0_cpu1_irq_mask; u32 mp0_cpu2_irq_mask; u32 mp0_cpu3_irq_mask; @@ -169,8 +468,8 @@ u32 mp0_cpu7_wfi_en; u32 root_cputop_addr; u32 root_core_addr; - u32 reserved8[10]; - u32 spm2sw_mailbox_0; /* 0x02d0 */ + u32 reserved7[10]; + u32 spm2sw_mailbox_0; u32 spm2sw_mailbox_1; u32 spm2sw_mailbox_2; u32 spm2sw_mailbox_3; @@ -227,22 +526,147 @@ u32 debugtop_sram_con; u32 dp_tx_pwr_con; u32 dpmaif_sram_con; - u32 dpy_shu2_sram_con; + u32 dpy_shu2_con; u32 dramc_mcu2_sram_con; u32 dramc_mcu_sram_con; u32 mcupm_pwr_con; u32 dpy2_pwr_con; u32 peri_pwr_con; + u32 reserved8[13]; + u32 spm_mem_ck_sel; + u32 spm_bus_protect_mask_b; + u32 spm_bus_protect1_mask_b; + u32 spm_bus_protect2_mask_b; + u32 spm_bus_protect3_mask_b; + u32 spm_bus_protect4_mask_b; + u32 spm_emi_bw_mode; + u32 ap2md_peer_wakeup; + u32 ulposc_con; + u32 spm2mm_con; + u32 spm_bus_protect5_mask_b; + u32 spm2mcupm_con; + u32 ap_mdsrc_req; + u32 spm2emi_enter_ulpm; + u32 spm2md_dvfs_con; + u32 md2spm_dvfs_con; + u32 spm_bus_protect6_mask_b; + u32 spm_bus_protect7_mask_b; + u32 spm_bus_protect8_mask_b; + u32 spm_pll_con; + u32 cpu_dvfs_req; + u32 spm_dram_mcu_sw_con0; + u32 spm_dram_mcu_sw_con1; + u32 spm_dram_mcu_sw_con2; + u32 spm_dram_mcu_sw_con3; + u32 spm_dram_mcu_sw_con4; + u32 spm_dram_mcu_sta_0; + u32 spm_dram_mcu_sta_1; + u32 spm_dram_mcu_sta_2; + u32 spm_dram_mcu_sw_sel_0; + u32 relay_dvfs_level; + u32 reserved9; + u32 dramc_dpy_clk_sw_con_0; + u32 dramc_dpy_clk_sw_con_1; + u32 dramc_dpy_clk_sw_con_2; + u32 dramc_dpy_clk_sw_con_3; + u32 dramc_dpy_clk_sw_sel_0; + u32 dramc_dpy_clk_sw_sel_1; + u32 dramc_dpy_clk_sw_sel_2; + u32 dramc_dpy_clk_sw_sel_3; + u32 dramc_dpy_clk_spm_con; + u32 spm_dvfs_level; + u32 spm_cirq_con; + u32 spm_dvfs_misc; + u32 spm_vs1_vs2_rc_con; + u32 rg_module_sw_cg_0_mask_req_0; + u32 rg_module_sw_cg_0_mask_req_1; + u32 rg_module_sw_cg_0_mask_req_2; + u32 rg_module_sw_cg_1_mask_req_0; + u32 rg_module_sw_cg_1_mask_req_1; + u32 rg_module_sw_cg_1_mask_req_2; + u32 rg_module_sw_cg_2_mask_req_0; + u32 rg_module_sw_cg_2_mask_req_1; + u32 rg_module_sw_cg_2_mask_req_2; + u32 rg_module_sw_cg_3_mask_req_0; + u32 rg_module_sw_cg_3_mask_req_1; + u32 rg_module_sw_cg_3_mask_req_2; + u32 pwr_status_mask_req_0; + u32 pwr_status_mask_req_1; + u32 pwr_status_mask_req_2; + u32 spm_cg_check_con; + u32 spm_src_rdy_sta; + u32 spm_dvs_dfs_level; + u32 spm_force_dvfs; + u32 reserved10[64]; + u32 spm_sw_flag_0; + u32 spm_sw_debug_0; + u32 spm_sw_flag_1; + u32 reserved11[8]; + u32 spm_sw_rsv_7; + u32 spm_sw_rsv_8; + u32 reserved12[203]; + u32 spm_ack_chk_con_3; + u32 spm_ack_chk_pc_3; + u32 spm_ack_chk_sel_3; + u32 spm_ack_chk_timer_3; + u32 reserved13[7]; + u32 sys_timer_con; + u32 reserved14[28]; + u32 md32pcm_cfgreg_sw_rstn; + u32 reserved15[127]; + u32 md32pcm_dma0_src; + u32 md32pcm_dma0_dst; + u32 md32pcm_dma0_wppt; + u32 md32pcm_dma0_wpto; + u32 md32pcm_dma0_count; + u32 md32pcm_dma0_con; + u32 md32pcm_dma0_start; + u32 reserved16[2]; + u32 md32pcm_dma0_rlct; }; - -check_member(mtk_spm_regs, md32_clk_con, 0x0084); -check_member(mtk_spm_regs, bus_protect_rdy, 0x0150); -check_member(mtk_spm_regs, dvfsrc_event_sta, 0x01a4); -check_member(mtk_spm_regs, spm_twam_last_sta0, 0x01d0); -check_member(mtk_spm_regs, mp0_cpu0_irq_mask, 0x0260); +check_member(mtk_spm_regs, poweron_config_en, 0x0); +check_member(mtk_spm_regs, vs2_psr_mask_b, 0x50); +check_member(mtk_spm_regs, md32_clk_con, 0x84); +check_member(mtk_spm_regs, mm_dvfs_halt, 0x144); +check_member(mtk_spm_regs, bus_protect_rdy, 0x150); +check_member(mtk_spm_regs, md32pcm_pc, 0x194); +check_member(mtk_spm_regs, dvfsrc_event_sta, 0x1a4); +check_member(mtk_spm_regs, bus_protect8_rdy, 0x1b8); +check_member(mtk_spm_regs, spm_twam_last_sta0, 0x1d0); +check_member(mtk_spm_regs, ext_int_wakeup_req_clr, 0x250); +check_member(mtk_spm_regs, mp0_cpu0_irq_mask, 0x260); +check_member(mtk_spm_regs, root_core_addr, 0x2a4); check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x02d0); -check_member(mtk_spm_regs, peri_pwr_con, 0x03c8); +check_member(mtk_spm_regs, peri_pwr_con, 0x3c8); +check_member(mtk_spm_regs, spm_mem_ck_sel, 0x400); +check_member(mtk_spm_regs, spm_force_dvfs, 0x4fc); +check_member(mtk_spm_regs, spm_sw_flag_0, 0x600); +check_member(mtk_spm_regs, spm_sw_flag_1, 0x608); +check_member(mtk_spm_regs, spm_sw_rsv_7, 0x62c); +check_member(mtk_spm_regs, spm_sw_rsv_8, 0x630); +check_member(mtk_spm_regs, spm_ack_chk_con_3, 0x960); +check_member(mtk_spm_regs, spm_ack_chk_timer_3, 0x96c); +check_member(mtk_spm_regs, sys_timer_con, 0x98c); +check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xa00); +check_member(mtk_spm_regs, md32pcm_dma0_src, 0xc00); +check_member(mtk_spm_regs, md32pcm_dma0_dst, 0xc04); +check_member(mtk_spm_regs, md32pcm_dma0_wppt, 0xc08); +check_member(mtk_spm_regs, md32pcm_dma0_wpto, 0xc0c); +check_member(mtk_spm_regs, md32pcm_dma0_count, 0xc10); +check_member(mtk_spm_regs, md32pcm_dma0_con, 0xc14); +check_member(mtk_spm_regs, md32pcm_dma0_start, 0xc18); +check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xc24); static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; +struct spm_desc { + const char *version; + u32 pmem_words; + u32 total_words; + u32 pmem_start; + u32 dmem_start; +}; + +int spm_init(void); + #endif /* SOC_MEDIATEK_MT8192_SPM_H */ diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c new file mode 100644 index 0000000..578a637 --- /dev/null +++ b/src/soc/mediatek/mt8192/spm.c @@ -0,0 +1,1085 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <cbfs.h> +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/spm.h> +#include <timer.h> + +static const u32 spm_firmware_binary[] = { + 0x3200001e, 0x6a00001e, 0x6e00001e, 0x6800001e, 0x6200001e, 0x6000001e, + 0x5e00001e, 0x5c00001e, 0x6000001e, 0x5800001e, 0x5600001e, 0x5400001e, + 0x5200001e, 0x5000001e, 0x4e00001e, 0x4c00001e, 0xd402001e, 0xee01001e, + 0x3a03001e, 0x0002001e, 0x3609001e, 0xfa01001e, 0xf601001e, 0xf201001e, + 0xee01001e, 0x000f0f98, 0x300d0e00, 0x000fee00, 0x380d0100, 0x000f1160, + 0x380d0200, 0x001c22d8, 0x01041218, 0x1c0423e1, 0x000c3262, 0x801c3303, + 0xf0064014, 0x00090104, 0x831d2201, 0x801c40f8, 0xd0066010, 0x00090101, + 0x831d3301, 0x150460f8, 0x000d0140, 0x18041101, 0x03931020, 0x001f0493, + 0x1393b912, 0x0400001f, 0x0000001e, 0xc0051198, 0x3fa02000, 0x00008005, + 0x0000a005, 0x0000a005, 0x0000a005, 0xe1a70292, 0x0300f2a7, 0x82ac018c, + 0x84ad03ad, 0x86ae05ae, 0x02ace2a5, 0x018b0300, 0x000802a8, 0x02ac2201, + 0xf2a5e1a5, 0xa005ee97, 0x00000000, 0x01200000, 0x31060013, 0x0621500f, + 0x3f200040, 0x010d0900, 0x07a8a80f, 0xa80d6188, 0x250f77a8, 0x250d0625, + 0x87b46625, 0x2fa086b4, 0x06ac87b4, 0x7f0cbc13, 0x0621500f, 0x3f200040, + 0x07a8a80f, 0x010d0900, 0x8a0d6188, 0x8a0f778a, 0x250f088a, 0xa80d0625, + 0x87b488a8, 0x57520200, 0x2fa086b4, 0x07ac88b4, 0x01000200, 0x31060013, + 0x0621500f, 0x3f200040, 0x0710200f, 0x01100900, 0x720d6188, 0xf3017744, + 0xf70696c5, 0xf89f7190, 0x6150f006, 0x06ff080f, 0x66ffbb0d, 0x8150f006, + 0xc7b3f501, 0x81ecfc06, 0xf80ff001, 0xf10606b5, 0x2fa07150, 0x8110f006, + 0x008008ac, 0x01000200, 0x13060011, 0x0721500f, 0x3f200040, 0x01100900, + 0x0810200f, 0x1e0d7188, 0xfe0f8804, 0x3c0d07ff, 0xf0017758, 0xf706a200, + 0x000f8190, 0xf006063c, 0x380d7150, 0xf00f663c, 0xf006073c, 0x180d2150, + 0xfc06773c, 0xf00121ec, 0x06b51800, 0x7150f106, 0xf0062fa0, 0x08ac8110, + 0x81890300, 0xc8890300, 0x0f0f07a8, 0xff0d01ff, 0xf00f16ff, 0x718a0100, + 0x0700300f, 0x774c680d, 0x61a871ac, 0x71280b45, 0x618b2fa0, 0x008061b6, + 0x01800000, 0x08002fa0, 0x00070600, 0x00806165, 0x01800000, 0x800cc0f3, + 0x11bb1100, 0x01800000, 0x06000800, 0x0700300f, 0x778c640d, 0x61640007, + 0x000c61a8, 0x9f1c11f0, 0x3fa030fa, 0x00803fa0, 0xa0c921a8, 0x02202fa0, + 0x21ac1144, 0x80c921a8, 0x31a821ac, 0x31b408c9, 0x2fa031a8, 0x31b680c9, + 0x31681e04, 0x0600300f, 0x668c6908, 0x2fa008c9, 0x50ac51ac, 0x08c921a8, + 0x21a821b4, 0x21b480c9, 0x20c921a8, 0x21a821b4, 0x21b490c9, 0x2fa021a8, + 0x21b698c9, 0x0f0d21a8, 0x21b41100, 0x08c921a8, 0x21a821b4, 0x21b420c9, + 0x80c921a8, 0x21a821b4, 0x21b490c9, 0x2fa021a8, 0x21b698c9, 0x81860300, + 0x000c01a8, 0x31bc1104, 0x3f200040, 0x0100300f, 0x1120640d, 0x9dc906a8, + 0x02202fa0, 0x06b66633, 0x28c921a8, 0x21a821b4, 0x21b4b0c9, 0x2fa021a8, + 0x21b6c8c9, 0x0100300f, 0x11346008, 0x0600f000, 0x07160b0f, 0x7708000d, + 0x6110f006, 0x8734fb4f, 0x71ecff06, 0x6110f006, 0x87b42fa0, 0x008007ac, + 0x0100300f, 0x11346008, 0x0600f000, 0x07160b0f, 0x7708000d, 0x6110f006, + 0x8734fb4f, 0x71ecff06, 0x6110f006, 0x87b42fa0, 0x008007ac, 0x0100300f, + 0x1150680d, 0x0700100f, 0x87c908a8, 0x00000fc9, 0xf1060210, 0x040081d0, + 0x87b50801, 0x86890300, 0x21d4f206, 0x56a808ac, 0x6600100c, 0x0700300f, + 0x06a846bc, 0x06ac1dc9, 0x01004000, 0x0600300f, 0x66b0600d, 0x12650007, + 0x78be58a8, 0x00008005, 0x831c58a8, 0x00a000fb, 0x12640007, 0x0100300f, + 0x1134660d, 0x890406a8, 0x831c66fc, 0x2fa0c0fa, 0x71b06008, 0x008000ac, + 0xe1a70292, 0xf6270b4c, 0x01140000, 0x40f328f2, 0xe1a5f6a5, 0xa005ee97, + 0x00800000, 0x0000a005, 0x0000a005, 0x0000a005, 0x0000a005, 0x0000a005, + 0x0100300f, 0x0300100f, 0x18086a08, 0x37003f0d, 0x101ac014, 0x06001000, + 0x00a08049, 0x71ac3044, 0x28584006, 0x4006e2b4, 0xe2b4285c, 0x06100000, + 0x31803f08, 0x87b435f3, 0x87b475f3, 0x87b4b5f3, 0x87b4f5f3, 0x76440007, + 0x000787b4, 0x87b47645, 0x76460007, 0x000787b4, 0x87b47647, 0x76480007, + 0x000787b4, 0x87b47649, 0x764a0007, 0x2fa087b4, 0x66510007, 0x008006ac, + 0x0000a4b9, 0x31a80114, 0x31c01120, 0x31a831ac, 0x11bd8904, 0x119c8904, + 0x312c0040, 0x890431a8, 0x831c11fe, 0x31a820fa, 0x11bc8904, 0x89042fa0, + 0x31ac119d, 0x90f268f3, 0x831c68f3, 0x3fa0c0fe, 0x01100000, 0x0697010f, + 0x01600007, 0x07ff010f, 0x68721b4c, 0x00072fa0, 0x28f27166, 0x300f0192, + 0x6b0d0800, 0x424c8800, 0xfd0fffa7, 0x74a801ff, 0x11ebff0d, 0x0499418a, + 0x1810f206, 0x01540900, 0x0400f5b4, 0xf4b40500, 0x0416000f, 0x1200f1b4, + 0xf5b401a8, 0xf1b4f4b4, 0x03ff1f0f, 0x31f8ff0d, 0xff06f0b4, 0xf80608d8, + 0x4b061800, 0x0300180c, 0x03004388, 0x03008287, 0xf94f078a, 0x030021ac, + 0x10ac0688, 0x01140000, 0x0b4c60ac, 0x0007502c, 0x00070163, 0x28f20162, + 0x18004606, 0x11998904, 0x02800000, 0xaeff1f17, 0x18007606, 0x01800000, + 0x9172fb4f, 0x170b0000, 0x61650007, 0x68004b06, 0x4b0668f2, 0x00076804, + 0x4b066164, 0x00076820, 0x7b066171, 0xffa57828, 0xfe972fa0, 0x00800080, + 0xd6a70b92, 0x76401504, 0xc4a7b3a7, 0x63401504, 0x54401504, 0x300f66a7, + 0x6d0d0600, 0x91a76600, 0x74a7f8a7, 0xe7a7a2a7, 0x83a75fa7, 0x9ec957a8, + 0x0100020f, 0x7600fd06, 0x0ec957a8, 0x1114000d, 0x7600f106, 0x718b57a8, + 0x08adde0f, 0x87adde0d, 0x16fcf906, 0x4f0657ac, 0x40801630, 0x0400300f, + 0x300fa1bc, 0x680d0100, 0x06a81150, 0x66938904, 0x06360040, 0xfafe1f1f, + 0x0600500f, 0x41006c08, 0x6600600d, 0x0700100f, 0x78003a0d, 0x000086b4, + 0x08b506b9, 0x08140000, 0x380087b7, 0x06b5e720, 0x06000800, 0x87b488b4, + 0x66a506ac, 0x83a574a5, 0x67201804, 0x45201804, 0x36201804, 0x91a55fa5, + 0xe7a5a2a5, 0xd6a5f8a5, 0xb3a5c4a5, 0xa0055e97, 0x00800000, 0xf8a70592, + 0x0800300f, 0x6a08d6a7, 0xe04b8620, 0xe7a7b1a7, 0x56a950ac, 0x06a806ac, + 0x6608c6b8, 0x01a88734, 0x864c680d, 0x420661ac, 0x0ba11718, 0x119b8904, + 0x81346608, 0x8650680d, 0x420600ac, 0x40c9111c, 0x87306d08, 0x880c0000, + 0x68ac51ac, 0xd6a5b1a5, 0xf8a5e7a5, 0xa005be97, 0x00800000, 0x03000192, + 0xffa78889, 0x200c71a8, 0x91ba1100, 0x0100300f, 0x11346008, 0x0600f000, + 0x062c0040, 0x02800000, 0x01200000, 0x06000100, 0x0540000f, 0x12650007, + 0x62640007, 0x52640007, 0x00208249, 0xb6fe1f17, 0xc3300000, 0x0700300f, + 0x7700660d, 0x52650007, 0x50c961a8, 0x61aa61b6, 0xffa571ac, 0xfe972fa0, + 0x00800080, 0x38f00049, 0xffa704f0, 0x00c971a8, 0xe3050000, 0x71a871b4, + 0xff0188c9, 0x1f17f700, 0x71b495fe, 0x178a71a8, 0xffa577b6, 0xfe972fa0, + 0x00800080, 0x37f00049, 0x61a8ffa7, 0xd1b94080, 0xc014ffa5, 0x00800812, + 0x00a0204c, 0x880466a8, 0x11866601, 0x049366ac, 0x78fe1f17, 0xc3090000, + 0x000d61a8, 0x61b41106, 0x80c961a8, 0xffa561b6, 0xfe972fa0, 0x00200040, + 0xfe972fa0, 0x00800080, 0x37f00049, 0x61a8ffa7, 0x80144080, 0xffa5204e, + 0x0810c014, 0x41980080, 0x880466a8, 0x11866601, 0x000066ac, 0xc0f30180, + 0x1130000c, 0x200c8414, 0xc3090000, 0x00a0a14d, 0x48fe1f17, 0x00208249, + 0x000d61a8, 0x61b41106, 0x80c961a8, 0xffa561b6, 0xfe972fa0, 0x00200040, + 0xfe972fa0, 0x00800080, 0xffa70192, 0x000c21a8, 0x84141120, 0xffa5200e, + 0xfe972fa0, 0x00200040, 0x21a89b49, 0x000048c9, 0x61b40680, 0x000cc5f3, + 0x00001130, 0x841cc309, 0x439b2006, 0x1afe1f17, 0x00208249, 0x30c961a8, + 0x61a861b4, 0x61b6a8c9, 0x2fa0ffa5, 0x0080fe97, 0x006d8014, 0x07140000, + 0x0700300f, 0x7780690d, 0x112061a8, 0x61ac61c0, 0x890461a8, 0x890411bd, + 0x61ac119c, 0x17844d06, 0x1102000c, 0xfd0881bb, 0x300f7184, 0x680d0800, + 0x00a08850, 0x890466a8, 0x76bc66fe, 0x890476a8, 0xc349629c, 0x52b60020, + 0x000c06a8, 0x831c6602, 0x00a0c0e6, 0x890461a8, 0x004011bc, 0x89042f20, + 0x61b6119d, 0xaef246f3, 0x418a21a8, 0x51fe7f1d, 0x46f32fa0, 0x07620007, + 0x4670ac49, 0x0200300f, 0x2204670d, 0x07003000, 0x718a11a8, 0x20fc8315, + 0x0100300f, 0x12006708, 0x124c2498, 0x670d13ac, 0x1f161304, 0x100fabff, + 0x00800700, 0x300f0192, 0x600d0100, 0x93bb11dc, 0x8949ffa7, 0x049908f0, + 0x21a8824c, 0x080f18c9, 0x21ac0700, 0x96ff1f17, 0x46920000, 0x13744706, + 0x770668c9, 0xffa51374, 0xfe972fa0, 0x00200040, 0x05f08949, 0x0870824c, + 0xcc6421a8, 0x040f0020, 0x21ac0700, 0x7eff1f17, 0x46920000, 0x13744706, + 0x770670c9, 0xffa51374, 0xfe972fa0, 0x00800080, 0x300f0192, 0x600d0b00, + 0xf000b934, 0x0b0f0100, 0x000d0616, 0xffa76a08, 0x1910f006, 0xa904f006, + 0xa9ecff06, 0x19084106, 0x51b84080, 0x2fa0ffa5, 0x0080fe97, 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0x00a00100, + 0x54f21f17, 0x1374630d, 0x01a8e1a5, 0x16948904, 0x06ace1a5, 0x01a8f1a5, + 0x11fe8904, 0x00a041be, 0x18f81f1f, 0x01a8f1a5, 0x11fb8904, 0x00a041be, + 0xe2ef1f1f, 0x01a8f1a5, 0x11ff8904, 0x00a041be, 0x12f91f1f, 0x01a8c1a5, + 0x11ff8904, 0x4c0f61b8, 0x0b4c0156, 0x06ac0020, 0x01564c0f, 0x0600a000, + 0x0700800f, 0x080a800f, 0x87af06af, 0x082f0040, 0xb2f51f17, 0x03800000, + 0x0794010f, 0x01100000, 0x86000400, 0x71640007, 0x07100000, 0xf206b1a5, + 0xf00671d4, 0x00006130, 0xadf30610, 0x66b38904, 0x0000aef2, 0x06acf60f, + 0x06100000, 0x8904adf3, 0xaef266b6, 0xf60f0000, 0x000006ac, 0xadf30610, + 0x66b58904, 0x0000aef2, 0x06acf60f, 0x01a8f1a5, 0x11f38904, 0x500fc1bc, + 0x1b0d0100, 0x06a811cc, 0x86b715c9, 0x866406a8, 0x06b600a0, 0x0100300f, + 0x1140610d, 0x61fcc406, 0x4a0686b4, 0xf30661e0, 0xfa0661ec, 0x7c060100, + 0x06a80184, 0x06ac0dc9, 0x01a8f1a5, 0x1100020c, 0x20c8801c, 0x0100510f, + 0x113cb00d, 0x040c01a8, 0x71ba1181, 0x0600510f, 0xc1030b00, 0x00ac6188, + 0x0100510f, 0x113cb10d, 0x040c01a8, 0x71ba1181, 0x0600510f, 0xc1130b00, + 0x00ac6188, 0x0100510f, 0x113cb20d, 0x040c01a8, 0x71ba1181, 0x0600510f, + 0xc1230b00, 0x00ac6188, 0x0100510f, 0x113cb30d, 0x040c01a8, 0x71ba1181, + 0x0600510f, 0xc1330b00, 0x00ac6188, 0x0127510f, 0x113c800d, 0x040c01a8, + 0x71ba1181, 0x0627510f, 0xc1030800, 0x00ac6188, 0x0127510f, 0x113c810d, + 0x040c01a8, 0x71ba1181, 0x0627510f, 0xc1130800, 0x00ac6188, 0x0127510f, + 0x113c820d, 0x040c01a8, 0x71ba1181, 0x0627510f, 0xc1230800, 0x00ac6188, + 0x00000593, 0x1f174410, 0xf398f9f1, 0x1f168fa5, 0x8e97ebf0, 0x801d43bc, + 0x00a06112, 0x01800000, 0x0600020f, 0x68720040, 0x81890300, 0x040c01a8, + 0x31be1100, 0x3f200040, 0x6608801d, 0x3f200040, 0x6708801d, 0x3f200040, + 0x00002fa0, 0x80f20180, 0x0100300f, 0x11746408, 0xf6af0000, 0x07cccc0f, + 0x77cccc0d, 0xf0062fa0, 0x07ac6128, 0x09800000, 0x00a00049, 0x0700300f, + 0x77a0640d, 0x19400007, 0x8904ffa7, 0x61a81afe, 0xc6ff1f17, 0x13082120, + 0x0800040f, 0x0200100f, 0x0400080f, 0x200fcab8, 0x00070500, 0x00078962, + 0x00072962, 0x0ba14961, 0x59610007, 0x89610007, 0x29610007, 0x49620007, + 0x59620007, 0x1c0d61a8, 0x05001100, 0x61b606bc, 0x619d8904, 0xff017188, + 0x07a8b67f, 0xff0f768a, 0x86b407ef, 0x76fff70d, 0x768a07a8, 0xffa506b6, + 0xfe972fa0, 0x00800080, 0xcfa70492, 0x78ef1f1f, 0xb6ff1f1f, 0xa6ff1f1f, + 0x81890300, 0x0300f1a7, 0xe1a78186, 0x01800000, 0x06200000, 0x61640007, + 0x01100000, 0x0694010f, 0x61650007, 0x01160b0f, 0x0600300f, 0x110c000d, + 0x66446008, 0x400651ac, 0x831576dc, 0x010fe0fa, 0x300f0794, 0x60080600, + 0x51ac6648, 0x01100000, 0x71640007, 0x16b84506, 0x61acf7a5, 0x16c04506, + 0x51b4e6a5, 0x66a8d6a7, 0x0100f80f, 0x1f17618b, 0x61acbded, 0x01a8f1a5, + 0x1100040c, 0x00a041be, 0x48fc1f1f, 0x01a8f1a5, 0x1100040c, 0xf1a581b8, + 0x000c01a8, 0x31be1120, 0x66ee1f1f, 0x01a8d1a5, 0x1140000c, 0x20688314, + 0x0600800f, 0x07800000, 0xcfa58049, 0x67670007, 0x3f20e74b, 0x01000100, + 0x01000201, 0x02010201, 0x01000402, 0x02010402, 0x04020402, 0x01000803, + 0x02010803, 0x04020803, 0x01001004, 0x02011004, 0x04021004, 0x08031004, + 0x01002005, 0x02012005, 0x04022005, 0x08032005, 0x01004006, 0x02014006, + 0x04024006, 0x08034006 +}; + +static struct spm_desc spm_firmware = { + .version = "pcm_suspend_v1.43_no_GPU_WAYEN", + .pmem_words = 0x9bf, + .total_words = 0x9d4, + .pmem_start = 0x10000000, + .dmem_start = 0x10003800 +}; + +static struct pwr_ctrl spm_init_ctrl = { + /* Auto-gen Start */ + + .pcm_flags = SPM_FLAG_DISABLE_VCORE_DVS | SPM_FLAG_DISABLE_VCORE_DFS | + SPM_FLAG_RUN_COMMON_SCENARIO, + + /* SPM_AP_STANDBY_CON */ + .reg_wfi_op = 0, + .reg_wfi_type = 0, + .reg_mp0_cputop_idle_mask = 0, + .reg_mp1_cputop_idle_mask = 0, + .reg_mcusys_idle_mask = 0, + .reg_md_apsrc_1_sel = 0, + .reg_md_apsrc_0_sel = 0, + .reg_conn_apsrc_sel = 0, + + /* SPM_SRC6_MASK */ + .reg_dpmaif_srcclkena_mask_b = 1, + .reg_dpmaif_infra_req_mask_b = 1, + .reg_dpmaif_apsrc_req_mask_b = 1, + .reg_dpmaif_vrf18_req_mask_b = 1, + .reg_dpmaif_ddr_en_mask_b = 1, + + /* SPM_SRC_REQ */ + .reg_spm_apsrc_req = 0, + .reg_spm_f26m_req = 0, + .reg_spm_infra_req = 0, + .reg_spm_vrf18_req = 0, + .reg_spm_ddr_en_req = 1, + .reg_spm_dvfs_req = 0, + .reg_spm_sw_mailbox_req = 0, + .reg_spm_sspm_mailbox_req = 0, + .reg_spm_adsp_mailbox_req = 0, + .reg_spm_scp_mailbox_req = 0, + + /* SPM_SRC_MASK */ + .reg_md_srcclkena_0_mask_b = 1, + .reg_md_srcclkena2infra_req_0_mask_b = 0, + .reg_md_apsrc2infra_req_0_mask_b = 1, + .reg_md_apsrc_req_0_mask_b = 1, + .reg_md_vrf18_req_0_mask_b = 1, + .reg_md_ddr_en_0_mask_b = 1, + .reg_md_srcclkena_1_mask_b = 0, + .reg_md_srcclkena2infra_req_1_mask_b = 0, + .reg_md_apsrc2infra_req_1_mask_b = 0, + .reg_md_apsrc_req_1_mask_b = 0, + .reg_md_vrf18_req_1_mask_b = 0, + .reg_md_ddr_en_1_mask_b = 0, + .reg_conn_srcclkena_mask_b = 1, + .reg_conn_srcclkenb_mask_b = 0, + .reg_conn_infra_req_mask_b = 1, + .reg_conn_apsrc_req_mask_b = 1, + .reg_conn_vrf18_req_mask_b = 1, + .reg_conn_ddr_en_mask_b = 1, + .reg_conn_vfe28_mask_b = 0, + .reg_srcclkeni0_srcclkena_mask_b = 1, + .reg_srcclkeni0_infra_req_mask_b = 1, + .reg_srcclkeni1_srcclkena_mask_b = 0, + .reg_srcclkeni1_infra_req_mask_b = 0, + .reg_srcclkeni2_srcclkena_mask_b = 0, + .reg_srcclkeni2_infra_req_mask_b = 0, + .reg_infrasys_apsrc_req_mask_b = 0, + .reg_infrasys_ddr_en_mask_b = 1, + .reg_md32_srcclkena_mask_b = 1, + .reg_md32_infra_req_mask_b = 1, + .reg_md32_apsrc_req_mask_b = 1, + .reg_md32_vrf18_req_mask_b = 1, + .reg_md32_ddr_en_mask_b = 1, + + /* SPM_SRC2_MASK */ + .reg_scp_srcclkena_mask_b = 1, + .reg_scp_infra_req_mask_b = 1, + .reg_scp_apsrc_req_mask_b = 1, + .reg_scp_vrf18_req_mask_b = 1, + .reg_scp_ddr_en_mask_b = 1, + .reg_audio_dsp_srcclkena_mask_b = 1, + .reg_audio_dsp_infra_req_mask_b = 1, + .reg_audio_dsp_apsrc_req_mask_b = 1, + .reg_audio_dsp_vrf18_req_mask_b = 1, + .reg_audio_dsp_ddr_en_mask_b = 1, + .reg_ufs_srcclkena_mask_b = 1, + .reg_ufs_infra_req_mask_b = 1, + .reg_ufs_apsrc_req_mask_b = 1, + .reg_ufs_vrf18_req_mask_b = 1, + .reg_ufs_ddr_en_mask_b = 1, + .reg_disp0_apsrc_req_mask_b = 1, + .reg_disp0_ddr_en_mask_b = 1, + .reg_disp1_apsrc_req_mask_b = 1, + .reg_disp1_ddr_en_mask_b = 1, + .reg_gce_infra_req_mask_b = 1, + .reg_gce_apsrc_req_mask_b = 1, + .reg_gce_vrf18_req_mask_b = 1, + .reg_gce_ddr_en_mask_b = 1, + .reg_apu_srcclkena_mask_b = 1, + .reg_apu_infra_req_mask_b = 1, + .reg_apu_apsrc_req_mask_b = 1, + .reg_apu_vrf18_req_mask_b = 1, + .reg_apu_ddr_en_mask_b = 1, + .reg_cg_check_srcclkena_mask_b = 0, + .reg_cg_check_apsrc_req_mask_b = 0, + .reg_cg_check_vrf18_req_mask_b = 0, + .reg_cg_check_ddr_en_mask_b = 0, + + /* SPM_SRC3_MASK */ + .reg_dvfsrc_event_trigger_mask_b = 1, + .reg_sw2spm_int0_mask_b = 0, + .reg_sw2spm_int1_mask_b = 0, + .reg_sw2spm_int2_mask_b = 0, + .reg_sw2spm_int3_mask_b = 0, + .reg_sc_adsp2spm_wakeup_mask_b = 0, + .reg_sc_sspm2spm_wakeup_mask_b = 0, + .reg_sc_scp2spm_wakeup_mask_b = 0, + .reg_csyspwrreq_mask = 1, + .reg_spm_srcclkena_reserved_mask_b = 0, + .reg_spm_infra_req_reserved_mask_b = 0, + .reg_spm_apsrc_req_reserved_mask_b = 0, + .reg_spm_vrf18_req_reserved_mask_b = 0, + .reg_spm_ddr_en_reserved_mask_b = 0, + .reg_mcupm_srcclkena_mask_b = 1, + .reg_mcupm_infra_req_mask_b = 1, + .reg_mcupm_apsrc_req_mask_b = 1, + .reg_mcupm_vrf18_req_mask_b = 1, + .reg_mcupm_ddr_en_mask_b = 1, + .reg_msdc0_srcclkena_mask_b = 1, + .reg_msdc0_infra_req_mask_b = 1, + .reg_msdc0_apsrc_req_mask_b = 1, + .reg_msdc0_vrf18_req_mask_b = 1, + .reg_msdc0_ddr_en_mask_b = 1, + .reg_msdc1_srcclkena_mask_b = 1, + .reg_msdc1_infra_req_mask_b = 1, + .reg_msdc1_apsrc_req_mask_b = 1, + .reg_msdc1_vrf18_req_mask_b = 1, + .reg_msdc1_ddr_en_mask_b = 1, + + /* SPM_SRC4_MASK */ + .ccif_event_mask_b = 0xFFF, + .reg_bak_psri_srcclkena_mask_b = 0, + .reg_bak_psri_infra_req_mask_b = 0, + .reg_bak_psri_apsrc_req_mask_b = 0, + .reg_bak_psri_vrf18_req_mask_b = 0, + .reg_bak_psri_ddr_en_mask_b = 0, + .reg_dramc0_md32_infra_req_mask_b = 1, + .reg_dramc0_md32_vrf18_req_mask_b = 0, + .reg_dramc1_md32_infra_req_mask_b = 1, + .reg_dramc1_md32_vrf18_req_mask_b = 0, + .reg_conn_srcclkenb2pwrap_mask_b = 0, + .reg_dramc0_md32_wakeup_mask = 1, + .reg_dramc1_md32_wakeup_mask = 1, + + /* SPM_SRC5_MASK */ + .reg_mcusys_merge_apsrc_req_mask_b = 0x11, + .reg_mcusys_merge_ddr_en_mask_b = 0x11, + .reg_msdc2_srcclkena_mask_b = 1, + .reg_msdc2_infra_req_mask_b = 1, + .reg_msdc2_apsrc_req_mask_b = 1, + .reg_msdc2_vrf18_req_mask_b = 1, + .reg_msdc2_ddr_en_mask_b = 1, + .reg_pcie_srcclkena_mask_b = 1, + .reg_pcie_infra_req_mask_b = 1, + .reg_pcie_apsrc_req_mask_b = 1, + .reg_pcie_vrf18_req_mask_b = 1, + .reg_pcie_ddr_en_mask_b = 1, + + /* SPM_WAKEUP_EVENT_MASK */ + .reg_wakeup_event_mask = 0xEFFFFFFF, + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + .reg_ext_wakeup_event_mask = 0xFFFFFFFF, + + /* Auto-gen End */ +}; + +static void spm_set_power_control(struct pwr_ctrl *pwrctrl) +{ + /* Auto-gen Start */ + + /* SPM_AP_STANDBY_CON */ + write32(&mtk_spm->spm_ap_standby_con, + ((pwrctrl->reg_wfi_op & 0x1) << 0) | + ((pwrctrl->reg_wfi_type & 0x1) << 1) | + ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) | + ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) | + ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) | + ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) | + ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) | + ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29)); + + /* SPM_SRC6_MASK */ + write32(&mtk_spm->spm_src6_mask, + ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 0) | + ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_dpmaif_ddr_en_mask_b & 0x1) << 4)); + + /* SPM_SRC_REQ */ + write32(&mtk_spm->spm_src_req, + ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) | + ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) | + ((pwrctrl->reg_spm_infra_req & 0x1) << 3) | + ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) | + ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) | + ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) | + ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) | + ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) | + ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) | + ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12)); + + /* SPM_SRC_MASK */ + write32(&mtk_spm->spm_src_mask, + ((pwrctrl->reg_md_srcclkena_0_mask_b & 0x1) << 0) | + ((pwrctrl->reg_md_srcclkena2infra_req_0_mask_b & 0x1) << 1) | + ((pwrctrl->reg_md_apsrc2infra_req_0_mask_b & 0x1) << 2) | + ((pwrctrl->reg_md_apsrc_req_0_mask_b & 0x1) << 3) | + ((pwrctrl->reg_md_vrf18_req_0_mask_b & 0x1) << 4) | + ((pwrctrl->reg_md_ddr_en_0_mask_b & 0x1) << 5) | + ((pwrctrl->reg_md_srcclkena_1_mask_b & 0x1) << 6) | + ((pwrctrl->reg_md_srcclkena2infra_req_1_mask_b & 0x1) << 7) | + ((pwrctrl->reg_md_apsrc2infra_req_1_mask_b & 0x1) << 8) | + ((pwrctrl->reg_md_apsrc_req_1_mask_b & 0x1) << 9) | + ((pwrctrl->reg_md_vrf18_req_1_mask_b & 0x1) << 10) | + ((pwrctrl->reg_md_ddr_en_1_mask_b & 0x1) << 11) | + ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) | + ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) | + ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 14) | + ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 16) | + ((pwrctrl->reg_conn_ddr_en_mask_b & 0x1) << 17) | + ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 18) | + ((pwrctrl->reg_srcclkeni0_srcclkena_mask_b & 0x1) << 19) | + ((pwrctrl->reg_srcclkeni0_infra_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_srcclkeni1_srcclkena_mask_b & 0x1) << 21) | + ((pwrctrl->reg_srcclkeni1_infra_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_srcclkeni2_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_srcclkeni2_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 26) | + ((pwrctrl->reg_md32_srcclkena_mask_b & 0x1) << 27) | + ((pwrctrl->reg_md32_infra_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_md32_apsrc_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_md32_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_md32_ddr_en_mask_b & 0x1) << 31)); + + /* SPM_SRC2_MASK */ + write32(&mtk_spm->spm_src2_mask, + ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) | + ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) | + ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) | + ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) | + ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 4) | + ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) | + ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) | + ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) | + ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) | + ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 9) | + ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) | + ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) | + ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) | + ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) | + ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 14) | + ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) | + ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 16) | + ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 18) | + ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_gce_ddr_en_mask_b & 0x1) << 22) | + ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 27) | + ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) | + ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_cg_check_ddr_en_mask_b & 0x1) << 31)); + + /* SPM_SRC3_MASK */ + write32(&mtk_spm->spm_src3_mask, + ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) | + ((pwrctrl->reg_sw2spm_int0_mask_b & 0x1) << 1) | + ((pwrctrl->reg_sw2spm_int1_mask_b & 0x1) << 2) | + ((pwrctrl->reg_sw2spm_int2_mask_b & 0x1) << 3) | + ((pwrctrl->reg_sw2spm_int3_mask_b & 0x1) << 4) | + ((pwrctrl->reg_sc_adsp2spm_wakeup_mask_b & 0x1) << 5) | + ((pwrctrl->reg_sc_sspm2spm_wakeup_mask_b & 0xf) << 6) | + ((pwrctrl->reg_sc_scp2spm_wakeup_mask_b & 0x1) << 10) | + ((pwrctrl->reg_csyspwrreq_mask & 0x1) << 11) | + ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 12) | + ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 13) | + ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 14) | + ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 15) | + ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 16) | + ((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) | + ((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_mcupm_ddr_en_mask_b & 0x1) << 21) | + ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) | + ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 26) | + ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) | + ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) | + ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) | + ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) | + ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 31)); + + /* SPM_SRC4_MASK */ + write32(&mtk_spm->spm_src4_mask, + ((pwrctrl->ccif_event_mask_b & 0xffff) << 0) | + ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) | + ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) | + ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) | + ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 20) | + ((pwrctrl->reg_dramc0_md32_infra_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_dramc0_md32_vrf18_req_mask_b & 0x1) << 22) | + ((pwrctrl->reg_dramc1_md32_infra_req_mask_b & 0x1) << 23) | + ((pwrctrl->reg_dramc1_md32_vrf18_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) | + ((pwrctrl->reg_dramc0_md32_wakeup_mask & 0x1) << 26) | + ((pwrctrl->reg_dramc1_md32_wakeup_mask & 0x1) << 27)); + + /* SPM_SRC5_MASK */ + write32(&mtk_spm->spm_src5_mask, + ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) | + ((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) | + ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 18) | + ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 19) | + ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 20) | + ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 21) | + ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 22) | + ((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 23) | + ((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 24) | + ((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 25) | + ((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 26) | + ((pwrctrl->reg_pcie_ddr_en_mask_b & 0x1) << 27)); + + /* SPM_WAKEUP_EVENT_MASK */ + write32(&mtk_spm->spm_wakeup_event_mask, + ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0)); + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + write32(&mtk_spm->spm_wakeup_event_ext_mask, + ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0)); + + /* Auto-gen End */ +} + +static void spm_register_init(void) +{ + u32 reg; + + /* enable register control */ + write32(&mtk_spm->poweron_config_en, SPM_REGWR_CFG_KEY | + BCLK_CG_EN_LSB); + + /* init power control register */ + write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* reset PCM */ + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | REG_EVENT_LOCK_EN_LSB | + REG_SPM_SRAM_ISOINT_B_LSB | RG_AHBMIF_APBEN_LSB | + REG_MD32_APB_INTERNAL_EN_LSB); + + /* initial SPM CLK control register */ + write32(&mtk_spm->spm_clk_con, read32(&mtk_spm->spm_clk_con) | + REG_SYSCLK1_SRC_MD2_SRCCLKENA); + + /* clean wakeup event raw status */ + write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF); + + /* clean ISR status */ + write32(&mtk_spm->spm_irq_mask, ISRM_ALL); + write32(&mtk_spm->spm_irq_sta, ISRC_ALL); + write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL); + + /* init r7 with POWER_ON_VAL1 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* DDR EN de-bounce length to 5us */ + write32(&mtk_spm->ddr_en_dbc_con0, DDR_EN_DBC_CON0_DEF); + write32(&mtk_spm->ddr_en_dbc_con1, REG_ALL_DDR_EN_DBC_EN_LSB); + + /* Configure ARMPLL Control Mode for MCDI */ + write32(&mtk_spm->armpll_clk_sel, ARMPLL_CLK_SEL_DEF); + + /* Init for SPM Resource ACK */ + write32(&mtk_spm->spm_resource_ack_con0, SPM_RESOURCE_ACK_CON0_DEF); + write32(&mtk_spm->spm_resource_ack_con1, SPM_RESOURCE_ACK_CON1_DEF); + write32(&mtk_spm->spm_resource_ack_con2, SPM_RESOURCE_ACK_CON2_DEF); + write32(&mtk_spm->spm_resource_ack_con3, SPM_RESOURCE_ACK_CON3_DEF); + + /* Init VCORE DVFS Status */ + write32(&mtk_spm->spm_dvfs_misc, (read32(&mtk_spm->spm_dvfs_misc) & + ~(SPM_DVFS_FORCE_ENABLE_LSB)) | (SPM_DVFSRC_ENABLE_LSB)); + write32(&mtk_spm->spm_dvfs_level, SPM_DVFS_LEVEL_DEF); + write32(&mtk_spm->spm_dvs_dfs_level, SPM_DVS_DFS_LEVEL_DEF); + + write32(&mtk_spm->spm_ack_chk_sel_3, SPM_ACK_CHK_3_SEL_HW_S1); + write32(&mtk_spm->spm_ack_chk_timer_3, SPM_ACK_CHK_3_HW_S1_CNT); + + /* apm_hw_s1_state_monitor_pause */ + reg = read32(&mtk_spm->spm_ack_chk_con_3); + reg |= (SPM_ACK_CHK_3_CON_HW_MODE_TRIG | SPM_ACK_CHK_3_CON_CLR_ALL); + reg &= ~(SPM_ACK_CHK_3_CON_EN); + write32(&mtk_spm->spm_ack_chk_con_3, reg); +} + +static void spm_set_sysclk_settle(void) +{ + u32 settle; + + write32(&mtk_spm->spm_clk_settle, SPM_SYSCLK_SETTLE); + settle = read32(&mtk_spm->spm_clk_settle); +} + +static void spm_code_swapping(void) +{ + u32 mask; + + mask = read32(&mtk_spm->spm_wakeup_event_mask); + write32(&mtk_spm->spm_wakeup_event_mask, + (mask & ~SPM_WAKEUP_EVENT_MASK_BIT0)); + write32(&mtk_spm->spm_cpu_wakeup_event, 1); + write32(&mtk_spm->spm_cpu_wakeup_event, 0); + write32(&mtk_spm->spm_wakeup_event_mask, mask); +} + +static void spm_reset_and_init_pcm(void) +{ + bool first_load_fw = true; + u32 con1; + + /* check the SPM FW is run or not */ + if (read32(&mtk_spm->md32pcm_cfgreg_sw_rstn) & + MD32PCM_CFGREG_SW_RSTN_RUN) + first_load_fw = false; + + if (!first_load_fw) { + spm_code_swapping(); + /* Backup PCM r0 -> SPM_POWER_ON_VAL0 before reset PCM`*/ + write32(&mtk_spm->spm_power_on_val0, + read32(&mtk_spm->pcm_reg0_data)); + } + + /* disable r0 and r7 to control power */ + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* disable pcm timer after leaving FW */ + write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | + (read32(&mtk_spm->pcm_con1) & ~RG_PCM_TIMER_EN_LSB)); + + /* reset PCM */ + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + /* init PCM_CON1 (disable PCM timer but keep PCM WDT setting) */ + con1 = read32(&mtk_spm->pcm_con1) & (RG_PCM_WDT_WAKE_LSB); + write32(&mtk_spm->pcm_con1, con1 | SPM_REGWR_CFG_KEY | + REG_EVENT_LOCK_EN_LSB | REG_SPM_SRAM_ISOINT_B_LSB | + RG_AHBMIF_APBEN_LSB | REG_MD32_APB_INTERNAL_EN_LSB); +} + +static void spm_kick_im_to_fetch(void) +{ + uintptr_t ptr; + u32 pmem_words; + u32 total_words; + u32 pmem_start; + u32 dmem_start; + u32 con0; + + ptr = (uintptr_t) spm_firmware_binary + 0x40000000; + pmem_words = spm_firmware.pmem_words; + total_words = spm_firmware.total_words; + pmem_start = spm_firmware.pmem_start; + dmem_start = spm_firmware.dmem_start; + + /* tell IM where is PCM code (use slave mode if code existed) */ + if (read32(&mtk_spm->md32pcm_dma0_src) != ptr || + read32(&mtk_spm->md32pcm_dma0_dst) != pmem_start || + read32(&mtk_spm->md32pcm_dma0_wppt) != pmem_words || + read32(&mtk_spm->md32pcm_dma0_wpto) != dmem_start || + read32(&mtk_spm->md32pcm_dma0_count) != total_words || + read32(&mtk_spm->md32pcm_dma0_con) != MD32PCM_DMA0_CON_VAL) { + write32(&mtk_spm->md32pcm_dma0_src, ptr); + write32(&mtk_spm->md32pcm_dma0_dst, pmem_start); + write32(&mtk_spm->md32pcm_dma0_wppt, pmem_words); + write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start); + write32(&mtk_spm->md32pcm_dma0_count, total_words); + write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL); + write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL); + } else { + write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) | + SPM_REGWR_CFG_KEY | RG_IM_SLAVE_LSB); + } + + /* kick IM to fetch (only toggle IM_KICK) */ + con0 = read32(&mtk_spm->pcm_con0); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); +} + +static void spm_init_pcm_register(void) +{ + /* init r0 with POWER_ON_VAL0 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val0)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* init r7 with POWER_ON_VAL1 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); +} + +static void spm_set_wakeup_event(struct pwr_ctrl *pwrctrl) +{ + u32 val, mask, isr; + + /* toggle event counter clear */ + write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) | + SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB); + + /* toggle for reset SYS TIMER start point */ + write32(&mtk_spm->sys_timer_con, read32(&mtk_spm->sys_timer_con) | + SYS_TIMER_START_EN_LSB); + + if (pwrctrl->timer_val_cust == 0) + val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; + else + val = pwrctrl->timer_val_cust; + + write32(&mtk_spm->pcm_timer_val, val); + + /* disable pcm timer */ + write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | + (read32(&mtk_spm->pcm_con1) & ~RG_PCM_TIMER_EN_LSB)); + + /* unmask AP wakeup source */ + if (pwrctrl->wake_src_cust == 0) + mask = pwrctrl->wake_src; + else + mask = pwrctrl->wake_src_cust; + + if (pwrctrl->reg_csyspwrreq_mask) + mask &= ~SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B; + + write32(&mtk_spm->spm_wakeup_event_mask, ~mask); + + /* unmask SPM ISR (keep TWAM setting) */ + isr = read32(&mtk_spm->spm_irq_mask); + write32(&mtk_spm->spm_irq_mask, isr | ISRM_RET_IRQ_AUX); + + /* toggle event counter clear */ + write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | + (read32(&mtk_spm->pcm_con1) & ~SPM_EVENT_COUNTER_CLR_LSB)); + + /* toggle for reset SYS TIMER start point */ + write32(&mtk_spm->sys_timer_con, read32(&mtk_spm->sys_timer_con) & + ~SYS_TIMER_START_EN_LSB); +} + +static void spm_set_pcm_flags(struct pwr_ctrl *pwrctrl) +{ + /* set PCM flags and data */ + if (pwrctrl->pcm_flags_cust_clr != 0) + pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr; + if (pwrctrl->pcm_flags_cust_set != 0) + pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set; + if (pwrctrl->pcm_flags1_cust_clr != 0) + pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr; + if (pwrctrl->pcm_flags1_cust_set != 0) + pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set; + + write32(&mtk_spm->spm_sw_flag_0, pwrctrl->pcm_flags); + write32(&mtk_spm->spm_sw_flag_1, pwrctrl->pcm_flags1); + write32(&mtk_spm->spm_sw_rsv_7, pwrctrl->pcm_flags); + write32(&mtk_spm->spm_sw_rsv_8, pwrctrl->pcm_flags1); +} + +static void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl) +{ + u32 con0, rstn; + + /* Waiting for loading SPMFW done*/ + while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0) + ; + + /* Init register to match PCM expectation */ + write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF); + write32(&mtk_spm->spm_bus_protect2_mask_b, + SPM_BUS_PROTECT2_MASK_B_DEF); + write32(&mtk_spm->pcm_reg_data_ini, 0); + + spm_set_pcm_flags(pwrctrl); + + /* Kick PCM to run (only toggle PCM_KICK) */ + con0 = read32(&mtk_spm->pcm_con0); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + /* Reset md32pcm */ + rstn = read32(&mtk_spm->md32pcm_cfgreg_sw_rstn); + write32(&mtk_spm->md32pcm_cfgreg_sw_rstn, + rstn | MD32PCM_CFGREG_SW_RSTN_RESET); + + /* Waiting for SPM init done */ + udelay(SPM_INIT_DONE_US); +} + +int spm_init(void) +{ + struct stopwatch sw; + + stopwatch_init(&sw); + + spm_register_init(); + spm_set_power_control(&spm_init_ctrl); + spm_set_sysclk_settle(); + spm_reset_and_init_pcm(); + spm_kick_im_to_fetch(); + spm_init_pcm_register(); + spm_set_wakeup_event(&spm_init_ctrl); + spm_kick_pcm_to_run(&spm_init_ctrl); + + printk(BIOS_INFO, "SPM: %s done in %ld msecs, %s, spm pc = 0x%x\n", + __func__, stopwatch_duration_msecs(&sw), spm_firmware.version, + read32(&mtk_spm->md32pcm_pc)); + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371 Gerrit-Change-Number: 46389 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 77

Change in coreboot[master]: soc/mediatek/mt8183/sspm.c: Use mtlib_load_and_run API
by Yidi Lin (Code Review) 10 Dec '20

10 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48233 ) Change subject: soc/mediatek/mt8183/sspm.c: Use mtlib_load_and_run API ...................................................................... soc/mediatek/mt8183/sspm.c: Use mtlib_load_and_run API Use mtlib_load_and_run API to load and run sspm firmware. TEST=emerge-kukui coreboot Change-Id: I63c4b99342bdebb2a94cbf0c6380b0a6817853e7 Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/sspm.c 2 files changed, 9 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/48233/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 43893c3..d2d0390 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -52,6 +52,7 @@ ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c +ramstage-y += ../common/mtlib.c ramstage-y += ../common/pmic_wrap.c ramstage-y += ../common/rtc.c rtc.c ramstage-y += soc.c diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c index efcf545..fca108b 100644 --- a/src/soc/mediatek/mt8183/sspm.c +++ b/src/soc/mediatek/mt8183/sspm.c @@ -1,29 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/barrier.h> -#include <cbfs.h> -#include <console/console.h> #include <device/mmio.h> +#include <soc/mtlib_common.h> #include <soc/sspm.h> -#include <string.h> -#define BUF_SIZE (64 * KiB) -static uint8_t sspm_bin[BUF_SIZE] __aligned(8); +#define SSPM_FW_FILE "sspm.bin" + +static void reset_sspm(void) +{ + write32(&mt8183_sspm->sw_rstn, 0x1); +} void sspm_init(void) { - const char *file_name = "sspm.bin"; - size_t fw_size = cbfs_boot_load_file(file_name, - sspm_bin, - sizeof(sspm_bin), - CBFS_TYPE_RAW); - - if (fw_size == 0) - die("SSPM file :sspm.bin not found."); - - memcpy((void *)SSPM_SRAM_BASE, sspm_bin, fw_size); - /* Memory barrier to ensure that all fw code is loaded - before we release the reset pin. */ - mb(); - write32(&mt8183_sspm->sw_rstn, 0x1); + mtlib_load_and_run(SSPM_FW_FILE, (void *)SSPM_SRAM_BASE, reset_sspm); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63c4b99342bdebb2a94cbf0c6380b0a6817853e7 Gerrit-Change-Number: 48233 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: soc/mediatek/mt8183: Add DRAM_DMA section
by Yidi Lin (Code Review) 10 Dec '20

10 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48232 ) Change subject: soc/mediatek/mt8183: Add DRAM_DMA section ...................................................................... soc/mediatek/mt8183: Add DRAM_DMA section mtlib_load_and_run uses DRAM_DMA section as CBFS buffer. The change "mediatek/mt8183: Remove DRAM_DMA section" is reverted for using mtlib_load_and_run. Unless this section is used by the DMA hardware, it is not necessary to be marked as non-cacheable resource. Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633 Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> --- A src/soc/mediatek/mt8183/include/soc/symbols.h M src/soc/mediatek/mt8183/memlayout.ld 2 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/48232/1 diff --git a/src/soc/mediatek/mt8183/include/soc/symbols.h b/src/soc/mediatek/mt8183/include/soc/symbols.h new file mode 100644 index 0000000..2c281b4 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/symbols.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_MEDIATEK_MT8183_SYMBOLS_H_ +#define _SOC_MEDIATEK_MT8183_SYMBOLS_H_ +#include <symbols.h> + +DECLARE_REGION(dram_dma) + +#endif /* _SOC_MEDIATEK_MT8183_SYMBOLS_H_ */ diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld index a266377..6a6b5b2 100644 --- a/src/soc/mediatek/mt8183/memlayout.ld +++ b/src/soc/mediatek/mt8183/memlayout.ld @@ -14,6 +14,11 @@ #define DRAM_INIT_CODE(addr, size) \ REGION(dram_init_code, addr, size, 4) +#define DRAM_DMA(addr, size) \ + REGION(dram_dma, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DRAM DMA buffer should be multiple of smallest page size (4K)!"); + SECTIONS { SRAM_START(0x00100000) @@ -36,7 +41,8 @@ SRAM_L2C_END(0x00280000) DRAM_START(0x40000000) - POSTRAM_CBFS_CACHE(0x40000000, 2M) + DRAM_DMA(0x40000000, 1M) + POSTRAM_CBFS_CACHE(0x40100000, 1M) RAMSTAGE(0x40200000, 256K) BL31(0x54600000, 0x60000) -- To view, visit https://review.coreboot.org/c/coreboot/+/48232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ce9f68883e2787ee7f3c5066f4c47c5ca315633 Gerrit-Change-Number: 48232 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 14

Change in coreboot[master]: soc/mediatek/common: A common API for loading the blob file
by Yidi Lin (Code Review) 10 Dec '20

10 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46930 ) Change subject: soc/mediatek/common: A common API for loading the blob file ...................................................................... soc/mediatek/common: A common API for loading the blob file load_blob_file is added for loading the blog file to the specified memory address. This function also measures the load time and the blob size. Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: Ie94001bbda25fe015f43172e92a1006e059de223 --- A src/soc/mediatek/common/include/soc/mtlib_common.h A src/soc/mediatek/common/mtlib.c M src/soc/mediatek/mt8192/Makefile.inc 3 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46930/1 diff --git a/src/soc/mediatek/common/include/soc/mtlib_common.h b/src/soc/mediatek/common/include/soc/mtlib_common.h new file mode 100644 index 0000000..3210468 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/mtlib_common.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MTLIB_COMMON_H +#define SOC_MEDIATEK_MTLIB_COMMON_H + +int load_blob_file(const char *name, unsigned long addr); + +#endif /* SOC_MEDIATEK_MTLIB_COMMON_H */ diff --git a/src/soc/mediatek/common/mtlib.c b/src/soc/mediatek/common/mtlib.c new file mode 100644 index 0000000..cdb748b --- /dev/null +++ b/src/soc/mediatek/common/mtlib.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbfs.h> +#include <console/console.h> +#include <soc/mtlib_common.h> +#include <timer.h> + +#define BUF_SIZE (128 * KiB) +static u8 blob_data[BUF_SIZE] __aligned(8); + +int load_blob_file(const char *name, unsigned long addr) +{ + struct stopwatch sw; + size_t blob_bytes; + + stopwatch_init(&sw); + + blob_bytes = cbfs_boot_load_file(name, blob_data, sizeof(blob_data), CBFS_TYPE_RAW); + if (blob_bytes == 0) { + printk(BIOS_ERR, "binary %s not found\n", name); + return CB_ERR; + } + + memcpy((void *)addr, blob_data, blob_bytes); + printk(BIOS_DEBUG, "%s: Load %s in %ld msecs, size %ld bytes\n", + __func__, name, stopwatch_duration_msecs(&sw), blob_bytes); + + return CB_SUCCESS; +} diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 6890910..bebb0c4 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -52,6 +52,7 @@ ramstage-y += devapc.c ramstage-y += ufs.c ramstage-y += mcupm.c +ramstage-y += ../common/mtlib.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie94001bbda25fe015f43172e92a1006e059de223 Gerrit-Change-Number: 46930 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

4 41

Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Sugnan Prabhu S (Code Review) 10 Dec '20

10 Dec '20

Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 69: (4 comments) https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/67/src/soc/intel/common/base… PS67, Line 260: BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, ucode_fw_sync, NULL); > > This will be moved as part of intel_fw_update where coreboot triggers CSE FW Update and UCODE Upda […] Ack https://review.coreboot.org/c/coreboot/+/27369/69/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/69/src/soc/intel/common/base… PS69, Line 58: halt(); : } > die already calls halt() Done https://review.coreboot.org/c/coreboot/+/27369/69/src/soc/intel/common/base… PS69, Line 131: goto failure; > There is only one occurrence of this so remove the goto? Done https://review.coreboot.org/c/coreboot/+/27369/69/src/soc/intel/common/base… PS69, Line 249: void ucode_fw_sync(void *unused) > any reason to not make this static? This is going to be called from intel_fw_update https://review.coreboot.org/c/coreboot/+/46819/6/src/soc/intel/common/basec… I will remove and make it static for now. I will make is global with the corresponding patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 69 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Thu, 10 Dec 2020 03:14:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Sugnan Prabhu S (Code Review) 10 Dec '20

10 Dec '20

Sugnan Prabhu S has uploaded a new patch set (#70) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... soc/intel/basecode: Add support for updating ucode loaded via FIT Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch) loading mechanism patches the microcode before CPU reset. In the current Chromebooks, field updatable FW has to be first verified by vboot. Since the MCU is loaded before reset, vboot cannot verify the same and hence we end up restricting FIT based MCU update only from RO. This patch implements a scheme which will allow chromebooks to update MCU in the field. Create 2 bootblocks (use INTEL_ADD_TOP_SWAP_BOOTBLOCK) each containing their own FIT table. First bootblock FIT has pointers to MCUs (in microcode_blob.bin) which resides in RO section. This will be used in the recovery scenario and also when booting with top-swap disabled i.e, RTC reset. Second bootblock (Normal mode) is identical to the first one except the FIT. Insert an additional pointer to a MCU that will reside in a staging area. Use the CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG config to insert the address of the staging area into FIT. Top swap control bit in RTC (BUC) PCR register (0x3414) is used to switch between the two bootblocks. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for a particular SoC (e.g., for Skylake/Kaby Lake it is 192K). This is a RW region just like the RW_MRC_CACHE. MCU from RW-A/RW-B will be copied to this region during boot. Protect this staging area with a FPR. Basic update flow: In non-recovery mode, Once a slot has been selected and loaded, check if the current slot MCU and RW staging MCU are same. If not, update the staging area with the MCU found in the current slot and reset the system. Also, make sure that the top-swap is enabled in normal/developer mode and disabled in recovery mode. In order to enable the update feature: * The mainboard chromeos.fmd should include a new region for staging MCU e.g, RW_UCODE_STAGED. * Select config INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE. Add documentation to describing the MCU update procedure. Update config name and Makefile.inc TODO: Since this update mechanism is dealing mostly with a single MCU it is best suited for systems where the CPU is soldered down and not replaceable (socketed). Extend the update mechanism to systems where the CPU is replaceable, by including multiple MCU for different CPUs. TEST=Create an FW image for soraka and flash, create a chromeos-firmwareupdate shellball with a newer MCU and perform an update. Make sure that the currently loaded microcode version matches the one in firmwareupdate. Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M Documentation/soc/intel/index.md A Documentation/soc/intel/ucode_update/flash_layout.svg A Documentation/soc/intel/ucode_update/microcode_update_model.md M Makefile.inc A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/ucode_update.c 7 files changed, 667 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/70 -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 70 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/block/uart: rework to use dummy device
by Michael Niewöhner (Code Review) 10 Dec '20

10 Dec '20

1 0

Change in coreboot[master]: soc/intel/common/block/uart: rework to use dummy device
by Michael Niewöhner (Code Review) 10 Dec '20

10 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48385 ) Change subject: soc/intel/common/block/uart: rework to use dummy device ...................................................................... Patch Set 3: > Patch Set 3: > > I only now realized that you stripped the most important > part when quoting me: > > > > > > What > > > > > about all the mainboards that use this driver by properly > > > > > matching the PCI IDs? > > Maybe you misunderstood. This driver is not only used > via a `chip` entry in the devicetree. It is foremost > used as a usual PCI driver. > > $ git grep 'device pci 1[89e].* on.*UART' src/mainboard/ > > This says there are at least 120 cases in the tree that > potentially use it and might break due to this change. The > driver would even be used if the device is not mentioned > in the dt at all, it's PCI. Ok, that's what *I* missed then... > > > > > > I can't say if this is working, or even if it can work. > > > > > > > > I wonder how this one is different from drivers/wifi/generic, which uses the same dummy model? > > > > > > Except it doesn't? It does not use a generic device below > > > a PCI device. And it checks the device path so it doesn't > > > attach PCI ops to a non-PCI device in the first place. > > > > What is this then? > > > > device pci 14.3 on > > chip drivers/wifi/generic > > register "wake" = "GPE0_PME_B0" > > device generic 0 on end > > end > > end # CNVi wifi > > Sorry, my bad. I didn't realize it's used with two > different topologies. The difference is that the driver > is prepared for that and attaches the CNVi ops only > in case of the generic device. And only then the parent > is queried. > > Here, OTOH, you always use the parent, no matter the > topology. Ack, got it. Thanks > > > > > You really should check the history of drivers/wifi/generic, commit d436750 for example... > > Well, the history is one thing. The current code is what > matters however. How about you read that? I did ;) Actually I meant that one change, the wording is just misleading Well, if we rework the driver/chip modeling like you proposed, we indeed can get rid of any fake devices. Also I'm not sure if we want to mix "drivers" and "chips" then, because it's not always certain which model needs to be used. Or would we keep chips for real devices then and only use "driver" when the port is the device? Where would we place driver options then? > device pci 19.2 hidden > driver soc/intel/common/block/uart > end > > device pci 14.3 on > driver drivers/wifi/generic > register "wake" = "GPE0_PME_B0" > end # CNVi wifi -- To view, visit https://review.coreboot.org/c/coreboot/+/48385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9c9398829b52e6b0523504b862aae9aff559bc7 Gerrit-Change-Number: 48385 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Dec 2020 02:53:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/supermicro/x11ssm-f: enable AER for PCIe root ports
by Michael Niewöhner (Code Review) 10 Dec '20

10 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48369 ) Change subject: mb/supermicro/x11ssm-f: enable AER for PCIe root ports ...................................................................... mb/supermicro/x11ssm-f: enable AER for PCIe root ports Follow vendor and enable Advanced Error Reporting for PCIe root ports. This enabled the Linux AER driver, which handles PCIe error conditions. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I9d9b5afca0ca891e2812445db1d42a46ba16199e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48369 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 549d7d2..7757b69 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -54,16 +54,19 @@ device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4) register "PcieRpEnable[0]" = "1" register "PcieRpLtrEnable[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5) register "PcieRpEnable[4]" = "1" register "PcieRpLtrEnable[4]" = "1" + register "PcieRpAdvancedErrorReporting[4]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device pci 1d.0 on # PCH PCIe Port 9 register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" device pci 00.0 on # GbE 1 subsystemid 0x15d9 0x1533 end @@ -71,6 +74,7 @@ device pci 1d.1 on # PCH PCIe Port 10 register "PcieRpEnable[9]" = "1" register "PcieRpLtrEnable[9]" = "1" + register "PcieRpAdvancedErrorReporting[9]" = "1" device pci 00.0 on # GbE 2 subsystemid 0x15d9 0x1533 end @@ -78,6 +82,7 @@ device pci 1d.2 on # PCH PCIe Port 11 register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" + register "PcieRpAdvancedErrorReporting[10]" = "1" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end -- To view, visit https://review.coreboot.org/c/coreboot/+/48369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d9b5afca0ca891e2812445db1d42a46ba16199e Gerrit-Change-Number: 48369 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/supermicro/x11ssm-f: add subsystem ids to PCI ports and devices
by Michael Niewöhner (Code Review) 10 Dec '20

10 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48368 ) Change subject: mb/supermicro/x11ssm-f: add subsystem ids to PCI ports and devices ...................................................................... mb/supermicro/x11ssm-f: add subsystem ids to PCI ports and devices Add the subsystem ids to PCI ports and devices, which were dumped on vendor firmware using `lspci`. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Idb36c5c72e1b0b8303439ae5dce772822f551d2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48368 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb 1 file changed, 7 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index a03ecc5..549d7d2 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -44,6 +44,7 @@ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" device domain 0 on + subsystemid 0x15d9 0x0896 inherit device pci 01.0 on # CPU PCIe Port (x16) / PCIe Slot 6 (JPCIE6) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X" end @@ -63,12 +64,16 @@ device pci 1d.0 on # PCH PCIe Port 9 register "PcieRpEnable[8]" = "1" register "PcieRpLtrEnable[8]" = "1" - device pci 00.0 on end # GbE 1 + device pci 00.0 on # GbE 1 + subsystemid 0x15d9 0x1533 + end end device pci 1d.1 on # PCH PCIe Port 10 register "PcieRpEnable[9]" = "1" register "PcieRpLtrEnable[9]" = "1" - device pci 00.1 on end # GbE 2 + device pci 00.0 on # GbE 2 + subsystemid 0x15d9 0x1533 + end end device pci 1d.2 on # PCH PCIe Port 11 register "PcieRpEnable[10]" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/48368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb36c5c72e1b0b8303439ae5dce772822f551d2d Gerrit-Change-Number: 48368 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2020