coreboot-gerrit December 2020

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Change in coreboot[master]: soc/amd/picasso: Add data fabric read helper function
by Jason Glenesk (Code Review) 10 Dec '20

10 Dec '20

Jason Glenesk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47726 ) Change subject: soc/amd/picasso: Add data fabric read helper function ...................................................................... Patch Set 3: (8 comments) https://review.coreboot.org/c/coreboot/+/47726/2/src/soc/amd/picasso/data_f… File src/soc/amd/picasso/data_fabric.c: https://review.coreboot.org/c/coreboot/+/47726/2/src/soc/amd/picasso/data_f… PS2, Line 176: return pci_read_config32(_SOC_DEV(DF_DEV, function), reg); > it might be useful to add a comment that the macros will apply a bit mask to the values, so no bit m […] Done https://review.coreboot.org/c/coreboot/+/47726/2/src/soc/amd/picasso/data_f… PS2, Line 180: * requested offset.*/ > Remove leading asterisk and add space in front of */ to match the short multi-line style. […] Done https://review.coreboot.org/c/coreboot/+/47726/2/src/soc/amd/picasso/data_f… PS2, Line 181: reg > reg is the byte address and the two last bits get masked off, since the access is always dword/qword […] Yes, this is always aligned so they omit the last bits https://review.coreboot.org/c/coreboot/+/47726/2/src/soc/amd/picasso/includ… File src/soc/amd/picasso/include/soc/data_fabric.h: https://review.coreboot.org/c/coreboot/+/47726/2/src/soc/amd/picasso/includ… PS2, Line 10: 0xFF > Use lower case for hex numbers here, line 31, 37, etc. Done https://review.coreboot.org/c/coreboot/+/47726/2/src/soc/amd/picasso/includ… PS2, Line 28: #define D18F0_DRAM_HOLE_CTL 0x104 > Unless I'm mistaken, lines 28-56 are unrelated to the "add data fabric helper". […] Done https://review.coreboot.org/c/coreboot/+/47726/2/src/soc/amd/picasso/includ… PS2, Line 28: #define D18F0_DRAM_HOLE_CTL 0x104 : #define DRAM_HOLE_CTL_VALID BIT(0) : #define DRAM_HOLE_CTL_BASE_SHFT 24 : #define DRAM_HOLE_CTL_BASE (0xFF << DRAM_HOLE_CTL_BASE_SHFT) : : #define D18F0_DRAM_BASE0 0x110 : #define DRAM_BASE_REG_VALID BIT(0) : #define DRAM_BASE_HOLE_EN BIT(1) : #define DRAM_BASE_INTLV_CH_SHFT 4 : #define DRAM_BASE_INTLV_CH (0xF << DRAM_BASE_INTLV_CH_SHFT) : #define DRAM_BASE_INTLV_SEL_SHFT 8 : #define DRAM_BASE_INTLV_SEL (0x7 << DRAM_BASE_INTLV_SEL_SHFT) : #define DRAM_BASE_ADDR_SHFT 12 : #define DRAM_BASE_ADDR (0xFFFFF << DRAM_BASE_ADDR_SHFT) : : #define D18F0_DRAM_LIMIT0 0x114 : #define DRAM_LIMIT_DST_ID_SHFT 0 : #define DRAM_LIMIT_DST_ID (0xFF << DRAM_LIMIT_DST_ID_SHFT) : #define DRAM_LIMIT_INTLV_NUM_SOCK_SHFT 8 : #define DRAM_LIMIT_INTLV_NUM_SOCK (0x1 << DRAM_LIMIT_INTLV_NUM_SOCK_SHFT) : #define DRAM_LIMIT_INTLV_NUM_DIE_SHFT 10 : #define DRAM_LIMIT_INTLV_NUM_DIE (0x3 << DRAM_LIMIT_INTLV_NUM_DIE_SHFT) : #define DRAM_LIMIT_ADDR_SHFT 12 : #define DRAM_LIMIT_ADDR (0xFFFFF << DRAM_LIMIT_ADDR_SHFT) : : #define DF_DRAM_BASE(dram_map_pair) ((dram_map_pair) * 2 * sizeof(uint32_t) \ : + D18F0_DRAM_BASE0) : #define DF_DRAM_LIMIT(dram_map_pair) ((dram_map_pair) * 2 * sizeof(uint32_t) \ : + D18F0_DRAM_LIMIT0) > i'd add those in the next commit, since they aren't needed or used for what this patch adds Done https://review.coreboot.org/c/coreboot/+/47726/2/src/soc/amd/picasso/includ… PS2, Line 62: BIT(0) > i'd prefer (1 << 0) over BIT(0), but both will work. your call. Done https://review.coreboot.org/c/coreboot/+/47726/2/src/soc/amd/picasso/includ… PS2, Line 70: DF_IND_CFG_INST_ID > is this a mask? if so, i'dd ad _MASK as suffix Done -- To view, visit https://review.coreboot.org/c/coreboot/+/47726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1 Gerrit-Change-Number: 47726 Gerrit-PatchSet: 3 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Dec 2020 12:58:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Generate ACPI CRAT objects in cb
by build bot (Jenkins) (Code Review) 10 Dec '20

10 Dec '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47727 ) Change subject: soc/amd/picasso: Generate ACPI CRAT objects in cb ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/47727/4/src/soc/amd/picasso/agesa_… File src/soc/amd/picasso/agesa_acpi.c: https://review.coreboot.org/c/coreboot/+/47727/4/src/soc/amd/picasso/agesa_… PS4, Line 506: hsa_entry->flags = CRAT_HSA_PR_FLAG_EN | CRAT_HSA_PR_FLAG_CPU_PRES; 'PRES' may be misspelled - perhaps 'PRESS'? -- To view, visit https://review.coreboot.org/c/coreboot/+/47727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If64fd624597b2ced014ba7f0332a6a48143c0e8c Gerrit-Change-Number: 47727 Gerrit-PatchSet: 4 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 10 Dec 2020 12:54:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Generate ACPI CRAT objects in cb
by Jason Glenesk (Code Review) 10 Dec '20

10 Dec '20

Hello build bot (Jenkins), Bao Zheng, Marshall Dawson, Jason Glenesk, Nikolai Vyssotski, Matt Papageorge, Justin Frodsham, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47727 to look at the new patch set (#4). Change subject: soc/amd/picasso: Generate ACPI CRAT objects in cb ...................................................................... soc/amd/picasso: Generate ACPI CRAT objects in cb Add code to collect all required information and generate ACPI CRAT table entries. Publish tables generated from cb, rather than use the tables created by FSP binary. BUG=b:155307433 TEST=Boot trembyle and compare coreboot generated tables with tables that FSP published previously. BRANCH=Zork Change-Id: If64fd624597b2ced014ba7f0332a6a48143c0e8c Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M src/include/cpu/amd/cpuid.h M src/soc/amd/picasso/agesa_acpi.c M src/soc/amd/picasso/include/soc/data_fabric.h 3 files changed, 674 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/47727/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/47727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If64fd624597b2ced014ba7f0332a6a48143c0e8c Gerrit-Change-Number: 47727 Gerrit-PatchSet: 4 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: Add data fabric read helper function
by Jason Glenesk (Code Review) 10 Dec '20

10 Dec '20

Hello build bot (Jenkins), Bao Zheng, Marshall Dawson, Jason Glenesk, Nikolai Vyssotski, Matt Papageorge, Justin Frodsham, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47726 to look at the new patch set (#3). Change subject: soc/amd/picasso: Add data fabric read helper function ...................................................................... soc/amd/picasso: Add data fabric read helper function Add new helper function to support reading a register from the data fabric. BUG=b:155307433 TEST=Boot trembyle with If64fd624597b2ced014ba7f0332a6a48143c0e8c and confirm read values match expected values. BRANCH=Zork Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1 Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M src/soc/amd/picasso/data_fabric.c M src/soc/amd/picasso/include/soc/data_fabric.h 2 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/47726/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/47726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1 Gerrit-Change-Number: 47726 Gerrit-PatchSet: 3 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/uart: rework to use dummy device
by Michael Niewöhner (Code Review) 10 Dec '20

10 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48385 ) Change subject: soc/intel/common/block/uart: rework to use dummy device ...................................................................... Patch Set 3: > Patch Set 3: > > > > > You really should check the history of drivers/wifi/generic, commit d436750 for example... > > > > > > Well, the history is one thing. The current code is what > > > matters however. How about you read that? > > > > I did ;) Actually I meant that one change, the wording is just misleading > > One major difference in the way UART driver is being handled in this CL and how CNVi device is handled is: > For CNVi: > - PCI operations are still performed as part of the PCI driver for the CNVi controller > - ACPI operations are performed as part of the chip driver written for the dummy device under CNVi controller > > For UART: > - This change performs PCI and ACPI operations on the parent of the dummy device. This does not work for the platforms that do not add the dummy device in devicetree/overridetree. So, that's actually what I had marked here already, right? https://review.coreboot.org/c/coreboot/+/48385/1/src/soc/intel/common/block… > > There are other drivers in coreboot that handle this in a similar way. Example: ISH. PCI operations are handled by PCI driver (either default PCI ops or by the special PCI driver provided in soc/intel) and ACPI operations are handled by chip driver implemented as part of src/drivers. > > One way to handle the UART situation in a similar way would be to provide only the PCI operations in PCI driver provided by soc/intel/common/block/uart and implement a chip driver in drivers/intel_lpss_uart or something similar that generates the required ACPI tables. > > > > > > > Well, if we rework the driver/chip modeling like you proposed, we indeed can get rid of any fake devices. Also I'm not sure if we want to mix "drivers" and "chips" then, because it's not always certain which model needs to be used. Or would we keep chips for real devices then and only use "driver" when the port is the device? > > > > Where would we place driver options then? > > I would be curious to understand how the new model would work too. -- To view, visit https://review.coreboot.org/c/coreboot/+/48385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9c9398829b52e6b0523504b862aae9aff559bc7 Gerrit-Change-Number: 48385 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Dec 2020 12:47:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/ehlcrb: Add EHL CRB memory initialization support
by Lean Sheng Tan (Code Review) 10 Dec '20

10 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48127 ) Change subject: mb/intel/ehlcrb: Add EHL CRB memory initialization support ...................................................................... mb/intel/ehlcrb: Add EHL CRB memory initialization support Update memory parameters based on memory type supported by Elkhart Lake CRB: 1. Update spd data for EHL LPDDR4X memory - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Add configurations for vref_ca & interleaved memory 3. Add EHL CRB on board LPDDR4X SPD data bin file 4. Update mainboard related FSPM UPDs as part of memory initialization Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b --- M src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c M src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc A src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c M src/soc/intel/elkhartlake/include/soc/meminit.h M src/soc/intel/elkhartlake/meminit.c 6 files changed, 115 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/48127/1 diff --git a/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c index 481ff09..3240834 100644 --- a/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c +++ b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c @@ -7,5 +7,15 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { - /* ToDo : Fill FSP-M spd related memory params */ + static struct spd_info ehlcrb_spd_info; + const struct mb_cfg *board_cfg = variant_memcfg_config(); + + /* TODO: Read the resistor strap to get number of memory segments */ + bool half_populated = false; + /* Initialize spd information for LPDDR4x board */ + ehlcrb_spd_info.read_type = READ_SPD_CBFS; + ehlcrb_spd_info.spd_spec.spd_index = 0x00; + + /* Initialize variant specific configurations */ + memcfg_init(&memupd->FspmConfig, board_cfg, &ehlcrb_spd_info, half_populated); } diff --git a/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc index 1af6515..70494b5 100644 --- a/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc +++ b/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc @@ -1,3 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-only -SPD_SOURCES = empty # 0b000 +SPD_SOURCES = ehlcrb # 0b000 diff --git a/src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex b/src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex new file mode 100644 index 0000000..71e5456 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c index 11db732..0f1dd69 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c @@ -5,4 +5,56 @@ #include <soc/meminit.h> #include <soc/romstage.h> -/* ToDo : Fill EHL related memory configs */ +static const struct mb_cfg ehlcrb_lpddr4x_memcfg_cfg = { + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6}, + .dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6}, + + /* Baseboard uses 100, 100 and 100 rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* Baseboard Rcomp target values */ + .rcomp_targets = {60, 40, 30, 20, 30}, + + /* LPDDR4x does not allow interleaved memory */ + .dq_pins_interleaved = 0, + + /* Baseboard is using config 2 for vref_ca */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, + + /* Set Board Type */ + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memcfg_config(void) +{ + return &ehlcrb_lpddr4x_memcfg_cfg; +} diff --git a/src/soc/intel/elkhartlake/include/soc/meminit.h b/src/soc/intel/elkhartlake/include/soc/meminit.h index ea4664a..2dcbd13 100644 --- a/src/soc/intel/elkhartlake/include/soc/meminit.h +++ b/src/soc/intel/elkhartlake/include/soc/meminit.h @@ -88,11 +88,26 @@ /* * Rcomp target values. These will typically be the following - * values for Elkhart Lake : { 80, 40, 40, 40, 30 } + * values for Elkhart Lake : { 60, 40, 30, 20, 30 } */ uint16_t rcomp_targets[5]; /* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + uint8_t dq_pins_interleaved; + + /* + * VREF_CA configuration. + * Set to 0 VREF_CA goes to both CH_A and CH_B, + * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, + * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + */ + uint8_t vref_ca_config; + + /* * Early Command Training Enable/Disable Control * 1 = enable, 0 = disable */ diff --git a/src/soc/intel/elkhartlake/meminit.c b/src/soc/intel/elkhartlake/meminit.c index cd777ba..f1f8270 100644 --- a/src/soc/intel/elkhartlake/meminit.c +++ b/src/soc/intel/elkhartlake/meminit.c @@ -109,6 +109,7 @@ /* Early Command Training Enabled */ mem_cfg->ECT = board_cfg->ect; - + mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; + mem_cfg->CaVrefConfig = board_cfg->vref_ca_config; mem_cfg->UserBd = board_cfg->UserBd; } -- To view, visit https://review.coreboot.org/c/coreboot/+/48127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b Gerrit-Change-Number: 48127 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/ehlcrb: Update ehl_crb device tree
by Lean Sheng Tan (Code Review) 10 Dec '20

10 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48124 ) Change subject: mb/intel/ehlcrb: Update ehl_crb device tree ...................................................................... mb/intel/ehlcrb: Update ehl_crb device tree Update Elkhartlake CRB devicetree devices based on EHL EDS. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I88097ced03f4376f309487b9d5207473f77742ef --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb 1 file changed, 99 insertions(+), 185 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/48124/1 diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index de4dcbe..51f9979 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -7,192 +7,106 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on - chip drivers/intel/dptf - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)" - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 119, SHUTDOWN)" + device pci 04.0 off end # SA Thermal device + device pci 08.0 off end # GNA + device pci 09.0 off end # CPU Intel Trace Hub - register "controls.power_limits.pl1" = "{ - .min_power = 3000, - .max_power = 6000, - .time_window_min = 1 * MSECS_PER_SEC, - .time_window_max = 1 * MSECS_PER_SEC, - .granularity = 200,}" - register "controls.power_limits.pl2" = "{ - .min_power = 20000, - .max_power = 20000, - .time_window_min = 1 * MSECS_PER_SEC, - .time_window_max = 1 * MSECS_PER_SEC, - .granularity = 1000,}" - device generic 0 on end - end - end # SA Thermal device + device pci 10.0 on end # I2C6 + device pci 10.1 on end # I2C7 + device pci 10.5 on end # Integrated Error Handler - device pci 05.0 on end - device pci 12.0 off end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Lower"" - register "type" = "UPC_TYPE_A" - device usb 2.0 on end - end - chip drivers/usb/acpi - register "desc" = ""WWAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.1 on end - end - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 1"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 2"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 3"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.5 on end - end - chip drivers/usb/acpi - register "desc" = ""USB C Connector 4"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - device usb 2.6 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Upper"" - register "type" = "UPC_TYPE_A" - device usb 2.7 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Lower"" - register "type" = "UPC_TYPE_A" - device usb 3.0 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3/2 Type-A Left Upper"" - register "type" = "UPC_TYPE_A" - device usb 3.1 on end - end - chip drivers/usb/acpi - register "desc" = ""WLAN"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.2 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused1"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.3 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused2"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.4 on end - end - chip drivers/usb/acpi - register "desc" = ""USB3 Port Unused3"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 3.5 on end - end - end - end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 off end # PMC SRAM - device pci 14.3 on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device generic 0 on end - end - end # CNVi wifi - device pci 14.5 on end # SDCard - device pci 15.0 on - chip drivers/i2c/max98373 - register "vmon_slot_no" = "4" - register "imon_slot_no" = "5" - register "uid" = "0" - register "desc" = ""RIGHT SPEAKER AMP"" - register "name" = ""MAXR"" - device i2c 31 on end - end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "6" - register "imon_slot_no" = "7" - register "uid" = "1" - register "desc" = ""LEFT SPEAKER AMP"" - register "name" = ""MAXL"" - device i2c 32 on end - end - chip drivers/i2c/da7219 - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H16_IRQ)" - register "btn_cfg" = "50" - register "mic_det_thr" = "500" - register "jack_ins_deb" = "20" - register "jack_det_rate" = ""32ms_64ms"" - register "jack_rem_deb" = "1" - register "a_d_btn_thr" = "0xa" - register "d_b_btn_thr" = "0x16" - register "b_c_btn_thr" = "0x21" - register "c_mic_btn_thr" = "0x3e" - register "btn_avg" = "4" - register "adc_1bit_rpt" = "1" - register "micbias_lvl" = "2600" - register "mic_amp_in_sel" = ""diff"" - device i2c 1a on end - end - end # I2C #0 Audio - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 on end # I2C - device pci 19.1 on end # I2C - device pci 19.2 on end # UART #2 - device pci 1a.0 on end # eMMC - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 on end # PCI Express Port 2 - WLAN - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - NVMe - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 on - chip drivers/spi/acpi - register "hid" = "ACPI_DT_NAMESPACE_HID" - register "compat_string" = ""google,cr50"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_H13_IRQ)" - device spi 0 on end - end - end # GSPI #1 - device pci 1f.0 on end # eSPI Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device pci 11.0 off end # Intel Programmable Services Engine UART0 + device pci 11.1 off end # Intel Programmable Services Engine UART1 + device pci 11.2 off end # Intel Programmable Services Engine UART2 + device pci 11.3 off end # Intel Programmable Services Engine UART3 + device pci 11.4 off end # Intel Programmable Services Engine UART4 + device pci 11.5 off end # Intel Programmable Services Engine UART5 + device pci 11.6 off end # Intel Programmable Services Engine IS20 + device pci 11.7 off end # Intel Programmable Services Engine IS21 + + device pci 12.0 on end # GSPI2 + device pci 12.3 on end # Management Engine UMA Access + device pci 12.4 on end # Management Engine PTT DMA Controller + device pci 12.5 off end # UFS0 + device pci 12.7 off end # UFS1 + + device pci 13.0 off end # Intel Programmable Services Engine GSPI0 + device pci 13.1 off end # Intel Programmable Services Engine GSPI1 + device pci 13.2 off end # Intel Programmable Services Engine GSPI2 + device pci 13.3 off end # Intel Programmable Services Engine GSPI3 + device pci 13.4 off end # Intel Programmable Services Engine GPIO0 + device pci 13.5 off end # Intel Programmable Services Engine GPIO1 + + device pci 14.0 on end # USB3.1 xHCI + device pci 14.1 off end # USB3.1 xDCI (OTG) + + device pci 15.0 on end # I2C0 + device pci 15.1 on end # I2C1 + device pci 15.2 on end # I2C2 + device pci 15.3 on end # I2C3 + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 on end # Management Engine Interface 2 + device pci 16.4 on end # Management Engine Interface 3 + device pci 16.5 on end # Management Engine Interface 4 + + device pci 17.0 on end # SATA + + device pci 18.0 off end # Intel Programmable Services Engine I2C7 + device pci 18.1 off end # Intel Programmable Services Engine CAN0 + device pci 18.2 off end # Intel Programmable Services Engine CAN1 + device pci 18.3 off end # Intel Programmable Services Engine QEP0 + device pci 18.4 off end # Intel Programmable Services Engine QEP1 + device pci 18.5 off end # Intel Programmable Services Engine QEP2 + device pci 18.6 off end # Intel Programmable Services Engine QEP3 + + device pci 19.0 on end # I2C4 + device pci 19.1 on end # I2C5 + device pci 19.2 on end # UART2 + + device pci 1a.0 on end # eMMC + device pci 1a.1 off end # SD + device pci 1a.3 off end # Intel Safety Island + + device pci 1b.0 off end # Intel Programmable Services Engine I2C0 + device pci 1b.1 off end # Intel Programmable Services Engine I2C1 + device pci 1b.2 off end # Intel Programmable Services Engine I2C2 + device pci 1b.3 off end # Intel Programmable Services Engine I2C3 + device pci 1b.4 off end # Intel Programmable Services Engine I2C4 + device pci 1b.5 off end # Intel Programmable Services Engine I2C5 + device pci 1b.6 off end # Intel Programmable Services Engine I2C6 + + device pci 1c.0 on end # RP1 (pcie0 single VC) + device pci 1c.1 on end # RP2 (pcie0 single VC) + device pci 1c.2 on end # RP3 (pcie0 single VC) + device pci 1c.3 on end # RP4 (pcie0 single VC) + device pci 1c.4 on end # RP5 (pcie1 multi VC) + device pci 1c.5 on end # RP6 (pcie2 multi VC) + device pci 1c.6 on end # RP7 (pcie3 multi VC) + + device pci 1d.0 off end # Intel Programmable Services Engine IPC (local host to PSE) + device pci 1d.1 on end # Intel Programmable Services Engine Time-Sensitive Networking GbE 0 + device pci 1d.2 on end # Intel Programmable Services Engine Time-Sensitive Networking GbE 1 + device pci 1d.3 off end # Intel Programmable Services Engine DMA0 + device pci 1d.4 off end # Intel Programmable Services Engine DMA1 + device pci 1d.5 off end # Intel Programmable Services Engine DMA2 + device pci 1d.6 off end # Intel Programmable Services Engine PWM + device pci 1d.7 off end # Intel Programmable Services Engine ADC + + device pci 1e.0 on end # UART0 + device pci 1e.1 on end # UART1 + device pci 1e.2 on end # GSPI0 + device pci 1e.3 on end # GSPI1 + device pci 1e.4 on end # PCH Time-Sensitive Networking GbE + device pci 1e.6 on end # HPET + device pci 1e.7 on end # IOAPIC + + device pci 1f.0 on end # eSPI Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 off end # Intel cAVS/HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI (flash & TPM) + device pci 1f.7 off end # PCH Intel Trace Hub end end -- To view, visit https://review.coreboot.org/c/coreboot/+/48124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88097ced03f4376f309487b9d5207473f77742ef Gerrit-Change-Number: 48124 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/ehlcrb: Remove JSL sku id info in SMBIOS
by Lean Sheng Tan (Code Review) 10 Dec '20

10 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48123 ) Change subject: mb/intel/ehlcrb: Remove JSL sku id info in SMBIOS ...................................................................... mb/intel/ehlcrb: Remove JSL sku id info in SMBIOS Remove JSL specific SMBIOS sku id info as it is not required by EHL. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: Ib672eb456ba62f2eb7f941630c4fbb34823664f5 --- M src/mainboard/intel/elkhartlake_crb/mainboard.c 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/48123/1 diff --git a/src/mainboard/intel/elkhartlake_crb/mainboard.c b/src/mainboard/intel/elkhartlake_crb/mainboard.c index f529573..c63beb7 100644 --- a/src/mainboard/intel/elkhartlake_crb/mainboard.c +++ b/src/mainboard/intel/elkhartlake_crb/mainboard.c @@ -3,7 +3,6 @@ #include <baseboard/variants.h> #include <device/device.h> #include <soc/gpio.h> -#include <smbios.h> static void mainboard_init(void *chip_info) { @@ -14,12 +13,6 @@ gpio_configure_pads(pads, num); } -const char *smbios_system_sku(void) -{ - static const char *sku_str = "sku2147483647"; /* sku{0-1} */ - return sku_str; -} - struct chip_operations mainboard_ops = { .init = mainboard_init, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/48123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib672eb456ba62f2eb7f941630c4fbb34823664f5 Gerrit-Change-Number: 48123 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/intel/ehlcrb: Remove IPU & MIPI related support from EHL CRB
by Lean Sheng Tan (Code Review) 10 Dec '20

10 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48122 ) Change subject: mb/intel/ehlcrb: Remove IPU & MIPI related support from EHL CRB ...................................................................... mb/intel/ehlcrb: Remove IPU & MIPI related support from EHL CRB THis patch removes IPU & MIPI related support from EHL CRB as they are not supported in EHL. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I3eb038009daaabd048f40c7953cb2c111cd4fe63 --- M src/mainboard/intel/elkhartlake_crb/Kconfig M src/mainboard/intel/elkhartlake_crb/mainboard.c M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb 3 files changed, 3 insertions(+), 117 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/48122/1 diff --git a/src/mainboard/intel/elkhartlake_crb/Kconfig b/src/mainboard/intel/elkhartlake_crb/Kconfig index 07dc311..7cf727c 100644 --- a/src/mainboard/intel/elkhartlake_crb/Kconfig +++ b/src/mainboard/intel/elkhartlake_crb/Kconfig @@ -9,14 +9,12 @@ select DRIVERS_INTEL_DPTF select DRIVERS_I2C_GENERIC select DRIVERS_I2C_MAX98373 - select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_ACPI select HAVE_SPD_IN_CBFS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_ELKHARTLAKE select SOC_INTEL_COMMON_BLOCK_DTT diff --git a/src/mainboard/intel/elkhartlake_crb/mainboard.c b/src/mainboard/intel/elkhartlake_crb/mainboard.c index a8a1cc2..54a6f6f 100644 --- a/src/mainboard/intel/elkhartlake_crb/mainboard.c +++ b/src/mainboard/intel/elkhartlake_crb/mainboard.c @@ -2,13 +2,10 @@ #include <baseboard/variants.h> #include <device/device.h> -#include <intelblocks/pcr.h> #include <soc/gpio.h> #include <soc/pcr_ids.h> #include <smbios.h> -#define SERIAL_IO_PCR_GPPRVRW4 0x60C - static void mainboard_init(void *chip_info) { const struct pad_config *pads; @@ -16,9 +13,6 @@ pads = variant_gpio_table(&num); gpio_configure_pads(pads, num); - - if (CONFIG(DRIVERS_INTEL_MIPI_CAMERA)) - pcr_write32(PID_SERIALIO, SERIAL_IO_PCR_GPPRVRW4, BIT8); } const char *smbios_system_sku(void) diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index af0c753..de4dcbe 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -28,21 +28,7 @@ end end # SA Thermal device - device pci 05.0 on - chip drivers/intel/mipi_camera - register "acpi_uid" = "0x50000" - register "acpi_name" = ""IPU0"" - register "device_type" = "INTEL_ACPI_CAMERA_CIO2" - - register "cio2_num_ports" = "2" - register "cio2_lanes_used" = "{2,2}" - register "cio2_lane_endpoint[0]" = ""^I2C4.CAM0"" - register "cio2_lane_endpoint[1]" = ""^I2C5.CAM1"" - register "cio2_prt[0]" = "0" - register "cio2_prt[1]" = "2" - device generic 0 on end - end - end + device pci 05.0 on end device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 @@ -178,100 +164,8 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 off end # SATA - device pci 19.0 on # I2C #4 Cam 0 - chip drivers/intel/mipi_camera - register "acpi_hid" = ""OVTI2740"" - register "acpi_uid" = "0" - register "acpi_name" = ""CAM0"" - register "chip_name" = ""Ov 2740 Camera"" - register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" - register "has_power_resource" = "1" - - register "ssdb.lanes_used" = "2" - register "num_freq_entries" = "1" - register "link_freq[0]" = "360000000" - register "remote_name" = ""IPU0"" - - #Controls - register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_3 - register "clk_panel.clks[0].freq" = "1" #19.2 Mhz - - register "gpio_panel.gpio[0].gpio_num" = "GPP_D5" #reset - register "gpio_panel.gpio[1].gpio_num" = "GPP_B14" #power - - #_ON - register "on_seq.ops_cnt" = "4" - register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" - register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" - register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" - register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" - - #_OFF - register "off_seq.ops_cnt" = "3" - register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" - register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)" - - device i2c 10 on end - end - end - device pci 19.1 on # I2C #5 Cam 1 and VCM - chip drivers/intel/mipi_camera - register "acpi_hid" = ""OVTI5675"" - register "acpi_uid" = "0" - register "acpi_name" = ""CAM1"" - register "chip_name" = ""Ov 5675 Camera"" - register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" - - register "ssdb.lanes_used" = "2" - register "ssdb.link_used" = "1" - register "ssdb.vcm_type" = "0x0C" - register "vcm_name" = ""VCM0"" - register "num_freq_entries" = "1" - register "link_freq[0]" = "DEFAULT_LINK_FREQ" - register "remote_name" = ""IPU0"" - - register "has_power_resource" = "1" - #Controls - register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_3 - register "clk_panel.clks[0].freq" = "1" #19.2 Mhz - - register "gpio_panel.gpio[0].gpio_num" = "GPP_D4" #power_enable - register "gpio_panel.gpio[1].gpio_num" = "GPP_C19" #reset - - #_ON - register "on_seq.ops_cnt" = "4" - register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" - register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" - register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)" - register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" - - #_OFF - register "off_seq.ops_cnt" = "3" - register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" - register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)" - - device i2c 36 on end - end - chip drivers/intel/mipi_camera - register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" - register "acpi_uid" = "3" - register "acpi_name" = ""VCM0"" - register "chip_name" = ""DW AF DAC"" - register "device_type" = "INTEL_ACPI_CAMERA_VCM" - - register "pr0" = ""\\_SB.PCI0.I2C5.CAM1.PRIC"" - register "vcm_compat" = ""dongwoon,dw9714"" - - register "ssdb.lanes_used" = "2" - register "num_freq_entries" = "1" - register "link_freq[0]" = "DEFAULT_LINK_FREQ" - register "remote_name" = ""IPU0"" - device i2c 0C on end - end - end - + device pci 19.0 on end # I2C + device pci 19.1 on end # I2C device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 off end # PCI Express Port 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/48122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3eb038009daaabd048f40c7953cb2c111cd4fe63 Gerrit-Change-Number: 48122 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/ehlcrb: Remove board ID detection via EC
by Lean Sheng Tan (Code Review) 10 Dec '20

10 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48121 ) Change subject: mb/intel/ehlcrb: Remove board ID detection via EC ...................................................................... mb/intel/ehlcrb: Remove board ID detection via EC Since there is no EC support on EHL CRB, this patch removes board ID detection via EC (board_id.c & board_id.h) and its related files. Temporarily removes variant_memcfg_config function in romstage_fsp_param.c, will be added back when updating memory configs later. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I40d96285dc05ec5faabc123950b6b3728299e99a --- M src/mainboard/intel/elkhartlake_crb/Makefile.inc D src/mainboard/intel/elkhartlake_crb/board_id.c D src/mainboard/intel/elkhartlake_crb/board_id.h M src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c M src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c 6 files changed, 1 insertion(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/48121/1 diff --git a/src/mainboard/intel/elkhartlake_crb/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/Makefile.inc index 69a9368..382ec2e 100644 --- a/src/mainboard/intel/elkhartlake_crb/Makefile.inc +++ b/src/mainboard/intel/elkhartlake_crb/Makefile.inc @@ -5,11 +5,8 @@ bootblock-y += bootblock.c romstage-y += romstage_fsp_params.c -romstage-y += board_id.c ramstage-y += mainboard.c -ramstage-y += board_id.c - subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/intel/elkhartlake_crb/board_id.c b/src/mainboard/intel/elkhartlake_crb/board_id.c deleted file mode 100644 index 90609ff..0000000 --- a/src/mainboard/intel/elkhartlake_crb/board_id.c +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <boardid.h> -#include <ec/acpi/ec.h> -#include <ec/google/chromeec/ec.h> -#include <stdint.h> - -#include "board_id.h" - -static uint32_t get_board_id_via_ext_ec(void) -{ - uint32_t id = BOARD_ID_INIT; - - if (google_chromeec_get_board_version(&id)) - id = BOARD_ID_UNKNOWN; - - return id; -} - -/* - * Get Board ID via EC I/O port write/read - * Board id is 5 bit, so mask other bits while returning board id. - */ -int get_board_id(void) -{ - MAYBE_STATIC_NONZERO int id = -1; - - if (id < 0) { - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - id = get_board_id_via_ext_ec(); - } else { - uint8_t buffer[2]; - uint8_t index; - if (send_ec_command(EC_FAB_ID_CMD) == 0) { - for (index = 0; index < sizeof(buffer); index++) - buffer[index] = recv_ec_data(); - id = (buffer[0] << 8) | buffer[1]; - } - } - } - - return (id & 0x1f); -} diff --git a/src/mainboard/intel/elkhartlake_crb/board_id.h b/src/mainboard/intel/elkhartlake_crb/board_id.h deleted file mode 100644 index 85c7c85..0000000 --- a/src/mainboard/intel/elkhartlake_crb/board_id.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _MAINBOARD_COMMON_BOARD_ID_H_ -#define _MAINBOARD_COMMON_BOARD_ID_H_ - -/* Board/FAB ID Command */ -#define EC_FAB_ID_CMD 0x0D - -/* - * Returns board information (board id[15:8] and - * Fab info[7:0]) on success and < 0 on error - */ -int get_board_id(void); - -#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c index 1354edf..481ff09 100644 --- a/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c +++ b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c @@ -4,7 +4,6 @@ #include <console/console.h> #include <soc/meminit.h> #include <soc/romstage.h> -#include "board_id.h" void mainboard_memory_init_params(FSPM_UPD *memupd) { diff --git a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h index 27e91a5..96ee4d5 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h @@ -13,6 +13,6 @@ const struct pad_config *variant_early_gpio_table(size_t *num); /* This function returns SPD related FSP-M mainboard configs */ -const struct mb_cfg *variant_memcfg_config(uint8_t board_id); +const struct mb_cfg *variant_memcfg_config(void); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c index 8446e6c..11db732 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c @@ -1,16 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> -#include <console/console.h> #include <gpio.h> #include <soc/meminit.h> #include <soc/romstage.h> /* ToDo : Fill EHL related memory configs */ - -const struct mb_cfg *variant_memcfg_config(uint8_t board_id) -{ - /* ToDo : Fill EHL related memory configs */ - - die("unsupported board id : 0x%x\n", board_id); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/48121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d96285dc05ec5faabc123950b6b3728299e99a Gerrit-Change-Number: 48121 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

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