coreboot-gerrit December 2020

coreboot-gerrit@coreboot.org

1 participants
3168 discussions

Change in coreboot[master]: soc/intel/common/block/uart: rework to use dummy device
by Furquan Shaikh (Code Review) 10 Dec '20

10 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48385 ) Change subject: soc/intel/common/block/uart: rework to use dummy device ...................................................................... Patch Set 3: > Patch Set 3: > > > Patch Set 3: > > > > > > > You really should check the history of drivers/wifi/generic, commit d436750 for example... > > > > > > > > Well, the history is one thing. The current code is what > > > > matters however. How about you read that? > > > > > > I did ;) Actually I meant that one change, the wording is just misleading > > > > One major difference in the way UART driver is being handled in this CL and how CNVi device is handled is: > > For CNVi: > > - PCI operations are still performed as part of the PCI driver for the CNVi controller > > - ACPI operations are performed as part of the chip driver written for the dummy device under CNVi controller > > > > For UART: > > - This change performs PCI and ACPI operations on the parent of the dummy device. This does not work for the platforms that do not add the dummy device in devicetree/overridetree. > > So, that's actually what I had marked here already, right? https://review.coreboot.org/c/coreboot/+/48385/1/src/soc/intel/common/block… You are going to need to allow PCI ops on the PCI device directly. And the separate chip driver for the dummy device will perform ACPI ops only. That will allow other mainboards to not use the dummy device at all. The way it is written currently in the link you pasted above - it assumes that the PCI device is always a parent of the dummy device which is not true for any other mainboards and hence it breaks the behavior. -- To view, visit https://review.coreboot.org/c/coreboot/+/48385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9c9398829b52e6b0523504b862aae9aff559bc7 Gerrit-Change-Number: 48385 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Dec 2020 18:43:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ==== 2nd gen
by Marshall Dawson (Code Review) 10 Dec '20

10 Dec '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48545 ) Change subject: ==== 2nd gen ...................................................................... ==== 2nd gen Change-Id: I60e363da6ee6e22dbdf314c856cc5e3f1b0e776a --- M util/amdfwtool/amdfwtool.c 1 file changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/48545/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 36d669b..401cf20 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -323,6 +323,13 @@ { .type = AMD_BIOS_INVALID }, }; +struct second_gen_efs { /* todo: expand for Server products */ + int gen:1; /* Client products only use bit 0 */ + int reserved:31; +} __attribute__((packed)); + +#define EFS_SECOND_GEN 0 + typedef struct _embedded_firmware { uint32_t signature; /* 0x55aa55aa */ uint32_t imc_entry; @@ -333,7 +340,7 @@ uint32_t bios0_entry; /* todo: add way to select correct entry */ uint32_t bios1_entry; uint32_t bios2_entry; - uint32_t second_gen_efs; /* Client SKUs b0=1 is Gen1, b1=0 is Gen2, Servers TBD */ + struct second_gen_efs efs_gen; uint32_t bios3_entry; uint32_t reserved_2Ch; uint32_t promontory_fw_ptr; @@ -1187,6 +1194,8 @@ break; case PLATFORM_RAVEN: case PLATFORM_PICASSO: + /* amd_romsig->efs_gen introduced after RAVEN/PICASSO. + * Leave as 0xffffffff for first gen */ amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; switch (efs_spi_micron_flag) { @@ -1203,7 +1212,7 @@ break; case PLATFORM_RENOIR: case PLATFORM_LUCIENNE: - amd_romsig->second_gen_efs = 0xfffffffe; + amd_romsig->efs_gen.gen = EFS_SECOND_GEN; amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; switch (efs_spi_micron_flag) { -- To view, visit https://review.coreboot.org/c/coreboot/+/48545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60e363da6ee6e22dbdf314c856cc5e3f1b0e776a Gerrit-Change-Number: 48545 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM
by Duncan Laurie (Code Review) 10 Dec '20

10 Dec '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47682 ) Change subject: drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM ...................................................................... drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM Configure the CFG2 register to set the latency to <64us in order to ensure the L1 exit latency is consistent across devices and that L1 ASPM is always enabled. BUG=b:173207454 TEST=Verify the device and link capability and control for L1: DevCap: Latency L1 <64us LnkCap: Latency L1 <64us LnkCtl: ASPM L1 Enabled Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: Ie2b85a6697f164fbe4f84d8cd5acb2b5911ca7a9 --- M src/drivers/genesyslogic/gl9755/gl9755.c M src/drivers/genesyslogic/gl9755/gl9755.h 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47682/1 diff --git a/src/drivers/genesyslogic/gl9755/gl9755.c b/src/drivers/genesyslogic/gl9755/gl9755.c index c3cdef1..ed76457 100644 --- a/src/drivers/genesyslogic/gl9755/gl9755.c +++ b/src/drivers/genesyslogic/gl9755/gl9755.c @@ -12,13 +12,23 @@ static void gl9755_init(struct device *dev) { + uint32_t reg; + printk(BIOS_INFO, "GL9755: init\n"); pci_dev_init(dev); /* Set Vendor Config to be configurable */ pci_or_config32(dev, CFG, CFG_EN); + /* Set LTR value */ pci_write_config32(dev, LTR, NO_SNOOP_SCALE|NO_SNOOP_VALUE|SNOOP_SCALE|SNOOP_VALUE); + + /* Adjust L1 exit latency to enable ASPM */ + reg = pci_read_config32(dev, CFG2); + reg &= ~CFG2_LAT_L1_MASK; + reg |= CFG2_LAT_L1_ASPM; + pci_write_config32(dev, CFG2, reg); + /* Set Vendor Config to be non-configurable */ pci_and_config32(dev, CFG, ~CFG_EN); } diff --git a/src/drivers/genesyslogic/gl9755/gl9755.h b/src/drivers/genesyslogic/gl9755/gl9755.h index 2d20faf..0492fab 100644 --- a/src/drivers/genesyslogic/gl9755/gl9755.h +++ b/src/drivers/genesyslogic/gl9755/gl9755.h @@ -1,11 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef DRIVERS_GENESYSLOGIC_GL9755_H +#define DRIVERS_GENESYSLOGIC_GL9755_H + /* Definitions for Genesys Logic GL9755 */ #define CFG 0x800 #define CFG_EN 0x1 +#define CFG2 0x48 +#define CFG2_LAT_L1_MASK ((0x7 << 12) | (0x7 << 3)) +#define CFG2_LAT_L1_ASPM ((0x6 << 12) | (0x6 << 3)) #define LTR 0x5C #define SNOOP_VALUE 0x25 #define SNOOP_SCALE (0x3 << 10) #define NO_SNOOP_VALUE (0x25 << 16) #define NO_SNOOP_SCALE (0x3 << 26) + +#endif /* DRIVERS_GENESYSLOGIC_GL9755_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b85a6697f164fbe4f84d8cd5acb2b5911ca7a9 Gerrit-Change-Number: 47682 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: drivers/intel/fsp1_1/cache_as_ram.S: Correct comment
by Frans Hendriks (Code Review) 10 Dec '20

10 Dec '20

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47802 ) Change subject: drivers/intel/fsp1_1/cache_as_ram.S: Correct comment ...................................................................... drivers/intel/fsp1_1/cache_as_ram.S: Correct comment Stack is setup for bootblock Tested on Facebook FBG1701 Change-Id: I0dd3fc91c90bf76e0d93925da35dc197d68d3e88 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/cache_as_ram.S 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47802/1 diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 3be9eb9..ce1ee9c 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -132,7 +132,7 @@ cmp $0, %eax jne halt2 - /* Setup bootloader stack */ + /* Setup bootblock stack */ movl $_ecar_stack, %esp /* -- To view, visit https://review.coreboot.org/c/coreboot/+/47802 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dd3fc91c90bf76e0d93925da35dc197d68d3e88 Gerrit-Change-Number: 47802 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/google/zork: Remove unsused code
by Mathew King (Code Review) 10 Dec '20

10 Dec '20

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48505 ) Change subject: mb/google/zork: Remove unsused code ...................................................................... mb/google/zork: Remove unsused code Remove unused code that appears to be left over from grunt. Signed-off-by: Mathew King <mathewk(a)chromium.org> Change-Id: Id5bdb1c957342d55c5e6378c503b8d90da050601 --- M src/mainboard/google/zork/mainboard.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h 4 files changed, 0 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/48505/1 diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 5ab90cf..413f34a 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -162,17 +162,6 @@ /* Update DUT configuration */ mainboard_devtree_update(); - - /* - * Some platforms use SCI not generated by a GPIO pin (event above 23). - * For these boards, gpe_configure_sci() is still needed, but all GPIO - * generated events (23-0) must be removed from gpe_table[]. - * For boards that only have GPIO generated events, table gpe_table[] - * must be removed, and get_gpe_table() should return NULL. - */ - gpes = variant_gpe_table(&num); - if (gpes != NULL) - gpe_configure_sci(gpes, num); } void mainboard_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index bf27abf..12d2890 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -169,18 +169,6 @@ return gpio_set_stage_ram; } -/* - * This function is still needed for boards that sets gevents above 23 - * that will generate SCI or SMI. Normally this function - * points to a table of gevents and what needs to be set. The code that - * calls it was modified so that when this function returns NULL then the - * caller does nothing. - */ -const __weak struct sci_source *variant_gpe_table(size_t *num) -{ - return NULL; -} - static void wifi_power_reset_configure_active_low_power(void) { /* diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 0745eda..a2ad517 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -181,18 +181,6 @@ return gpio_set_stage_ram; } -/* - * This function is still needed for boards that sets gevents above 23 - * that will generate SCI or SMI. Normally this function - * points to a table of gevents and what needs to be set. The code that - * calls it was modified so that when this function returns NULL then the - * caller does nothing. - */ -const __weak struct sci_source *variant_gpe_table(size_t *num) -{ - return NULL; -} - static void wifi_power_reset_configure_active_low_power(void) { /* diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h index 4ec6add..f6e7e7c 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h @@ -9,7 +9,6 @@ #include <soc/platform_descriptors.h> #include "chip.h" -const struct sci_source *variant_gpe_table(size_t *num); const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); /* * This function provides base GPIO configuration table. It is typically provided by -- To view, visit https://review.coreboot.org/c/coreboot/+/48505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5bdb1c957342d55c5e6378c503b8d90da050601 Gerrit-Change-Number: 48505 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/google/volteer: Fix a few devicetree device refs
by Tim Wawrzynczak (Code Review) 10 Dec '20

10 Dec '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48511 ) Change subject: mb/google/volteer: Fix a few devicetree device refs ...................................................................... mb/google/volteer: Fix a few devicetree device refs Commit b0e169ac85 included a few small omissions and typos when converting 'device pci xx.y' to 'device ref blah' after adding the new chipset.cb file for TGL. This patch fixes these errors: 1) MIPI camera support requires I2C2 & I2C3 enabled 2) Malefor SAR sensor is on I2C2, not I2C3 BUG=b:175165653 TEST=abuild -p none -t google/volteer -x -a -c max Change-Id: I577957d67f47bbe88bbc2535fb1cb5c8f7390438 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/malefor/overridetree.cb 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/48511/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 353aa27..30625ca 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -464,6 +464,9 @@ device generic 0 on end end end + # MIPI camera devices are on I2C buses 2 and 3 + device ref i2c2 on end + device ref i2c3 on end device ref heci1 on end device ref sata on end device ref pcie_rp1 on end diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index ec9bd67..95dc3f7 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -63,7 +63,7 @@ device i2c 5d on end end end - device ref i2c3 on + device ref i2c2 on chip drivers/i2c/sx9310 register "desc" = ""SAR0 Proximity Sensor"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" -- To view, visit https://review.coreboot.org/c/coreboot/+/48511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I577957d67f47bbe88bbc2535fb1cb5c8f7390438 Gerrit-Change-Number: 48511 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/tigerlake: Check TBT & TCSS ports for wake events
by Tim Wawrzynczak (Code Review) 10 Dec '20

10 Dec '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47396 ) Change subject: soc/intel/tigerlake: Check TBT & TCSS ports for wake events ...................................................................... soc/intel/tigerlake: Check TBT & TCSS ports for wake events Wakes from TBT ports and TCSS devices will show up as PME_B0_STS wakes, so add checks for wakes from these devices in pch_log_pme_internal_wake_source. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ie9904c3c01ea85fcd83218fcfeaa4378b07c1463 --- M src/soc/intel/tigerlake/elog.c 1 file changed, 25 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/47396/1 diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 88324d6..b8b2cc5 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -76,13 +76,17 @@ bool dev_found = false; const struct pme_map ipme_map[] = { - { PCH_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA }, - { PCH_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE }, - { PCH_DEVFN_SATA, ELOG_WAKE_SOURCE_PME_SATA }, - { PCH_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE }, - { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, - { PCH_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI }, - { PCH_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI }, + { PCH_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA }, + { PCH_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE }, + { PCH_DEVFN_SATA, ELOG_WAKE_SOURCE_PME_SATA }, + { PCH_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE }, + { PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCH_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI }, + { PCH_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI }, + { SA_DEVFN_TCSS_XHCI, ELOG_WAKE_SOURCE_PME_TCSS_XHCI }, + { SA_DEVFN_TCSS_XDCI, ELOG_WAKE_SOURCE_PME_TCSS_XDCI }, + { SA_DEVFN_TCSS_DMA0, ELOG_WAKE_SOURCE_PME_TCSS_DMA0 }, + { SA_DEVFN_TCSS_DMA1, ELOG_WAKE_SOURCE_PME_TCSS_DMA1 }, }; for (i = 0; i < ARRAY_SIZE(ipme_map); i++) { @@ -106,6 +110,20 @@ if (!dev_found) dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info()); + /* Check Thunderbolt ports */ + if (!dev_found) { + for (i = 0; i < NUM_TBT_FUNCTIONS; i++) { + const struct device *dev = pcidev_path_on_root(SA_DEVFN_TBT(i)); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TBT, i); + dev_found = true; + } + } + } + if (!dev_found) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9904c3c01ea85fcd83218fcfeaa4378b07c1463 Gerrit-Change-Number: 47396 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 16

Change in coreboot[master]: soc/intel/common: Add North XHCI block driver
by Tim Wawrzynczak (Code Review) 10 Dec '20

10 Dec '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47411 ) Change subject: soc/intel/common: Add North XHCI block driver ...................................................................... soc/intel/common: Add North XHCI block driver Add a driver for the North XHCI block, which is part of the Type-C Subsystem. This driver only adds support for logging wake events from USB2 and USB3 ports associated with the North XHCI. Change-Id: I9f28354e031e3eda587f4faf8ef7595dce8b33ea Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- A src/soc/intel/common/block/include/intelblocks/north_xhci.h A src/soc/intel/common/block/north_xhci/Kconfig A src/soc/intel/common/block/north_xhci/Makefile.inc A src/soc/intel/common/block/north_xhci/elog.c 4 files changed, 138 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/47411/1 diff --git a/src/soc/intel/common/block/include/intelblocks/north_xhci.h b/src/soc/intel/common/block/include/intelblocks/north_xhci.h new file mode 100644 index 0000000..a561847 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/north_xhci.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_NORTH_XHCI_H +#define SOC_INTEL_COMMON_BLOCK_NORTH_XHCI_H + +#include <stdint.h> +#include <types.h> + +struct north_xhci_usb_info { + uint32_t usb2_port_status_reg; + uint32_t num_usb2_ports; + uint32_t usb3_port_status_reg; + uint32_t num_usb3_ports; +}; + +/* + * soc_get_north_xhci_usb_info() - Get the information about North USB2 & USB3 ports. + * + * This function is used to get USB ports and status register offset information within a North + * XHCI controller. + * + * Return: North USB ports and status register offset info for the SoC. + */ +const struct north_xhci_usb_info *soc_get_north_xhci_usb_info(void); + +/* + * pch_xhci_update_wake_event() - Identify and log North XHCI wake events. + * @info: Information about number of North USB ports and their status reg offset. + * + * This function goes through individual USB port status registers within the North XHCI block + * and identifies if any of those USB ports triggered a wake-up and logs information about those + * ports to the event log. + * + * Returns true if a North XHCI USB port was the source of a wake. + */ +bool north_xhci_update_wake_event(const struct north_xhci_usb_info *info); + +#endif /* SOC_INTEL_COMMON_BLOCK_NORTH_XHCI_H */ diff --git a/src/soc/intel/common/block/north_xhci/Kconfig b/src/soc/intel/common/block/north_xhci/Kconfig new file mode 100644 index 0000000..0517d25 --- /dev/null +++ b/src/soc/intel/common/block/north_xhci/Kconfig @@ -0,0 +1,6 @@ +config SOC_INTEL_COMMON_BLOCK_NORTH_XHCI_ELOG + bool + default n + help + Set this option to identify if the North XHCI caused a wake and log + that information to the event log. diff --git a/src/soc/intel/common/block/north_xhci/Makefile.inc b/src/soc/intel/common/block/north_xhci/Makefile.inc new file mode 100644 index 0000000..9ac3048 --- /dev/null +++ b/src/soc/intel/common/block/north_xhci/Makefile.inc @@ -0,0 +1,2 @@ +#ramstage-$(SOC_INTEL_COMMON_BLOCK_NORTH_XHCI_ELOG) += elog.c +ramstage-y += elog.c diff --git a/src/soc/intel/common/block/north_xhci/elog.c b/src/soc/intel/common/block/north_xhci/elog.c new file mode 100644 index 0000000..5006318 --- /dev/null +++ b/src/soc/intel/common/block/north_xhci/elog.c @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <device/pci_ops.h> +#include <elog.h> +#include <intelblocks/north_xhci.h> +#include <soc/pci_devs.h> +#include <stdint.h> +#include <types.h> + +/* Port Link State */ +#define PORTSC_PLS_MASK 0xf0 +#define PORTSC_PLS_RESUME 0xf0 +/* Connect Status Change */ +#define PORTSC_CSC BIT(17) +/* Port Link State Change */ +#define PORTSC_PLC BIT(22) +/* Wake On Connect Enable */ +#define PORTSC_WCE BIT(25) +/* Wake On Disconnect Enable */ +#define PORTSC_WDE BIT(26) + +/* MMIO space between PORTSC registers */ +#define NEXT_PORT_OFFSET 0x10 + +static bool is_connect_wake_capable(uint32_t portsc) +{ + return !!(portsc & (PORTSC_WDE | PORTSC_WCE)); +} + +static bool connect_status_changed(uint32_t portsc) +{ + return !!(portsc & PORTSC_CSC); +} + +static bool is_link_state_changed(uint32_t portsc) +{ + return !!(portsc & PORTSC_PLC); +} + +static bool link_status_is_resume(uint32_t portsc) +{ + return (portsc & PORTSC_PLS_MASK) == PORTSC_PLS_RESUME; +} + +static bool log_port_wakes(uintptr_t base, uint8_t num, uint8_t event) +{ + uint32_t portsc; + unsigned int i; + bool found = false; + + /* For each port, if it is: + * 1) Capable of wakes on connect/disconnect and connect status changed, or: + * 2) Link state changed and its new state is a resume (indicating USB activity), + * then add a wake event to the elog. + */ + for (i = 0; i < num; i++, base += NEXT_PORT_OFFSET) { + portsc = read32((void *)base); + if (portsc == 0xffffffff) + continue; + + if ((is_connect_wake_capable(portsc) && connect_status_changed(portsc)) || + (is_link_state_changed(portsc) && link_status_is_resume(portsc))) { + elog_add_event_wake(event, i + 1); + found = true; + } + } + + return found; +} + +bool north_xhci_update_wake_event(const struct north_xhci_usb_info *info) +{ + const struct device *tcss_xhci = pcidev_path_on_root(SA_DEV_TCSS_XHCI); + bool found = false; + + if (!tcss_xhci) + return false; + + const uintptr_t mmio_base = pci_read_config32(tcss_xhci, PCI_BASE_ADDRESS_0) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + + found |= log_port_wakes(mmio_base + info->usb2_port_status_reg, + info->num_usb2_ports, + ELOG_WAKE_SOURCE_PME_TCSS_XHCI_USB_2); + + found |= log_port_wakes(mmio_base + info->usb3_port_status_reg, + info->num_usb3_ports, + ELOG_WAKE_SOURCE_PME_TCSS_XHCI_USB_3); + + return found; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f28354e031e3eda587f4faf8ef7595dce8b33ea Gerrit-Change-Number: 47411 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 26

Change in coreboot[master]: soc/intel/xeon_sp/nvs: Use common global NVS
by Marc Jones (Code Review) 10 Dec '20

10 Dec '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48491 ) Change subject: soc/intel/xeon_sp/nvs: Use common global NVS ...................................................................... soc/intel/xeon_sp/nvs: Use common global NVS The xeon_sp ACPI NVS and ramstage NVS were out of sync. Since there isn't anything uncommon with the soc NVS, use the Intel common NVS. This covers the NVS cases of common code used by xeon_sp. Update the mainboards for this change. Change-Id: Icf422f5b75a1ca7a3d8f3d63638b8d86a56fdd7b Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/mainboard/ocp/deltalake/dsdt.asl M src/mainboard/ocp/tiogapass/dsdt.asl D src/soc/intel/xeon_sp/acpi/globalnvs.asl M src/soc/intel/xeon_sp/include/soc/nvs.h 4 files changed, 4 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/48491/1 diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl index 1541134..63aeb70 100644 --- a/src/mainboard/ocp/deltalake/dsdt.asl +++ b/src/mainboard/ocp/deltalake/dsdt.asl @@ -14,7 +14,7 @@ #include "acpi/platform.asl" // global NVS and variables - #include <soc/intel/xeon_sp/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> #include <cpu/intel/common/acpi/cpu.asl> diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index 7905a9c..7fa518b 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -12,7 +12,7 @@ ) { #include "acpi/platform.asl" - #include <soc/intel/xeon_sp/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> #include <cpu/intel/common/acpi/cpu.asl> #include <soc/intel/xeon_sp/acpi/uncore.asl> Scope (\_SB.PC00) diff --git a/src/soc/intel/xeon_sp/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/acpi/globalnvs.asl deleted file mode 100644 index 00848cc..0000000 --- a/src/soc/intel/xeon_sp/acpi/globalnvs.asl +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Global Variables */ - -Name(\PICM, 0) // IOAPIC/8259 - -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PRM0, 8, // 0x03 - SMI function parameter - PRM1, 8, // 0x04 - SMI function parameter - SCIF, 8, // 0x05 - SCI function - PRM2, 8, // 0x06 - SCI function parameter - PRM3, 8, // 0x07 - SCI function parameter - LCKF, 8, // 0x08 - Global Lock function for EC - PRM4, 8, // 0x09 - Lock function parameter - PRM5, 8, // 0x0a - Lock function parameter - P80D, 32, // 0x0b - Debug port (IO 0x80) value - LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) - PCNT, 8, // 0x11 - Processor count - TPMP, 8, // 0x12 - TPM Present and Enabled - TLVL, 8, // 0x13 - Throttle Level - PPCM, 8, // 0x14 - Maximum P-state usable by OS - PM1I, 64, // 0x15 - PM1 wake status bit - GPEI, 64, // 0x1D - GPE wake status bit - U2WE, 16, // 0x25 - USB2 Wake Enable Bitmap - U3WE, 8, // 0x27 - USB3 Wake Enable Bitmap - - /* Device Config */ - Offset (0x30), - S5U0, 8, // 0x30 - Enable USB0 in S5 - S5U1, 8, // 0x31 - Enable USB1 in S5 - S3U0, 8, // 0x32 - Enable USB0 in S3 - S3U1, 8, // 0x33 - Enable USB1 in S3 - TACT, 8, // 0x34 - Thermal Active trip point - TPSV, 8, // 0x35 - Thermal Passive trip point - TCRT, 8, // 0x36 - Thermal Critical trip point - DPTE, 8, // 0x37 - Enable DPTF - - /* Base addresses */ - Offset (0x50), - CMEM, 32, // 0x50 - CBMEM TOC - TOLM, 32, // 0x54 - Top of Low Memory - CBMC, 32, // 0x58 - coreboot mem console pointer - MMOB, 32, // 0x5C - MMIO Base Low Base - MMOL, 32, // 0x60 - MMIO Base Low Limit - MMHB, 64, // 0x64 - MMIO Base High Base - MMHL, 64, // 0x6C - MMIO Base High Limit - TSGB, 32, // 0x74 - TSEG Base - TSSZ, 32, // 0x78 - TSEG Size -} diff --git a/src/soc/intel/xeon_sp/include/soc/nvs.h b/src/soc/intel/xeon_sp/include/soc/nvs.h index 100a442..5129458 100644 --- a/src/soc/intel/xeon_sp/include/soc/nvs.h +++ b/src/soc/intel/xeon_sp/include/soc/nvs.h @@ -3,18 +3,6 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ -#include <stdint.h> +#include <intelblocks/nvs.h> -/* TODO - this requires xeon sp, server board support */ -/* NOTE: We do not use intelblocks/nvs.h since it includes - mostly client specific attributes */ - -/* TODO: This is not aligned with the ACPI asl code */ -struct __packed global_nvs { - uint8_t pcnt; /* 0x00 - Processor Count */ - uint32_t cbmc; /* 0x01 - coreboot memconsole */ - uint8_t uior; - uint8_t rsvd3[250]; -}; - -#endif /* _SOC_NVS_H_ */ +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf422f5b75a1ca7a3d8f3d63638b8d86a56fdd7b Gerrit-Change-Number: 48491 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: sb/intel/bd82x6x: Make me_common.c a compilation unit
by Angel Pons (Code Review) 10 Dec '20

10 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42019 ) Change subject: sb/intel/bd82x6x: Make me_common.c a compilation unit ...................................................................... sb/intel/bd82x6x: Make me_common.c a compilation unit We need to make most things non-static so that the code builds. Change-Id: I17e561abf2378632f72d0aa9f0057cb1bee23514 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/Makefile.inc M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_common.c 5 files changed, 47 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/42019/1 diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 9e34e96..cf9bf50 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -15,6 +15,7 @@ ramstage-y += usb_xhci.c ramstage-y += me.c ramstage-y += me_8.x.c +ramstage-y += me_common.c ramstage-y += smbus.c ramstage-y += ../common/pciehp.c @@ -24,7 +25,7 @@ ramstage-$(CONFIG_ELOG) += elog.c -smm-y += smihandler.c me.c me_8.x.c pch.c +smm-y += smihandler.c me.c me_8.x.c pch.c me_common.c romstage-y += early_smbus.c me_status.c romstage-y += early_rcba.c diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 515f984..d2a3480 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -28,9 +28,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -/* FIXME: For verification purposes only */ -#include "me_common.c" - /* Get ME firmware version */ static int __unused mkhi_get_fw_version(void) { diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 5aaf661..a55a1f2 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -221,6 +221,34 @@ ME_FIRMWARE_UPDATE_BIOS_PATH, } me_bios_path; +/* Defined in me_common.c for both ramstage and smm */ +const char *const me_get_bios_path_string(int path); + +void mei_read_dword_ptr(void *ptr, int offset); +void mei_write_dword_ptr(void *ptr, int offset); + +#ifndef __SIMPLE_DEVICE__ +void pci_read_dword_ptr(struct device *dev, void *ptr, int offset); +#endif + +void read_host_csr(struct mei_csr *csr); +void write_host_csr(struct mei_csr *csr); + +void read_me_csr(struct mei_csr *csr); + +void write_cb(u32 dword); +u32 read_cb(void); + +int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data, void *rsp_data, int rsp_bytes); + +int mkhi_end_of_post(void); +void update_mei_base_address(void); +bool is_mei_base_address_valid(void); +int intel_mei_setup(struct device *dev); +int intel_me_extend_valid(struct device *dev); +void intel_me_hide(struct device *dev); + /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index fcf4dd3..1a331e9 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -28,9 +28,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -/* FIXME: For verification purposes only */ -#include "me_common.c" - static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 790b870..83e7fe6 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -25,7 +25,7 @@ [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static inline const char *const me_get_bios_path_string(int path) +const char *const me_get_bios_path_string(int path) { return me_bios_path_values[path]; } @@ -70,14 +70,14 @@ * ME/MEI access helpers using memcpy to avoid aliasing. */ -static inline void mei_read_dword_ptr(void *ptr, int offset) +void mei_read_dword_ptr(void *ptr, int offset) { u32 dword = read32(mei_base_address + (offset / sizeof(u32))); memcpy(ptr, &dword, sizeof(dword)); mei_dump(ptr, dword, offset, "READ"); } -static inline void mei_write_dword_ptr(void *ptr, int offset) +void mei_write_dword_ptr(void *ptr, int offset) { u32 dword = 0; memcpy(&dword, ptr, sizeof(dword)); @@ -86,7 +86,7 @@ } #ifndef __SIMPLE_DEVICE__ -static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) +void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -94,28 +94,28 @@ } #endif -static inline void read_host_csr(struct mei_csr *csr) +void read_host_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_H_CSR); } -static inline void write_host_csr(struct mei_csr *csr) +void write_host_csr(struct mei_csr *csr) { mei_write_dword_ptr(csr, MEI_H_CSR); } -static inline void read_me_csr(struct mei_csr *csr) +void read_me_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_ME_CSR_HA); } -static inline void write_cb(u32 dword) +void write_cb(u32 dword) { write32(mei_base_address + (MEI_H_CB_WW / sizeof(u32)), dword); mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); } -static inline u32 read_cb(void) +u32 read_cb(void) { u32 dword = read32(mei_base_address + (MEI_ME_CB_RW / sizeof(u32))); mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); @@ -310,8 +310,8 @@ return mei_wait_for_me_ready(); } -static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) +int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data, void *rsp_data, int rsp_bytes) { if (mei_send_msg(mei, mkhi, req_data) < 0) return -1; @@ -321,7 +321,7 @@ } /* Send END OF POST message to the ME */ -static int __unused mkhi_end_of_post(void) +int mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -351,12 +351,12 @@ #ifdef __SIMPLE_DEVICE__ -static inline void update_mei_base_address(void) +void update_mei_base_address(void) { mei_base_address = (u32 *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); } -static inline bool is_mei_base_address_valid(void) +bool is_mei_base_address_valid(void) { return mei_base_address && mei_base_address != (u32 *)0xfffffff0; } @@ -364,7 +364,7 @@ #else /* Prepare ME for MEI messages */ -static int intel_mei_setup(struct device *dev) +int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -391,7 +391,7 @@ } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(struct device *dev) +int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -438,7 +438,7 @@ } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(struct device *dev) +void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/42019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17e561abf2378632f72d0aa9f0057cb1bee23514 Gerrit-Change-Number: 42019 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 13

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2020