Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48468 )
Change subject: Makefile.inc: Remove the CBNT bootblock flag
......................................................................
Makefile.inc: Remove the CBNT bootblock flag
At the moment this was only used for aligning the bootblock to 64
bytes. At the moment this automatically done with
CONFIG_C_ENV_BOOTBLOCK_SIZE.
Change-Id: I0c879119e525b512eebe3f4c5ff9b2f426c6b6ff
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.inc
1 file changed, 0 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/48468/1
diff --git a/Makefile.inc b/Makefile.inc
index 420ce51..d95cb88 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -730,16 +730,6 @@
endif
-ifeq ($(CONFIG_INTEL_CBNT_SUPPORT),y)
-
-CBNTIBB := --cbnt
-
-else
-
-CBNTIBB :=
-
-endif # CONFIG_INTEL_CBNT_SUPPORT
-
ifeq ($(CONFIG_COMPRESS_BOOTBLOCK),y)
$(objcbfs)/bootblock.lz4: $(objcbfs)/bootblock.elf $(objutil)/cbfstool/cbfs-compression-tool
@@ -1081,7 +1071,6 @@
-n bootblock \
-t bootblock \
$(TXTIBB) \
- $(CBNTIBB) \
-b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \
$(TS_OPTIONS)
else # ifeq ($(CONFIG_ARCH_X86),y)
--
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Frank Chu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47358 )
Change subject: mb/google/volteer: Create drobit variant
......................................................................
Abandoned
--
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Ken Lu has uploaded a new patch set (#2) to the change originally created by Frank Chu. ( https://review.coreboot.org/c/coreboot/+/48495 )
Change subject: mb/google/volteer: Update drobit device tree
......................................................................
mb/google/volteer: Update drobit device tree
Update drobit device tree override to match schematics.
BUG=b:175351914
BRANCH=none
TEST=emerge-volteer coreboot
Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com>
Change-Id: I48a3024df4270b111b90c4fb56847aad6e65bfa1
---
M src/mainboard/google/volteer/variants/drobit/overridetree.cb
1 file changed, 233 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/48495/2
--
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Ken Lu has uploaded a new patch set (#2) to the change originally created by Frank Chu. ( https://review.coreboot.org/c/coreboot/+/48496 )
Change subject: mb/google/volteer: Update SPD table for drobit
......................................................................
mb/google/volteer: Update SPD table for drobit
drobit memory table as follow:
value Vendor Part number
0x00 MICRON MT53E512M32D2NP-046 WT:E
0x00 HYNIX H9HCNNNBKMMLXR-NEE
0x01 MICRON MT53E1G32D2NP-046 WT:A
0x02 HYNIX H9HCNNNCPMMLXR-NEE
BUG=b:175351914
BRANCH=none
TEST=emerge-volteer coreboot
Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com>
Change-Id: Icd9439f8449856d4ec6798a4e4310dd139bce05f
---
A src/mainboard/google/volteer/variants/drobit/Makefile.inc
A src/mainboard/google/volteer/variants/drobit/memory.c
M src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc
M src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt
A src/mainboard/google/volteer/variants/drobit/memory/mem_list_variant.txt
D src/mainboard/google/volteer/variants/drobit/memory/mem_parts_used.txt
6 files changed, 80 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/48496/2
--
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Gerrit-Change-Id: Icd9439f8449856d4ec6798a4e4310dd139bce05f
Gerrit-Change-Number: 48496
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Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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Ken Lu has uploaded a new patch set (#2) to the change originally created by Frank Chu. ( https://review.coreboot.org/c/coreboot/+/48497 )
Change subject: mb/google/volteer: Add GPIO to drobit support
......................................................................
mb/google/volteer: Add GPIO to drobit support
Add support for gpio driver for drobit
BUG=b:175351914
BRANCH=none
TEST=emerge-volteer coreboot
Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com>
Change-Id: I54ba182c6da3db282961b3c72a4d2d11d1001e95
---
M src/mainboard/google/volteer/variants/drobit/Makefile.inc
A src/mainboard/google/volteer/variants/drobit/gpio.c
2 files changed, 188 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/48497/2
--
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Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com>
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48516 )
Change subject: soc/amd/picasso: factor out write_resume_eip to common code
......................................................................
soc/amd/picasso: factor out write_resume_eip to common code
Change-Id: I24454aa9e2ccc98b2aceb6b189e072e6e50b8b30
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/soc/amd/common/block/cpu/noncar/Makefile.inc
A src/soc/amd/common/block/cpu/noncar/write_resume_eip.c
A src/soc/amd/common/block/include/amdblocks/cpu.h
M src/soc/amd/picasso/bootblock.c
4 files changed, 36 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/48516/1
diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
index 7a3be34..ed08d2a 100644
--- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc
+++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc
@@ -1,5 +1,6 @@
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y)
bootblock-y += pre_c.S
+bootblock-y += write_resume_eip.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR
diff --git a/src/soc/amd/common/block/cpu/noncar/write_resume_eip.c b/src/soc/amd/common/block/cpu/noncar/write_resume_eip.c
new file mode 100644
index 0000000..e9b59d9
--- /dev/null
+++ b/src/soc/amd/common/block/cpu/noncar/write_resume_eip.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <arch/cpu.h>
+#include <amdblocks/cpu.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/msr.h>
+
+asmlinkage void bootblock_resume_entry(void);
+
+void write_resume_eip(void)
+{
+ msr_t s3_resume_entry = {
+ .hi = (uint64_t)(uintptr_t)bootblock_resume_entry >> 32,
+ .lo = (uintptr_t)bootblock_resume_entry & 0xffffffff,
+ };
+
+ /*
+ * Writing to the EIP register can only be done once, otherwise a fault is triggered.
+ * When this register is written, it will trigger the microcode to stash the CPU state
+ * (crX , mtrrs, registers, etc) into the CC6 save area. On resume, the state will be
+ * restored and execution will continue at the EIP.
+ */
+ if (!acpi_is_wakeup_s3())
+ wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry);
+}
diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h
new file mode 100644
index 0000000..0a93643
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/cpu.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_BLOCK_CPU_H
+#define AMD_BLOCK_CPU_H
+
+void write_resume_eip(void);
+
+#endif /* AMD_BLOCK_CPU_H */
diff --git a/src/soc/amd/picasso/bootblock.c b/src/soc/amd/picasso/bootblock.c
index 0b52a17..7d1f01c 100644
--- a/src/soc/amd/picasso/bootblock.c
+++ b/src/soc/amd/picasso/bootblock.c
@@ -2,12 +2,12 @@
#include <stdint.h>
#include <symbols.h>
+#include <amdblocks/cpu.h>
#include <amdblocks/reset.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
-#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/tsc.h>
@@ -16,9 +16,6 @@
#include <soc/southbridge.h>
#include <soc/i2c.h>
#include <amdblocks/amd_pci_mmconf.h>
-#include <acpi/acpi.h>
-
-asmlinkage void bootblock_resume_entry(void);
/* PSP performs the memory training and setting up DRAM map prior to x86 cores
being released. Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise,
@@ -91,23 +88,6 @@
enable_cache();
}
-static void write_resume_eip(void)
-{
- msr_t s3_resume_entry = {
- .hi = (uint64_t)(uintptr_t)bootblock_resume_entry >> 32,
- .lo = (uintptr_t)bootblock_resume_entry & 0xffffffff,
- };
-
- /*
- * Writing to the EIP register can only be done once, otherwise a fault is triggered.
- * When this register is written, it will trigger the microcode to stash the CPU state
- * (crX , mtrrs, registers, etc) into the CC6 save area. On resume, the state will be
- * restored and execution will continue at the EIP.
- */
- if (!acpi_is_wakeup_s3())
- wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry);
-}
-
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
set_caching();
--
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