coreboot-gerrit December 2020

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Change in coreboot[master]: soc/amd/picasso: Add data fabric read helper function
by Marshall Dawson (Code Review) 11 Dec '20

11 Dec '20

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47726 ) Change subject: soc/amd/picasso: Add data fabric read helper function ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/47726/2/src/soc/amd/picasso/includ… File src/soc/amd/picasso/include/soc/data_fabric.h: https://review.coreboot.org/c/coreboot/+/47726/2/src/soc/amd/picasso/includ… PS2, Line 62: BIT(0) > Done Hmm, we seem to oscillate back and forth. There was a big push before to use BIT(). -- To view, visit https://review.coreboot.org/c/coreboot/+/47726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1 Gerrit-Change-Number: 47726 Gerrit-PatchSet: 4 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Dec 2020 16:12:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/block/acpi: Skip UART debug table if not used
by Marc Jones (Code Review) 11 Dec '20

11 Dec '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48247 ) Change subject: soc/intel/common/block/acpi: Skip UART debug table if not used ...................................................................... soc/intel/common/block/acpi: Skip UART debug table if not used Skip the ACPI UART debug table if common block UART isn't selected. Change-Id: I8d627998ca450c32496c90e51aad48f332b40e23 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/common/block/acpi/acpi.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/48247/1 diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 6c389fa..84a85d2 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -154,9 +154,12 @@ unsigned long current, struct acpi_rsdp *rsdp) { - current = acpi_write_dbg2_pci_uart(rsdp, current, - uart_get_device(), - ACPI_ACCESS_SIZE_DWORD_ACCESS); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_UART)) { + current = acpi_write_dbg2_pci_uart(rsdp, current, + uart_get_device(), + ACPI_ACCESS_SIZE_DWORD_ACCESS); + } + return acpi_write_hpet(device, current, rsdp); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d627998ca450c32496c90e51aad48f332b40e23 Gerrit-Change-Number: 48247 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: Kconfig: Show console debug options if loglevel override is set
by Marc Jones (Code Review) 11 Dec '20

11 Dec '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48249 ) Change subject: Kconfig: Show console debug options if loglevel override is set ...................................................................... Kconfig: Show console debug options if loglevel override is set Show console debug options that would only be available if console SPEW was selected when the override loglevel option is selected. Change-Id: I2fb22562688d6b0bc9235c9ebe5d427dc2a67767 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/Kconfig 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/48249/1 diff --git a/src/Kconfig b/src/Kconfig index dc98ca2..b9df3a0 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -905,7 +905,7 @@ # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional # printk(BIOS_DEBUG, ...) calls. config DEBUG_MALLOC - prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 + prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL bool default n help @@ -917,7 +917,7 @@ # Only visible if DEBUG_SPEW (8) is set. config DEBUG_RESOURCES - bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8 + bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL default n help This option enables additional PCI memory and IO debug messages. @@ -939,7 +939,7 @@ # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional # printk(BIOS_DEBUG, ...) calls. config REALMODE_DEBUG - prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 + prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL bool default n depends on PCI_OPTION_ROM_RUN_REALMODE -- To view, visit https://review.coreboot.org/c/coreboot/+/48249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fb22562688d6b0bc9235c9ebe5d427dc2a67767 Gerrit-Change-Number: 48249 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/intel/common/block/lpc: Include correct acpi.h
by Marc Jones (Code Review) 11 Dec '20

11 Dec '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48251 ) Change subject: soc/intel/common/block/lpc: Include correct acpi.h ...................................................................... soc/intel/common/block/lpc: Include correct acpi.h If ACPI is configured, use the correct acpi.h include path. Change-Id: I0590a028b11f34e423d8f0007e0653037b0849a0 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/common/block/lpc/lpc.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/48251/1 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index d11aa10..37b4e04 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -4,10 +4,17 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <intelblocks/acpi.h> #include <intelblocks/lpc_lib.h> #include <soc/pm.h> +#if CONFIG(HAVE_ACPI_TABLES) +#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI) +#include <intelblocks/acpi.h> +#else +#include <soc/acpi.h> +#endif /* HAVE_ACPI_TABLES */ +#endif /* SOC_INTEL_COMMON_ACPI */ + /* SoC overrides */ /* Common weak definition, needs to be implemented in each soc LPC driver. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0590a028b11f34e423d8f0007e0653037b0849a0 Gerrit-Change-Number: 48251 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: sb/intel/x/smbus.c: Factor out common code
by Angel Pons (Code Review) 11 Dec '20

11 Dec '20

Hello Felix Singer, Nico Huber, Arthur Heymans, Michael Niewöhner, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48364 to review the following change. Change subject: sb/intel/x/smbus.c: Factor out common code ...................................................................... sb/intel/x/smbus.c: Factor out common code Since common smbus.c gets built for romstage as well, create a new file to hold this common code. Account for ICH7 not having a memory BAR, too. Change-Id: I4ab46750c6fb7f71cbd55848e79ecc3e44cbbd04 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/smbus.c M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/smbus_ops.c A src/southbridge/intel/common/smbus_ops.h M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/i82801ix/smbus.c M src/southbridge/intel/i82801jx/smbus.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/lynxpoint/smbus.c 9 files changed, 99 insertions(+), 411 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/48364/1 diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 0da3b76..9ba9e12 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -8,6 +8,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/smbus_host.h> +#include <southbridge/intel/common/smbus_ops.h> #include "pch.h" static void pch_smbus_init(struct device *dev) @@ -27,75 +28,6 @@ smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR); } -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_write_byte(res->base, device, address, data); -} - -static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buf) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_block_write(res->base, device, cmd, bytes, buf); -} - -static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_block_read(res->base, device, cmd, bytes, buf); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, - .block_read = lsmbus_block_read, - .block_write = lsmbus_block_write, -}; - -static void smbus_read_resources(struct device *dev) -{ - struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = CONFIG_FIXED_SMBUS_IO_BASE; - res->size = 32; - res->limit = res->base + res->size - 1; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Also add MMIO resource */ - res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); -} - static const char *smbus_acpi_name(const struct device *dev) { return "SBUS"; diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 1ededd2..6c57481 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -9,6 +9,7 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus_ops.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c diff --git a/src/southbridge/intel/common/smbus_ops.c b/src/southbridge/intel/common/smbus_ops.c new file mode 100644 index 0000000..b0ecc1a --- /dev/null +++ b/src/southbridge/intel/common/smbus_ops.c @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <device/path.h> +#include <device/smbus.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/smbus_host.h> +#include <southbridge/intel/common/smbus_ops.h> + +static int lsmbus_read_byte(struct device *dev, u8 address) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); + + return do_smbus_read_byte(res->base, device, address); +} + +static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); + return do_smbus_write_byte(res->base, device, address, data); +} + +static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buf) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); + return do_smbus_block_write(res->base, device, cmd, bytes, buf); +} + +static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf) +{ + u16 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); + return do_smbus_block_read(res->base, device, cmd, bytes, buf); +} + +struct smbus_bus_operations lops_smbus_bus = { + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, + .block_read = lsmbus_block_read, + .block_write = lsmbus_block_write, +}; + +void smbus_read_resources(struct device *dev) +{ + struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); + res->base = CONFIG_FIXED_SMBUS_IO_BASE; + res->size = 32; + res->limit = res->base + res->size - 1; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* The memory BAR does not exist for ICH7 and earlier */ + if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) + return; + + /* Also add MMIO resource */ + res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); +} diff --git a/src/southbridge/intel/common/smbus_ops.h b/src/southbridge/intel/common/smbus_ops.h new file mode 100644 index 0000000..fbdbb99 --- /dev/null +++ b/src/southbridge/intel/common/smbus_ops.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <device/smbus.h> +#include <device/smbus_host.h> + +extern struct smbus_bus_operations lops_smbus_bus; + +void smbus_read_resources(struct device *dev); diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index 5915f3d..739e552 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -7,74 +7,9 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/smbus_host.h> +#include <southbridge/intel/common/smbus_ops.h> #include "i82801gx.h" -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_write_byte(res->base, device, address, data); -} - -static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buf) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_block_write(res->base, device, cmd, bytes, buf); -} - -static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_block_read(res->base, device, cmd, bytes, buf); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, - .block_read = lsmbus_block_read, - .block_write = lsmbus_block_write, -}; - -static void smbus_read_resources(struct device *dev) -{ - struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = CONFIG_FIXED_SMBUS_IO_BASE; - res->size = 32; - res->limit = res->base + res->size - 1; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c index 8daaf2e..1ccd9f5 100644 --- a/src/southbridge/intel/i82801ix/smbus.c +++ b/src/southbridge/intel/i82801ix/smbus.c @@ -8,6 +8,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/smbus_host.h> +#include <southbridge/intel/common/smbus_ops.h> #include "i82801ix.h" static void pch_smbus_init(struct device *dev) @@ -16,75 +17,6 @@ pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14))); } -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_write_byte(res->base, device, address, data); -} - -static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buf) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_block_write(res->base, device, cmd, bytes, buf); -} - -static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_block_read(res->base, device, cmd, bytes, buf); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, - .block_read = lsmbus_block_read, - .block_write = lsmbus_block_write, -}; - -static void smbus_read_resources(struct device *dev) -{ - struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = CONFIG_FIXED_SMBUS_IO_BASE; - res->size = 32; - res->limit = res->base + res->size - 1; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Also add MMIO resource */ - res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); -} - static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c index 2e2491a..11a3daa 100644 --- a/src/southbridge/intel/i82801jx/smbus.c +++ b/src/southbridge/intel/i82801jx/smbus.c @@ -8,6 +8,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/smbus_host.h> +#include <southbridge/intel/common/smbus_ops.h> #include "i82801jx.h" static void pch_smbus_init(struct device *dev) @@ -16,75 +17,6 @@ pci_and_config16(dev, 0x80, ~((1 << 8) | (1 << 10) | (1 << 12) | (1 << 14))); } -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_write_byte(res->base, device, address, data); -} - -static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buf) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_block_write(res->base, device, cmd, bytes, buf); -} - -static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_block_read(res->base, device, cmd, bytes, buf); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, - .block_read = lsmbus_block_read, - .block_write = lsmbus_block_write, -}; - -static void smbus_read_resources(struct device *dev) -{ - struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = CONFIG_FIXED_SMBUS_IO_BASE; - res->size = 32; - res->limit = res->base + res->size - 1; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Also add MMIO resource */ - res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); -} - static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index 7e976e0..352b589 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -8,6 +8,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/smbus_host.h> +#include <southbridge/intel/common/smbus_ops.h> #include "pch.h" static void pch_smbus_init(struct device *dev) @@ -26,75 +27,6 @@ smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR); } -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_write_byte(res->base, device, address, data); -} - -static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buf) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_block_write(res->base, device, cmd, bytes, buf); -} - -static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_block_read(res->base, device, cmd, bytes, buf); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, - .block_read = lsmbus_block_read, - .block_write = lsmbus_block_write, -}; - -static void smbus_read_resources(struct device *dev) -{ - struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = CONFIG_FIXED_SMBUS_IO_BASE; - res->size = 32; - res->limit = res->base + res->size - 1; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Also add MMIO resource */ - res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); -} - static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index a173b43..e2d42ac 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -7,6 +7,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/smbus_host.h> +#include <southbridge/intel/common/smbus_ops.h> #include "pch.h" static void pch_smbus_init(struct device *dev) @@ -26,75 +27,6 @@ smbus_set_slave_addr(res->base, SMBUS_SLAVE_ADDR); } -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_write_byte(res->base, device, address, data); -} - -static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buf) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_block_write(res->base, device, cmd, bytes, buf); -} - -static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_block_read(res->base, device, cmd, bytes, buf); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, - .block_read = lsmbus_block_read, - .block_write = lsmbus_block_write, -}; - -static void smbus_read_resources(struct device *dev) -{ - struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = CONFIG_FIXED_SMBUS_IO_BASE; - res->size = 32; - res->limit = res->base + res->size - 1; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Also add MMIO resource */ - res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); -} - static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, -- To view, visit https://review.coreboot.org/c/coreboot/+/48364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ab46750c6fb7f71cbd55848e79ecc3e44cbbd04 Gerrit-Change-Number: 48364 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: sb/intel/bd82x6x: Drop invalid SATA registers
by Angel Pons (Code Review) 11 Dec '20

11 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47099 ) Change subject: sb/intel/bd82x6x: Drop invalid SATA registers ...................................................................... sb/intel/bd82x6x: Drop invalid SATA registers Code was copy-pasted from older chips and has no effect on bd82x6x. Change-Id: I909158906c4dc8b6f0a16558c61f095ef425a776 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/bd82x6x/sata.c 2 files changed, 2 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/47099/1 diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index eff0858..151627d 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -159,48 +159,8 @@ #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ -#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) - -#define IDE_SDMA_TIM 0x4a - -#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) - #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ #define SATA_SP 0xd0 /* Scratchpad */ diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 484f0f1..875f3f7 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -117,20 +117,8 @@ printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); /* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); -- To view, visit https://review.coreboot.org/c/coreboot/+/47099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I909158906c4dc8b6f0a16558c61f095ef425a776 Gerrit-Change-Number: 47099 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: soc/intel/xeon_sp: Lock PAM and SMRAM registers
by Arthur Heymans (Code Review) 11 Dec '20

11 Dec '20

Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47168 to look at the new patch set (#13). Change subject: soc/intel/xeon_sp: Lock PAM and SMRAM registers ...................................................................... soc/intel/xeon_sp: Lock PAM and SMRAM registers The CedarIsland FSP Integration recommends locking down some things. Change-Id: I72e04b55d69a8da79485e084b39c3bd38504897f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/chip.c 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/47168/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/47168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72e04b55d69a8da79485e084b39c3bd38504897f Gerrit-Change-Number: 47168 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in em100[master]: em100: usb reset utility
by Stefan Reinauer (Code Review) 11 Dec '20

11 Dec '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/48547 ) Change subject: em100: usb reset utility ...................................................................... em100: usb reset utility If youre EM100 hangs because of an incomplete transfer, you can use this Linux utility to reset the USB port and get the EM100 working again Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I5cc9c6108dff5d980c97a92a1ac4a209ea77a3ca --- A usbreset.c 1 file changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/47/48547/1 diff --git a/usbreset.c b/usbreset.c new file mode 100644 index 0000000..d0a5c07 --- /dev/null +++ b/usbreset.c @@ -0,0 +1,38 @@ +#include <stdio.h> +#include <unistd.h> +#include <fcntl.h> +#include <errno.h> +#include <sys/ioctl.h> + +#include <linux/usbdevice_fs.h> + +int main(int argc, char **argv) +{ + const char *filename; + int fd; + int rc; + + if (argc != 2) { + fprintf(stderr, "Usage: usbreset device-filename\n"); + fprintf(stderr, " device-filename i.e. /dev/bus/usb/001/024\n"); + return 1; + } + filename = argv[1]; + + fd = open(filename, O_WRONLY); + if (fd < 0) { + perror("Error opening output file"); + return 1; + } + + printf("Resetting USB device %s\n", filename); + rc = ioctl(fd, USBDEVFS_RESET, 0); + if (rc < 0) { + perror("Error in ioctl"); + return 1; + } + printf("Reset successful\n"); + + close(fd); + return 0; +} -- To view, visit https://review.coreboot.org/c/em100/+/48547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I5cc9c6108dff5d980c97a92a1ac4a209ea77a3ca Gerrit-Change-Number: 48547 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/ocp/deltalake: Update GPIO configurations according to schematics
by Hung-Te Lin (Code Review) 11 Dec '20

11 Dec '20

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47229 ) Change subject: mb/ocp/deltalake: Update GPIO configurations according to schematics ...................................................................... mb/ocp/deltalake: Update GPIO configurations according to schematics On Delta Lake DVT, dump GPIO settings from UEFI firmware for new PCH (C621A) by util/inteltool and generate the header file by util/intelp2m. The DVT and EVT GPIO configurations are the same. The initial value of GPP_B20 (POST complete) should be high, otherwise BIC would get incorrect sensor readings and see events like PCH prochot. Tested=On OCP Delta Lake DVT, dump GPIO configurations by Intel ITP and verify the results match with the header file. Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47229 Reviewed-by: Tim Chu <Tim.Chu(a)quantatw.com> Reviewed-by: Jonathan Zhang <jonzhang(a)fb.com> Reviewed-by: Johnny Lin <Johnny_Lin(a)wiwynn.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/ocp/deltalake/include/cpxsp_dl_gpio.h 1 file changed, 23 insertions(+), 23 deletions(-) Approvals: build bot (Jenkins): Verified Jonathan Zhang: Looks good to me, approved Johnny Lin: Looks good to me, but someone else must approve Tim Chu: Looks good to me, but someone else must approve diff --git a/src/mainboard/ocp/deltalake/include/cpxsp_dl_gpio.h b/src/mainboard/ocp/deltalake/include/cpxsp_dl_gpio.h index 6a31c74..fad22aa 100644 --- a/src/mainboard/ocp/deltalake/include/cpxsp_dl_gpio.h +++ b/src/mainboard/ocp/deltalake/include/cpxsp_dl_gpio.h @@ -9,7 +9,7 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Community 0 ------- */ /* ------- GPIO Group GPP_A ------- */ - PAD_CFG_NF(GPP_A0, NONE, RSMRST, NF1), /* RCIN# */ + PAD_CFG_NF(GPP_A0, NONE, RSMRST, NF3), /* ESPI_ALERT1# */ PAD_CFG_NF(GPP_A1, NONE, RSMRST, NF1), /* LAD0 */ PAD_CFG_NF(GPP_A2, NONE, RSMRST, NF1), /* LAD1 */ PAD_CFG_NF(GPP_A3, NONE, RSMRST, NF1), /* LAD2 */ @@ -22,9 +22,9 @@ PAD_NC(GPP_A10, NONE), /* GPIO */ PAD_CFG_NF(GPP_A11, NONE, RSMRST, NF1), /* PME# */ PAD_CFG_GPI_SCI(GPP_A12, NONE, RSMRST, OFF, NONE), /* GPIO */ - PAD_NC(GPP_A13, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A13, NONE, RSMRST, NF1), /* SUSWARN#/SUSPWRDNACK */ PAD_NC(GPP_A14, NONE), /* GPIO */ - PAD_NC(GPP_A15, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A15, NONE, RSMRST, NF1), /* SUS_ACK# */ PAD_NC(GPP_A16, NONE), /* GPIO */ PAD_NC(GPP_A17, NONE), /* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A18, NONE, RSMRST, OFF, ACPI), /* GPIO */ @@ -37,7 +37,7 @@ /* ------- GPIO Group GPP_B ------- */ PAD_NC(GPP_B0, NONE), /* GPIO */ PAD_NC(GPP_B1, NONE), /* GPIO */ - PAD_NC(GPP_B2, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, RSMRST, OFF, ACPI), /* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, RSMRST, OFF, ACPI), /* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, RSMRST, OFF, ACPI), /* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, RSMRST, OFF, ACPI), /* GPIO */ @@ -55,7 +55,7 @@ PAD_CFG_GPI_TRIG_OWN(GPP_B17, NONE, RSMRST, OFF, ACPI), /* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, RSMRST, OFF, ACPI), /* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, RSMRST, OFF, ACPI), /* GPIO */ - PAD_CFG_GPO(GPP_B20, 0, RSMRST), /* GPIO */ + PAD_CFG_GPO(GPP_B20, 1, RSMRST), /* GPIO */ PAD_NC(GPP_B21, NONE), /* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, RSMRST, OFF, ACPI), /* GPIO */ PAD_CFG_NF(GPP_B23, NONE, RSMRST, NF2), /* PCHHOT# */ @@ -67,10 +67,10 @@ PAD_NC(GPP_F3, NONE), /* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, RSMRST, OFF, ACPI), /* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, RSMRST, OFF, ACPI), /* GPIO */ - PAD_NC(GPP_F6, NONE), /* GPIO */ - PAD_NC(GPP_F7, NONE), /* GPIO */ - PAD_NC(GPP_F8, NONE), /* GPIO */ - PAD_NC(GPP_F9, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_F6, 0, RSMRST), /* GPIO */ + PAD_CFG_GPO(GPP_F7, 0, RSMRST), /* GPIO */ + PAD_CFG_GPO(GPP_F8, 0, RSMRST), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, RSMRST, OFF, ACPI), /* GPIO */ PAD_NC(GPP_F10, NONE), /* GPIO */ PAD_NC(GPP_F11, NONE), /* GPIO */ PAD_NC(GPP_F12, NONE), /* GPIO */ @@ -107,14 +107,14 @@ PAD_NC(GPP_C16, NONE), /* GPIO */ PAD_NC(GPP_C17, NONE), /* GPIO */ PAD_NC(GPP_C18, NONE), /* GPIO */ - PAD_NC(GPP_C19, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, RSMRST, OFF, ACPI), /* GPIO */ /* GPP_C20 - RESERVED */ PAD_CFG_GPI_TRIG_OWN(GPP_C21, NONE, RSMRST, OFF, ACPI), /* GPIO */ PAD_CFG_GPI_SMI(GPP_C22, NONE, RSMRST, LEVEL, INVERT), /* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C23, NONE, RSMRST, OFF, ACPI), /* GPIO */ /* ------- GPIO Group GPP_D ------- */ - PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_NMI(GPP_D0, NONE, RSMRST, LEVEL, NONE), /* GPIO */ PAD_NC(GPP_D1, NONE), /* GPIO */ PAD_NC(GPP_D2, NONE), /* GPIO */ PAD_NC(GPP_D3, NONE), /* GPIO */ @@ -130,8 +130,8 @@ PAD_NC(GPP_D13, NONE), /* GPIO */ PAD_NC(GPP_D14, NONE), /* GPIO */ PAD_NC(GPP_D15, NONE), /* GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, RSMRST, OFF, ACPI), /* GPIO */ - PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_D16, 0, RSMRST), /* GPIO */ + PAD_CFG_GPO(GPP_D17, 0, RSMRST), /* GPIO */ PAD_NC(GPP_D18, NONE), /* GPIO */ PAD_CFG_GPO(GPP_D19, 0, RSMRST), /* GPIO */ PAD_NC(GPP_D20, NONE), /* GPIO */ @@ -179,8 +179,8 @@ PAD_NC(GPP_I5, NONE), /* GPIO */ PAD_NC(GPP_I6, NONE), /* GPIO */ PAD_NC(GPP_I7, NONE), /* GPIO */ - PAD_NC(GPP_I8, NONE), /* GPIO */ - PAD_NC(GPP_I9, NONE), /* GPIO */ + PAD_CFG_NF(GPP_I8, NONE, RSMRST, NF2), /* PCI_DIS */ + PAD_CFG_NF(GPP_I9, NONE, RSMRST, NF2), /* LAN_DIS */ PAD_NC(GPP_I10, NONE), /* GPIO */ /* ------- GPIO Community 4 ------- */ @@ -218,9 +218,9 @@ PAD_NC(GPP_K4, NONE), /* GPIO */ PAD_NC(GPP_K5, NONE), /* GPIO */ PAD_NC(GPP_K6, NONE), /* GPIO */ - PAD_NC(GPP_K7, NONE), /* GPIO */ - PAD_NC(GPP_K8, NONE), /* GPIO */ - PAD_NC(GPP_K9, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_K7, NONE, RSMRST, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_K8, NONE, RSMRST, NF1), /* LAN_NCSI_ARB_IN */ + PAD_CFG_NF(GPP_K9, NONE, RSMRST, NF1), /* LAN_NCSI_ARB_OUT */ PAD_CFG_NF(GPP_K10, NONE, RSMRST, NF1), /* PE_RST# */ /* ------- GPIO Community 5 ------- */ @@ -270,9 +270,9 @@ /* GPP_H16 - RESERVED */ /* GPP_H17 - RESERVED */ PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, RSMRST, OFF, ACPI), /* GPIO */ - PAD_NC(GPP_H19, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, RSMRST, OFF, ACPI), /* GPIO */ PAD_CFG_NF(GPP_H20, NONE, RSMRST, NF2), /* SSATAXPCIE2 */ - PAD_NC(GPP_H21, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, RSMRST, OFF, ACPI), /* GPIO */ PAD_NC(GPP_H22, NONE), /* GPIO */ PAD_NC(GPP_H23, NONE), /* GPIO */ @@ -303,7 +303,7 @@ static const struct pad_config early_gpio_table[] = { /* ------- GPIO Community 0 ------- */ /* ------- GPIO Group GPP_A ------- */ - PAD_CFG_NF(GPP_A0, NONE, RSMRST, NF1), /* RCIN# */ + PAD_CFG_NF(GPP_A0, NONE, RSMRST, NF3), /* ESPI_ALERT1# */ PAD_CFG_NF(GPP_A1, NONE, RSMRST, NF1), /* LAD0 */ PAD_CFG_NF(GPP_A2, NONE, RSMRST, NF1), /* LAD1 */ PAD_CFG_NF(GPP_A3, NONE, RSMRST, NF1), /* LAD2 */ @@ -313,9 +313,9 @@ PAD_CFG_NF(GPP_A8, NONE, RSMRST, NF1), /* CLKRUN# */ PAD_CFG_NF(GPP_A9, NONE, RSMRST, NF1), /* CLKOUT_LPC0 */ PAD_NC(GPP_A10, NONE), /* GPIO */ - PAD_NC(GPP_A13, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A13, NONE, RSMRST, NF1), /* SUSWARN#/SUSPWRDNACK */ PAD_NC(GPP_A14, NONE), /* GPIO */ - PAD_NC(GPP_A15, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A15, NONE, RSMRST, NF1), /* SUS_ACK# */ }; #endif /* CFG_GPIO_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Gerrit-Change-Number: 47229 Gerrit-PatchSet: 11 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: util/cbfstool/fit.c: Add support for adding Boot Guard manifests
by Arthur Heymans (Code Review) 11 Dec '20

11 Dec '20

Hello Michał Żygowski, Christian Walter, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48469 to review the following change. Change subject: util/cbfstool/fit.c: Add support for adding Boot Guard manifests ...................................................................... util/cbfstool/fit.c: Add support for adding Boot Guard manifests Change-Id: I8221590cad16cffea3f8b50dd880a77934b78ea8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M util/cbfstool/fit.c 1 file changed, 45 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/48469/1 diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index 44573ca..63956dd 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -434,6 +434,43 @@ fit_entry_add_size(&fit->header, sizeof(struct fit_entry)); } +/* + * There can be zero or one FIT_TYPE_BOOT_POLICY entries + * + * The caller has to provide valid arguments as those aren't verified. + */ +static void update_fit_boot_policy_entry(struct fit_table *fit, + struct fit_entry *entry, + uint64_t boot_policy_addr, + uint32_t boot_policy_size) +{ + entry->address = boot_policy_addr; + entry->type_checksum_valid = FIT_TYPE_BOOT_POLICY; + entry->size_reserved = boot_policy_size; + entry->version = FIT_TXT_VERSION; + entry->checksum = 0; + fit_entry_add_size(&fit->header, sizeof(struct fit_entry)); +} + +/* + * There can be zero or one FIT_TYPE_KEY_MANIFEST entries + * + * The caller has to provide valid arguments as those aren't verified. + */ +static void update_fit_key_manifest_entry(struct fit_table *fit, + struct fit_entry *entry, + uint64_t key_manifest_addr, + uint32_t key_manifest_size) +{ + entry->address = key_manifest_addr; + + entry->type_checksum_valid = FIT_TYPE_KEY_MANIFEST; + entry->size_reserved = key_manifest_size; + entry->version = FIT_TXT_VERSION; + entry->checksum = 0; + fit_entry_add_size(&fit->header, sizeof(struct fit_entry)); +} + /* Special case for ucode CBFS file, as it might contain more than one ucode */ int fit_add_microcode_file(struct fit_table *fit, struct cbfs_image *image, @@ -626,10 +663,10 @@ case FIT_TYPE_BIOS_STARTUP: case FIT_TYPE_BIOS_POLICY: case FIT_TYPE_TXT_POLICY: - return 1; - case FIT_TYPE_TPM_POLICY: case FIT_TYPE_KEY_MANIFEST: case FIT_TYPE_BOOT_POLICY: + return 1; + case FIT_TYPE_TPM_POLICY: default: return 0; } @@ -684,6 +721,12 @@ case FIT_TYPE_TXT_POLICY: update_fit_txt_policy_entry(fit, entry, offset); break; + case FIT_TYPE_KEY_MANIFEST: + update_fit_key_manifest_entry(fit, entry, offset, len); + break; + case FIT_TYPE_BOOT_POLICY: + update_fit_boot_policy_entry(fit, entry, offset, len); + break; default: return 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/48469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8221590cad16cffea3f8b50dd880a77934b78ea8 Gerrit-Change-Number: 48469 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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