coreboot-gerrit December 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: drop duplicate PM ACPI ti...
by Michael Niewöhner (Code Review) 11 Dec '20

11 Dec '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45958 to look at the new patch set (#37). Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: drop duplicate PM ACPI timer disabling ...................................................................... [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: drop duplicate PM ACPI timer disabling FSP already disables the PM ACPI timer, when EnableTcoTimer=0, so there is no need to do it again in coreboot. Change-Id: I5594ac423d6dff4c3212d657c242137492dc5d2a Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/finalize.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/finalize.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/finalize.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/finalize.c 18 files changed, 5 insertions(+), 108 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45958/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/45958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5594ac423d6dff4c3212d657c242137492dc5d2a Gerrit-Change-Number: 45958 Gerrit-PatchSet: 37 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/ipmi: add code to set BMC/IPMI enablement from jumper
by Michael Niewöhner (Code Review) 11 Dec '20

11 Dec '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48094 to look at the new patch set (#15). Change subject: drivers/ipmi: add code to set BMC/IPMI enablement from jumper ...................................................................... drivers/ipmi: add code to set BMC/IPMI enablement from jumper Some boards, like the Supermicro X11SSM-F, have a jumper for enabling or disabling the BMC and IPMI. Add a new devicetree driver option to set the GPIO used for the jumper and enable or disable IPMI according to its value. This gets used in the follow-up change by Supermicro X11SSM-F. Test: Boot with jumper set to each enabled and disabled and see if IPMI gets enabled. Successfully tested on Supermicro X11SSM-F. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Icde3232843a7138797a4b106560f170972edeb9c --- M src/drivers/ipmi/chip.h M src/drivers/ipmi/ipmi_kcs_ops.c 2 files changed, 24 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/48094/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/48094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icde3232843a7138797a4b106560f170972edeb9c Gerrit-Change-Number: 48094 Gerrit-PatchSet: 15 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [RFC] move chip_ops to comm/block/gpio
by Michael Niewöhner (Code Review) 11 Dec '20

11 Dec '20

Michael Niewöhner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/48343 ) Change subject: [RFC] move chip_ops to comm/block/gpio ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/48343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2ad643f27f0183d6466aec716be8b5d4a289aa6 Gerrit-Change-Number: 48343 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/amd/common/block/smbus: refactor fch_smbus_init
by Felix Held (Code Review) 11 Dec '20

11 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48434 ) Change subject: soc/amd/common/block/smbus: refactor fch_smbus_init ...................................................................... soc/amd/common/block/smbus: refactor fch_smbus_init Move the setup of the base address to a separate function and explicitly set the SMBUS and ASF I/O port decode even though it is expected to already be set after reset. Change-Id: I8072ab78985021d19b6528100c674ecdd777e62e Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/smbus/smbus_early_fch.c 2 files changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/48434/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 3887f73..865ad48 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -15,12 +15,12 @@ * newer SoCs, but not for the generations with separate FCH or Kabini. */ #define PM_DECODE_EN 0x00 +#define SMBUS_ASF_IO_BASE_SHIFT 8 +#define SMBUS_ASF_IO_BASE_MASK (0xff << SMBUS_ASF_IO_BASE_SHIFT) #define SMBUS_ASF_IO_EN (1 << 4) #define CF9_IO_EN (1 << 1) #define LEGACY_IO_EN (1 << 0) -#define SMB_ASF_IO_BASE 0x01 /* part of PM_DECODE_EN */ - /* * Earlier devices enable the ACPIMMIO bank decodes in PMx24. All discrete FCHs * and the Kabini SoC fall into this category. Kabini's successor, Mullins, uses diff --git a/src/soc/amd/common/block/smbus/smbus_early_fch.c b/src/soc/amd/common/block/smbus/smbus_early_fch.c index 3d04778..2b20425 100644 --- a/src/soc/amd/common/block/smbus/smbus_early_fch.c +++ b/src/soc/amd/common/block/smbus/smbus_early_fch.c @@ -3,14 +3,24 @@ #include <stdint.h> #include <amdblocks/acpimmio.h> #include <amdblocks/smbus.h> -#include <soc/southbridge.h> +#include <soc/iomap.h> + +static void fch_smbus_enable_decode(uint16_t base) +{ + uint32_t val = pm_read32(PM_DECODE_EN); + /* Configure upper byte of the I/O address; lower byte is always 0 */ + val = (val & ~SMBUS_ASF_IO_BASE_MASK) | (base & SMBUS_ASF_IO_BASE_MASK); + /* Set enable decode bit even though it should already be set */ + val |= SMBUS_ASF_IO_EN; + pm_write32(PM_DECODE_EN, val); +} void fch_smbus_init(void) { /* 400 kHz smbus speed. */ const uint8_t smbus_speed = (66000000 / (400000 * 4)); - pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); + fch_smbus_enable_decode(SMB_BASE_ADDR); smbus_write8(SMBTIMING, smbus_speed); /* Clear all SMBUS status bits */ smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); -- To view, visit https://review.coreboot.org/c/coreboot/+/48434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8072ab78985021d19b6528100c674ecdd777e62e Gerrit-Change-Number: 48434 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in em100[master]: Update xz to upstream revision 090e6a0
by Stefan Reinauer (Code Review) 11 Dec '20

11 Dec '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/47898 ) Change subject: Update xz to upstream revision 090e6a0 ...................................................................... Update xz to upstream revision 090e6a0 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I700e7f93d713d3c181125dd751ff84d74fd2efe2 --- M xz/README M xz/xz.h M xz/xz_crc32.c M xz/xz_crc64.c M xz/xz_dec_bcj.c M xz/xz_dec_lzma2.c M xz/xz_lzma2.h M xz/xz_stream.h 8 files changed, 28 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/98/47898/1 diff --git a/xz/README b/xz/README index 6cbf1f0..172e771 100644 --- a/xz/README +++ b/xz/README @@ -1 +1 @@ -These files are unmodified versions of xz-embedded 40d291b. +These files are unmodified versions of xz-embedded 090e6a0. diff --git a/xz/xz.h b/xz/xz.h index 0a4b38d..d24b94a 100644 --- a/xz/xz.h +++ b/xz/xz.h @@ -2,7 +2,7 @@ * XZ decompressor * * Authors: Lasse Collin <lasse.collin(a)tukaani.org> - * Igor Pavlov <http://7-zip.org/> + * Igor Pavlov <https://7-zip.org/> * * This file has been put into the public domain. * You can do whatever you want with this file. @@ -32,7 +32,7 @@ * enum xz_mode - Operation mode * * @XZ_SINGLE: Single-call mode. This uses less RAM than - * than multi-call modes, because the LZMA2 + * multi-call modes, because the LZMA2 * dictionary doesn't need to be allocated as * part of the decoder state. All required data * structures are allocated at initialization, diff --git a/xz/xz_crc32.c b/xz/xz_crc32.c index 34532d1..5627b00 100644 --- a/xz/xz_crc32.c +++ b/xz/xz_crc32.c @@ -2,7 +2,7 @@ * CRC32 using the polynomial from IEEE-802.3 * * Authors: Lasse Collin <lasse.collin(a)tukaani.org> - * Igor Pavlov <http://7-zip.org/> + * Igor Pavlov <https://7-zip.org/> * * This file has been put into the public domain. * You can do whatever you want with this file. diff --git a/xz/xz_crc64.c b/xz/xz_crc64.c index ca1caee..215e04d 100644 --- a/xz/xz_crc64.c +++ b/xz/xz_crc64.c @@ -4,7 +4,7 @@ * This file is similar to xz_crc32.c. See the comments there. * * Authors: Lasse Collin <lasse.collin(a)tukaani.org> - * Igor Pavlov <http://7-zip.org/> + * Igor Pavlov <https://7-zip.org/> * * This file has been put into the public domain. * You can do whatever you want with this file. diff --git a/xz/xz_dec_bcj.c b/xz/xz_dec_bcj.c index a768e6d..72ddac6 100644 --- a/xz/xz_dec_bcj.c +++ b/xz/xz_dec_bcj.c @@ -2,7 +2,7 @@ * Branch/Call/Jump (BCJ) filter decoders * * Authors: Lasse Collin <lasse.collin(a)tukaani.org> - * Igor Pavlov <http://7-zip.org/> + * Igor Pavlov <https://7-zip.org/> * * This file has been put into the public domain. * You can do whatever you want with this file. diff --git a/xz/xz_dec_lzma2.c b/xz/xz_dec_lzma2.c index 156f26f..2deb544 100644 --- a/xz/xz_dec_lzma2.c +++ b/xz/xz_dec_lzma2.c @@ -2,7 +2,7 @@ * LZMA2 decoder * * Authors: Lasse Collin <lasse.collin(a)tukaani.org> - * Igor Pavlov <http://7-zip.org/> + * Igor Pavlov <https://7-zip.org/> * * This file has been put into the public domain. * You can do whatever you want with this file. @@ -387,7 +387,14 @@ *left -= copy_size; - memcpy(dict->buf + dict->pos, b->in + b->in_pos, copy_size); + /* + * If doing in-place decompression in single-call mode and the + * uncompressed size of the file is larger than the caller + * thought (i.e. it is invalid input!), the buffers below may + * overlap and cause undefined behavior with memcpy(). + * With valid inputs memcpy() would be fine here. + */ + memmove(dict->buf + dict->pos, b->in + b->in_pos, copy_size); dict->pos += copy_size; if (dict->full < dict->pos) @@ -397,7 +404,11 @@ if (dict->pos == dict->end) dict->pos = 0; - memcpy(b->out + b->out_pos, b->in + b->in_pos, + /* + * Like above but for multi-call mode: use memmove() + * to avoid undefined behavior with invalid input. + */ + memmove(b->out + b->out_pos, b->in + b->in_pos, copy_size); } @@ -421,6 +432,12 @@ if (dict->pos == dict->end) dict->pos = 0; + /* + * These buffers cannot overlap even if doing in-place + * decompression because in multi-call mode dict->buf + * has been allocated by us in this file; it's not + * provided by the caller like in single-call mode. + */ memcpy(b->out + b->out_pos, dict->buf + dict->start, copy_size); } diff --git a/xz/xz_lzma2.h b/xz/xz_lzma2.h index 071d67b..92d852d 100644 --- a/xz/xz_lzma2.h +++ b/xz/xz_lzma2.h @@ -2,7 +2,7 @@ * LZMA2 definitions * * Authors: Lasse Collin <lasse.collin(a)tukaani.org> - * Igor Pavlov <http://7-zip.org/> + * Igor Pavlov <https://7-zip.org/> * * This file has been put into the public domain. * You can do whatever you want with this file. diff --git a/xz/xz_stream.h b/xz/xz_stream.h index 66cb5a7..430bb3a 100644 --- a/xz/xz_stream.h +++ b/xz/xz_stream.h @@ -19,7 +19,7 @@ /* * See the .xz file format specification at - * http://tukaani.org/xz/xz-file-format.txt + * https://tukaani.org/xz/xz-file-format.txt * to understand the container format. */ -- To view, visit https://review.coreboot.org/c/em100/+/47898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I700e7f93d713d3c181125dd751ff84d74fd2efe2 Gerrit-Change-Number: 47898 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Register APCB and APCB_BK respectively
by Bao Zheng (Code Review) 11 Dec '20

11 Dec '20

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48524 to review the following change. Change subject: amdfwtool: Register APCB and APCB_BK respectively ...................................................................... amdfwtool: Register APCB and APCB_BK respectively We took the assumption the APCB(0x60) and APCB_BK(0x68) are the same file. For picasso, they are. For later programe, they are not. Change-Id: Idea7847691c2b511b489c306f04a8cb8945fd057 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc M util/amdfwtool/amdfwtool.c 2 files changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/48524/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 7cbae92..962081c 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -188,7 +188,10 @@ OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ - --instance $(shell printf "%x" $$(($(i)-1))) --apcb )) + --instance $(shell printf "%x" $$(($(i)-1))) --apcb ) ) +OPT_PSP_APCB_FILES_BK=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ + $(call add_opt_prefix, $(word $(i), $(PSP_APCB_FILES)), \ + --instance $(shell printf "1%x" $$(($(i)-1))) --apcb ) ) OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base) OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin) @@ -217,6 +220,7 @@ DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ + $(OPT_PSP_APCB_FILES_BK) \ $(OPT_APOB_ADDR) \ $(OPT_PSP_BIOSBIN_FILE) \ $(OPT_PSP_BIOSBIN_DEST) \ diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 36d669b..4edf7bc 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1333,9 +1333,11 @@ sub = 0; break; case 'a': - register_bdt_data(AMD_BIOS_APCB, sub, instance, optarg); - register_bdt_data(AMD_BIOS_APCB_BK, sub, - instance, optarg); + if ((instance & 0xF0) == 0) + register_bdt_data(AMD_BIOS_APCB, sub, instance & 0xF, optarg); + else + register_bdt_data(AMD_BIOS_APCB_BK, sub, + instance & 0xF, optarg); sub = instance = 0; break; case 'Q': -- To view, visit https://review.coreboot.org/c/coreboot/+/48524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idea7847691c2b511b489c306f04a8cb8945fd057 Gerrit-Change-Number: 48524 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

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Change in coreboot[master]: util/amdfwtool: Fix EFS generation polarity
by Marshall Dawson (Code Review) 11 Dec '20

11 Dec '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47769 ) Change subject: util/amdfwtool: Fix EFS generation polarity ...................................................................... util/amdfwtool: Fix EFS generation polarity The DWORD used to indicate the Embedded Firmware Structure's generation uses 1 to indicate a first-gen structure, e.g. a SPI device's erased value of 0xffffffff. A 0 in bit 0 is how Client PSPs will interpret the structure as designed for second-gen. This change and the original addition should have no effects on any current products as none interpret offset 0x24. BUG=b:158755102 TEST=inspect EFS in coreboot.rom Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: If391f356a1811ed04acdfe9ab9de2e146f6ef5fd --- M util/amdfwtool/amdfwtool.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/47769/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 9cf6a4f..36d669b 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -333,7 +333,7 @@ uint32_t bios0_entry; /* todo: add way to select correct entry */ uint32_t bios1_entry; uint32_t bios2_entry; - uint32_t second_gen_efs; + uint32_t second_gen_efs; /* Client SKUs b0=1 is Gen1, b1=0 is Gen2, Servers TBD */ uint32_t bios3_entry; uint32_t reserved_2Ch; uint32_t promontory_fw_ptr; @@ -1182,13 +1182,11 @@ } switch (soc_id) { case PLATFORM_STONEYRIDGE: - amd_romsig->second_gen_efs = 0; amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode; amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed; break; case PLATFORM_RAVEN: case PLATFORM_PICASSO: - amd_romsig->second_gen_efs = 0; amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; switch (efs_spi_micron_flag) { @@ -1205,7 +1203,7 @@ break; case PLATFORM_RENOIR: case PLATFORM_LUCIENNE: - amd_romsig->second_gen_efs = 1; + amd_romsig->second_gen_efs = 0xfffffffe; amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; switch (efs_spi_micron_flag) { -- To view, visit https://review.coreboot.org/c/coreboot/+/47769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If391f356a1811ed04acdfe9ab9de2e146f6ef5fd Gerrit-Change-Number: 47769 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P)
by Michael Niewöhner (Code Review) 11 Dec '20

11 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P) ...................................................................... Patch Set 10: (11 comments) https://review.coreboot.org/c/coreboot/+/38978/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38978/7//COMMIT_MSG@37 PS7, Line 37: - Touchpad. Hangs off either EC or some I2C controller and needs ACPI. > Well, it's connected to the EC's PS/2 port 3 (according to the kb9012 ds). […] Done https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… PS5, Line 223: register "SendVrMbxCmd" = "2" > What I could find out: There are issues with (some) IMVP8 controllers. […] Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 37: register "SataTestMode" = "1" > Yes, I do want that. Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 40: register "SataPortsDevSlp[0]" = "0" : register "SataPortsDevSlp[1]" = "0" : > schematics say nooooo ;) Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 42: SataSpeedLimit" = "3" > speed 3 (also matches 0) is the default already Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 86: register "usb2_ports[3]" = "USB2_PORT_EMPTY" # N/C > not required anymore; drop; see CB:45106 Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 93: register "usb3_ports[1]" = "USB3_PORT_EMPTY" # N/C : register "usb3_ports[2]" = "USB3_PORT_EMPTY" # N/C : register "usb3_ports[3]" = "USB3_PORT_EMPTY" # N/C : > not required anymore; drop them; see CB:45106 Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 108: device pci 04.0 off end # CPU Thermal Subsystem > it's not about EC ACPI and it's not only about DPTF. […] Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/gpio.c: https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 7: #define PAD_CFG_NF_BUF_TRIG(a, b, c, d, e, f) PAD_CFG_NF(a, b, c, d) > I'd rather re-do the whole file. Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 144: _PAD_CFG_STRUCT(GPP_B3, : PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | : PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | : PAD_BUF(TX_DISABLE), : PAD_PULL(NONE)), : > I'll re-do the whole file Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/romstage.c: https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 32: /* These settings are most likely useless if using a release build of FSP */ : mem_cfg->PcdDebugInterfaceFlags = 2; /* 2: Enable UART */ : mem_cfg->PcdSerialIoUartNumber = 2; /* 2: Use UART #2 */ : mem_cfg->PcdSerialDebugBaudRate = 7; /* 7: 115200 baud */ : mem_cfg->PcdSerialDebugLevel = 3; /* 3: Log <= Info */ : > well, that's all fsp defaults (except the TH bit in PcdSerialIoUartNumber, which doesn't do anything […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 10 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Fri, 11 Dec 2020 19:29:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P)
by build bot (Jenkins) (Code Review) 11 Dec '20

11 Dec '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P) ...................................................................... Patch Set 10: (3 comments) https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-57… File src/mainboard/acer/es1-572/gpio.c: https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-57… PS10, Line 131: PAD_CFG_GPI_SCI_LOW(GPP_E16, UP_20K, DEEP, LEVEL),/* GPP_E16 / EC_SCI# */ // TODO SMI? smihandler line over 96 characters https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-57… File src/mainboard/acer/es1-572/romstage.c: https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-57… PS10, Line 20: FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV) https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-57… PS10, Line 21: FSP_M_TEST_CONFIG *const test_cfg = &mupd->FspmTestConfig; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 10 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Fri, 11 Dec 2020 19:28:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P)
by Michael Niewöhner (Code Review) 11 Dec '20

11 Dec '20

Michael Niewöhner has uploaded a new patch set (#10) to the change originally created by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P) ...................................................................... mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P) Both the Acer Aspire ES1-572 and the Acer Extensa 2540 use the same mainboard, the Compal LA-E061P. This change adds support for it. See Documentation/mainboard/acer/aspire_es1-572_and_extensa_2540.md for what is working and what not. Needs test: - Battery - Touchpad (seems to work but hangs often.. maybe my tp is defective) - Card reader - Lid - Audio Todo: - make s3 work (again) - make LID ACPI code work - make ec acpi code actually work (currently just dropped in vendor code and applied some replacements like One -> 1 and so on) Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- A Documentation/mainboard/acer/aspire_es1-572_and_extensa_2540.md A Documentation/mainboard/acer/la-e061p_flash_diode_1.jpg A Documentation/mainboard/acer/la-e061p_flash_diode_2.jpg A Documentation/mainboard/acer/la-e061p_flash_diode_3.jpg A Documentation/mainboard/acer/la-e061p_uart.jpg M Documentation/mainboard/index.md A src/mainboard/acer/es1-572/Kconfig A src/mainboard/acer/es1-572/Kconfig.name A src/mainboard/acer/es1-572/Makefile.inc A src/mainboard/acer/es1-572/acpi/ec.asl A src/mainboard/acer/es1-572/acpi/lid.asl A src/mainboard/acer/es1-572/acpi/mainboard.asl A src/mainboard/acer/es1-572/acpi/superio.asl A src/mainboard/acer/es1-572/board_info.txt A src/mainboard/acer/es1-572/bootblock.c A src/mainboard/acer/es1-572/cmos.default A src/mainboard/acer/es1-572/cmos.layout A src/mainboard/acer/es1-572/data.vbt A src/mainboard/acer/es1-572/devicetree.cb A src/mainboard/acer/es1-572/dsdt.asl A src/mainboard/acer/es1-572/gma-mainboard.ads A src/mainboard/acer/es1-572/gpio.c A src/mainboard/acer/es1-572/gpio_early.c A src/mainboard/acer/es1-572/hda_verb.c A src/mainboard/acer/es1-572/include/mainboard/gpio.h A src/mainboard/acer/es1-572/ramstage.c A src/mainboard/acer/es1-572/romstage.c 27 files changed, 1,849 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/38978/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 10 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2020