coreboot-gerrit December 2020

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Michael Niewöhner (Code Review) 13 Dec '20

13 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48583 ) Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... Patch Set 7: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Dec 2020 23:21:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/include/spc/gpio: fix pin numbers in comments
by Felix Held (Code Review) 13 Dec '20

13 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48563 ) Change subject: soc/amd/*/include/spc/gpio: fix pin numbers in comments ...................................................................... soc/amd/*/include/spc/gpio: fix pin numbers in comments Change-Id: I9e91f28659c49927aaa4c7cd67f73bb11258c27c Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/include/soc/gpio.h M src/soc/amd/stoneyridge/include/soc/gpio.h 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/48563/1 diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index 4fbb937..8f33ca6 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -14,7 +14,7 @@ #define SOC_GPIO_TOTAL_PINS 145 -/* Bank 0: GPIO_0 - GPIO_62 */ +/* Bank 0: GPIO_0 - GPIO_63 */ #define GPIO_0 0 #define GPIO_1 1 #define GPIO_2 2 @@ -79,7 +79,7 @@ #define GPIO_120 120 #define GPIO_121 121 -/* Bank 2: GPIO_128 - GPIO_183 */ +/* Bank 2: GPIO_128 - GPIO_191 */ #define GPIO_129 129 #define GPIO_130 130 #define GPIO_131 131 diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 8bfb1f6..714d219 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -14,7 +14,7 @@ #define SOC_GPIO_TOTAL_PINS 149 -/* Bank 0: GPIO_0 - GPIO_62 */ +/* Bank 0: GPIO_0 - GPIO_63 */ #define GPIO_0 0 #define GPIO_1 1 #define GPIO_2 2 @@ -89,7 +89,7 @@ #define GPIO_122 122 #define GPIO_126 126 -/* Bank 2: GPIO_128 - GPIO_183 */ +/* Bank 2: GPIO_128 - GPIO_191 */ #define GPIO_129 129 #define GPIO_130 130 #define GPIO_131 131 -- To view, visit https://review.coreboot.org/c/coreboot/+/48563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e91f28659c49927aaa4c7cd67f73bb11258c27c Gerrit-Change-Number: 48563 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/gpio: use all-y in Makefile
by Felix Held (Code Review) 13 Dec '20

13 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48585 ) Change subject: soc/amd/common/block/gpio: use all-y in Makefile ...................................................................... soc/amd/common/block/gpio: use all-y in Makefile Change-Id: Ib77e3d088cc07da4e43a63afb863bb90796f9a37 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/gpio_banks/Makefile.inc 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/48585/1 diff --git a/src/soc/amd/common/block/gpio_banks/Makefile.inc b/src/soc/amd/common/block/gpio_banks/Makefile.inc index 5b738bd..616b589 100644 --- a/src/soc/amd/common/block/gpio_banks/Makefile.inc +++ b/src/soc/amd/common/block/gpio_banks/Makefile.inc @@ -1,10 +1,6 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS),y) -bootblock-y += gpio.c -verstage-y += gpio.c -romstage-y += gpio.c -postcar-y += gpio.c -ramstage-y += gpio.c +all-y += gpio.c smm-y += gpio.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS -- To view, visit https://review.coreboot.org/c/coreboot/+/48585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib77e3d088cc07da4e43a63afb863bb90796f9a37 Gerrit-Change-Number: 48585 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: add caching setup in bootblock
by Felix Held (Code Review) 13 Dec '20

13 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48517 ) Change subject: soc/amd/cezanne: add caching setup in bootblock ...................................................................... soc/amd/cezanne: add caching setup in bootblock The code can likely be factored out to common code, but since I'm not entirely sure yet that there will be no differences, I'll copy for now instead. Change-Id: I5fc158518cf9534ab9727f3305abeb4b34049e76 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/bootblock.c M src/soc/amd/cezanne/include/soc/iomap.h 3 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/48517/1 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 15db2e6..89c0df9 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -2,6 +2,8 @@ ifeq ($(CONFIG_SOC_AMD_CEZANNE),y) +subdirs-y += ../../../cpu/x86/mtrr + all-y += config.c bootblock-y += bootblock.c diff --git a/src/soc/amd/cezanne/bootblock.c b/src/soc/amd/cezanne/bootblock.c index 9fb99bd..4d791e0 100644 --- a/src/soc/amd/cezanne/bootblock.c +++ b/src/soc/amd/cezanne/bootblock.c @@ -3,12 +3,90 @@ #include <amdblocks/amd_pci_mmconf.h> #include <bootblock_common.h> #include <console/console.h> +#include <cpu/amd/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/x86/tsc.h> +#include <soc/iomap.h> #include <soc/southbridge.h> #include <stdint.h> +/* + * PSP performs the memory training and setting up DRAM map prior to x86 cores being released. + * Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, route lower memory addresses + * covered by fixed MTRRs to DRAM except for 0xa0000-0xc0000. + */ +static void set_caching(void) +{ + msr_t top_mem; + msr_t sys_cfg; + msr_t mtrr_def_type; + msr_t fixed_mtrr_ram; + msr_t fixed_mtrr_mmio; + struct var_mtrr_context mtrr_ctx; + + var_mtrr_context_init(&mtrr_ctx, NULL); + top_mem = rdmsr(TOP_MEM); + /* Enable RdDram and WrDram attributes in fixed MTRRs. */ + sys_cfg = rdmsr(SYSCFG_MSR); + sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; + + /* Fixed MTRR constants. */ + fixed_mtrr_ram.lo = fixed_mtrr_ram.hi = + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 0) | + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 8) | + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) | + ((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24); + fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi = + ((MTRR_TYPE_UNCACHEABLE) << 0) | + ((MTRR_TYPE_UNCACHEABLE) << 8) | + ((MTRR_TYPE_UNCACHEABLE) << 16) | + ((MTRR_TYPE_UNCACHEABLE) << 24); + + /* Prep default MTRR type. */ + mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR); + mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK; + mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE; + mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; + + disable_cache(); + + wrmsr(SYSCFG_MSR, sys_cfg); + + clear_all_var_mtrr(); + + var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK); + var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + /* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */ + wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio); + wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram); + wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram); + + wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type); + + /* Enable Fixed and Variable MTRRs. */ + sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn; + sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB; + /* AGESA currently expects SYSCFG_MSR_MtrrFixDramModEn to be set. Once + MP init happens in coreboot proper it can be knocked down. */ + wrmsr(SYSCFG_MSR, sys_cfg); + + enable_cache(); +} + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + set_caching(); enable_pci_mmconf(); /* diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 4d47f7e..b377ee3 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -3,6 +3,9 @@ #ifndef AMD_CEZANNE_IOMAP_H #define AMD_CEZANNE_IOMAP_H +/* MMIO Ranges */ +#define FLASH_BASE_ADDR ((0xffffffff - CONFIG_ROM_SIZE) + 1) + /* I/O Ranges */ #define NCP_ERR 0x00f0 #define SMB_BASE_ADDR 0x0b00 -- To view, visit https://review.coreboot.org/c/coreboot/+/48517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fc158518cf9534ab9727f3305abeb4b34049e76 Gerrit-Change-Number: 48517 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/ipmi: add code to set BMC/IPMI enablement from jumper
by Michael Niewöhner (Code Review) 13 Dec '20

13 Dec '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48094 to look at the new patch set (#21). Change subject: drivers/ipmi: add code to set BMC/IPMI enablement from jumper ...................................................................... drivers/ipmi: add code to set BMC/IPMI enablement from jumper Some boards, like the Supermicro X11SSM-F, have a jumper for enabling or disabling the BMC and IPMI. Add a new devicetree driver option to set the GPIO used for the jumper and enable or disable IPMI according to its value. This gets used in the follow-up change by Supermicro X11SSM-F. Test: Boot with jumper set to each enabled and disabled and see if IPMI gets enabled. Successfully tested on Supermicro X11SSM-F. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Icde3232843a7138797a4b106560f170972edeb9c --- M src/drivers/ipmi/chip.h M src/drivers/ipmi/ipmi_kcs_ops.c 2 files changed, 28 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/48094/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/48094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icde3232843a7138797a4b106560f170972edeb9c Gerrit-Change-Number: 48094 Gerrit-PatchSet: 21 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/ipmi: add code to set BMC/IPMI enablement from jumper
by build bot (Jenkins) (Code Review) 13 Dec '20

13 Dec '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48094 ) Change subject: drivers/ipmi: add code to set BMC/IPMI enablement from jumper ...................................................................... Patch Set 20: (1 comment) https://review.coreboot.org/c/coreboot/+/48094/20/src/drivers/ipmi/ipmi_kcs… File src/drivers/ipmi/ipmi_kcs_ops.c: https://review.coreboot.org/c/coreboot/+/48094/20/src/drivers/ipmi/ipmi_kcs… PS20, Line 94: dev->enabled = conf->gpio_dev->ops->ops_gpio->get(conf->bmc_jumper_gpio); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/48094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icde3232843a7138797a4b106560f170972edeb9c Gerrit-Change-Number: 48094 Gerrit-PatchSet: 20 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Dec 2020 21:52:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/ipmi: add code to set BMC/IPMI enablement from jumper
by Michael Niewöhner (Code Review) 13 Dec '20

13 Dec '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48094 to look at the new patch set (#20). Change subject: drivers/ipmi: add code to set BMC/IPMI enablement from jumper ...................................................................... drivers/ipmi: add code to set BMC/IPMI enablement from jumper Some boards, like the Supermicro X11SSM-F, have a jumper for enabling or disabling the BMC and IPMI. Add a new devicetree driver option to set the GPIO used for the jumper and enable or disable IPMI according to its value. This gets used in the follow-up change by Supermicro X11SSM-F. Test: Boot with jumper set to each enabled and disabled and see if IPMI gets enabled. Successfully tested on Supermicro X11SSM-F. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Icde3232843a7138797a4b106560f170972edeb9c --- M src/drivers/ipmi/chip.h M src/drivers/ipmi/ipmi_kcs_ops.c 2 files changed, 26 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/48094/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/48094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icde3232843a7138797a4b106560f170972edeb9c Gerrit-Change-Number: 48094 Gerrit-PatchSet: 20 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: device + util/sconfig: introduce new device `gpio`
by Michael Niewöhner (Code Review) 13 Dec '20

13 Dec '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48582 to look at the new patch set (#4). Change subject: device + util/sconfig: introduce new device `gpio` ...................................................................... device + util/sconfig: introduce new device `gpio` Introduce a new device `gpio` that is going to be used for generic abstraction of gpio operations in the devicetree. This change adds the nev device type to sconfig and adds generic gpio operations to the `device_operations` struct. Change-Id: Ic4572ad8b37bd1afd2fb213b2c67fb8aec536786 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/device/device_const.c M src/device/device_util.c M src/include/device/device.h A src/include/device/gpio.h M src/include/device/path.h M util/sconfig/lex.yy.c_shipped M util/sconfig/main.c M util/sconfig/sconfig.l M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.tab.h_shipped M util/sconfig/sconfig.y 11 files changed, 335 insertions(+), 390 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/48582/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/48582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4572ad8b37bd1afd2fb213b2c67fb8aec536786 Gerrit-Change-Number: 48582 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: update spm.c
by Roger Lu (Code Review) 13 Dec '20

13 Dec '20

Hello Roger Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48450 to review the following change. Change subject: update spm.c ...................................................................... update spm.c 1. Replace 0x40000000 with SPM_SYSTEM_BASE_OFFSET 2. Change print level - old: printk(BIOS_INFO, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n", - new: printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n", 3. Always kick IM to refetch our trusted data. Change-Id: I185200655f7c9d18a4fc1dd95b6a2a6e4e6966c1 --- M src/soc/mediatek/mt8192/spm.c 1 file changed, 10 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/48450/1 diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index 1c552bd..0eb46ac 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -10,6 +10,7 @@ #include <soc/symbols.h> #include <timer.h> +#define SPM_SYSTEM_BASE_OFFSET 0x40000000 #define SPMFW_HEADER_SIZE 16 static const struct pwr_ctrl spm_init_ctrl = { @@ -433,14 +434,14 @@ u32 pmem_start; u32 dmem_start; - ptr = (uintptr_t)pcm->buf + 0x40000000; + ptr = (uintptr_t)pcm->buf + SPM_SYSTEM_BASE_OFFSET; pmem_words = pcm->desc.pmem_words; total_words = pcm->desc.total_words; dmem_words = total_words - pmem_words; pmem_start = pcm->desc.pmem_start; dmem_start = pcm->desc.dmem_start; - printk(BIOS_INFO, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n", + printk(BIOS_DEBUG, "%s: ptr = %#lx, pmem/dmem words = %#x/%#x\n", __func__, (long)ptr, pmem_words, dmem_words); /* DMA needs 16-byte aligned source data. */ @@ -449,24 +450,13 @@ assert(pmem_words % 4 == 0); assert(dmem_words % 4 == 0); - /* Tell IM where is PCM code (use slave mode if code existed) */ - if (read32(&mtk_spm->md32pcm_dma0_src) != ptr || - read32(&mtk_spm->md32pcm_dma0_dst) != pmem_start || - read32(&mtk_spm->md32pcm_dma0_wppt) != pmem_words || - read32(&mtk_spm->md32pcm_dma0_wpto) != dmem_start || - read32(&mtk_spm->md32pcm_dma0_count) != total_words || - read32(&mtk_spm->md32pcm_dma0_con) != MD32PCM_DMA0_CON_VAL) { - write32(&mtk_spm->md32pcm_dma0_src, ptr); - write32(&mtk_spm->md32pcm_dma0_dst, pmem_start); - write32(&mtk_spm->md32pcm_dma0_wppt, pmem_words); - write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start); - write32(&mtk_spm->md32pcm_dma0_count, total_words); - write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL); - write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL); - } else { - setbits32(&mtk_spm->pcm_con1, - SPM_REGWR_CFG_KEY | RG_IM_SLAVE_LSB); - } + write32(&mtk_spm->md32pcm_dma0_src, ptr); + write32(&mtk_spm->md32pcm_dma0_dst, pmem_start); + write32(&mtk_spm->md32pcm_dma0_wppt, pmem_words); + write32(&mtk_spm->md32pcm_dma0_wpto, dmem_start); + write32(&mtk_spm->md32pcm_dma0_count, total_words); + write32(&mtk_spm->md32pcm_dma0_con, MD32PCM_DMA0_CON_VAL); + write32(&mtk_spm->md32pcm_dma0_start, MD32PCM_DMA0_START_VAL); setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I185200655f7c9d18a4fc1dd95b6a2a6e4e6966c1 Gerrit-Change-Number: 48450 Gerrit-PatchSet: 1 Gerrit-Owner: Roger Lu <roger.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Roger Lu <roger.lu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/ipmi: add code to set BMC/IPMI enablement from jumper
by Michael Niewöhner (Code Review) 12 Dec '20

12 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48094 ) Change subject: drivers/ipmi: add code to set BMC/IPMI enablement from jumper ...................................................................... Patch Set 18: (1 comment) https://review.coreboot.org/c/coreboot/+/48094/18//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/48094/18//COMMIT_MSG@15 PS18, Line 15: : Test: Boot with jumper set to each enabled and disabled and see if IPMI : gets enabled. Successfully tested on Supermicro X11SSM-F. : I need to test this again -- To view, visit https://review.coreboot.org/c/coreboot/+/48094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icde3232843a7138797a4b106560f170972edeb9c Gerrit-Change-Number: 48094 Gerrit-PatchSet: 18 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Dec 2020 01:03:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit December 2020