coreboot-gerrit December 2020

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Change in coreboot[master]: Doc/mb/lenovo: Explain simpler GM45 flash method first
by Angel Pons (Code Review) 14 Dec '20

14 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48604 ) Change subject: Doc/mb/lenovo: Explain simpler GM45 flash method first ...................................................................... Doc/mb/lenovo: Explain simpler GM45 flash method first Do not mislead newcomers into thinking the GM45 series laptops are hard to flash. Describe the simple coreboot flashing procedure first, then explain how to remove the ME firmware and use a custom flash layout. Also, reword a sentence on the simple flashing procedure for clarity. Change-Id: Ie83ec3d20f00e9d9c869e483e24d601506857f07 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/mainboard/lenovo/montevina_series.md 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/48604/1 diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md index c886a21..b513c97 100644 --- a/Documentation/mainboard/lenovo/montevina_series.md +++ b/Documentation/mainboard/lenovo/montevina_series.md @@ -9,6 +9,15 @@ Note that this does not allow you to determine whether the chip is in a SOIC-8 or a SOIC-16 package. +## Installing with ME firmware + +To install coreboot and keep ME working, you don't need to do anything special +with the flash descriptor. Only flash the `bios` region externally and don't +touch any other regions: +```console +# flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios +``` + ## Installing without ME firmware ```eval_rst @@ -127,15 +136,6 @@ Then build coreboot and flash whole `build/coreboot.rom` to the chip. -## Installing with ME firmware - -To install coreboot and keep ME working, you don't need to do anything special -with the flash descriptor. Just flash only `bios` externally and don't touch any -other regions: -```console -# flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios -``` - ## Flash layout The flash layouts of the OEM firmware are as follows: -- To view, visit https://review.coreboot.org/c/coreboot/+/48604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie83ec3d20f00e9d9c869e483e24d601506857f07 Gerrit-Change-Number: 48604 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Doc/mainboard: Sort Lenovo laptop generation groups
by Angel Pons (Code Review) 14 Dec '20

14 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48603 ) Change subject: Doc/mainboard: Sort Lenovo laptop generation groups ...................................................................... Doc/mainboard: Sort Lenovo laptop generation groups GM45 is older than Arrandale, so swap their order. Change-Id: I5b94d940c0378dd561535257d3352700fd482527 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/mainboard/index.md 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/48603/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 4b46b7c..95efe55 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -89,15 +89,15 @@ - [X2xx common](lenovo/x2xx_series.md) - [vboot](lenovo/vboot.md) -### Arrandale series - -- [T410](lenovo/t410.md) - ### GM45 series - [X200 / T400 / T500 / X301 common](lenovo/montevina_series.md) - [X301](lenovo/x301.md) +### Arrandale series + +- [T410](lenovo/t410.md) + ### Sandy Bridge series - [T420](lenovo/t420.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/48603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b94d940c0378dd561535257d3352700fd482527 Gerrit-Change-Number: 48603 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/glados/var/caroline: Drop zero setting from dt
by Angel Pons (Code Review) 14 Dec '20

14 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48579 ) Change subject: mb/google/glados/var/caroline: Drop zero setting from dt ...................................................................... mb/google/glados/var/caroline: Drop zero setting from dt Unset devicetree options already default to zero. Note that this setting is not referenced anywhere else, and will be removed in a follow-up. Change-Id: I7bcc1c66caa9167c2327e1dc782f69c5de0fac2e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/glados/variants/caroline/overridetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/48579/1 diff --git a/src/mainboard/google/glados/variants/caroline/overridetree.cb b/src/mainboard/google/glados/variants/caroline/overridetree.cb index 967a95a..e213d02 100644 --- a/src/mainboard/google/glados/variants/caroline/overridetree.cb +++ b/src/mainboard/google/glados/variants/caroline/overridetree.cb @@ -8,7 +8,6 @@ register "SlowSlewRateForIa" = "3" # Fast/16 register "SlowSlewRateForGt" = "3" # Fast/16 register "SlowSlewRateForSa" = "0" # Fast/2 - register "FastPkgCRampDisable" = "0" register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port (main) register "usb2_ports[1]" = "USB2_PORT_MAX(OC_SKIP)" # Type-C Port (sub) -- To view, visit https://review.coreboot.org/c/coreboot/+/48579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bcc1c66caa9167c2327e1dc782f69c5de0fac2e Gerrit-Change-Number: 48579 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: WIP: coreboot: Enable ANALOGIX_ANX7625
by yongqiang niu (Code Review) 13 Dec '20

13 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46576 ) Change subject: WIP: coreboot: Enable ANALOGIX_ANX7625 ...................................................................... WIP: coreboot: Enable ANALOGIX_ANX7625 Enable ANALOGIX_ANX7625 to support display in coreboot Signed-off-by: Huijuan Xie <huijuan.xie(a)mediatek.corp-partner.google.com> Change-Id: I837e56ba4e98cc94c33484e79c4d5ff45a62becd --- M src/mainboard/google/asurada/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46576/1 diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig index 7c93815..3a825b6 100644 --- a/src/mainboard/google/asurada/Kconfig +++ b/src/mainboard/google/asurada/Kconfig @@ -27,6 +27,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select DRIVER_ANALOGIX_ANX7625 if BOARD_GOOGLE_ASURADA config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/46576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I837e56ba4e98cc94c33484e79c4d5ff45a62becd Gerrit-Change-Number: 46576 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Furquan Shaikh (Code Review) 13 Dec '20

13 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48583 ) Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… File src/soc/intel/alderlake/chip.c: https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… PS7, Line 202: else if (dev->path.type == DEVICE_PATH_GPIO) : dev->ops = &soc_gpio_ops; Rather than adding this to every SoC, I think this can be handled within soc/intel/common/block/gpio driver. i.e. add something like: static void intel_gpio_enable(struct device *dev) { assert(dev->path.type == DEVICE_PATH_GPIO); dev->ops = &soc_gpio_ops; } struct chip_operations soc_gpio_ctrlr_ops = { CHIP_NAME("Intel GPIO controller") .enable_dev = intel_gpio_enable, } In addition to this, you will need a chip.h in that driver. -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Dec 2020 06:07:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/ehlcrb: Remove unrelated Kconfig settings
by Lean Sheng Tan (Code Review) 13 Dec '20

13 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48544 ) Change subject: mb/intel/ehlcrb: Remove unrelated Kconfig settings ...................................................................... mb/intel/ehlcrb: Remove unrelated Kconfig settings Update Kconfig to remove unrelated configs inheritted from JSL_RVP. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: Ia744b57302f7c8310c42e12cf019b7f6e7b8f9e9 --- M src/mainboard/intel/elkhartlake_crb/Kconfig 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48544/1 diff --git a/src/mainboard/intel/elkhartlake_crb/Kconfig b/src/mainboard/intel/elkhartlake_crb/Kconfig index 7cf727c..e8206ad 100644 --- a/src/mainboard/intel/elkhartlake_crb/Kconfig +++ b/src/mainboard/intel/elkhartlake_crb/Kconfig @@ -3,12 +3,9 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 - select DPTF_USE_EISA_HID - select DRIVERS_I2C_DA7219 select DRIVERS_I2C_HID select DRIVERS_INTEL_DPTF select DRIVERS_I2C_GENERIC - select DRIVERS_I2C_MAX98373 select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_ACPI @@ -16,7 +13,6 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SOC_INTEL_ELKHARTLAKE - select SOC_INTEL_COMMON_BLOCK_DTT config MAINBOARD_DIR string @@ -51,7 +47,4 @@ default 2 if INTEL_LPSS_UART_FOR_CONSOLE default 0 -config TPM_TIS_ACPI_INTERRUPT - int - default 45 # GPE0_DW1_13 (GPP_H13) endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia744b57302f7c8310c42e12cf019b7f6e7b8f9e9 Gerrit-Change-Number: 48544 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Update IRQ routing settings
by Lean Sheng Tan (Code Review) 13 Dec '20

13 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48543 ) Change subject: soc/intel/elkhartlake: Update IRQ routing settings ...................................................................... soc/intel/elkhartlake: Update IRQ routing settings Update IRQ routing settings. Extra reference: - ACPI spec 6.2.13 _PRT Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I53feeab81e82c539fa8e39bf90d3f662f75e6d53 --- M src/soc/intel/elkhartlake/acpi/pci_irqs.asl M src/soc/intel/elkhartlake/include/soc/irq.h 2 files changed, 145 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/48543/1 diff --git a/src/soc/intel/elkhartlake/acpi/pci_irqs.asl b/src/soc/intel/elkhartlake/acpi/pci_irqs.asl index aa494a7..8f511f2 100644 --- a/src/soc/intel/elkhartlake/acpi/pci_irqs.asl +++ b/src/soc/intel/elkhartlake/acpi/pci_irqs.asl @@ -3,99 +3,161 @@ #include <soc/irq.h> Name (PICP, Package () { - Package(){0x001FFFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x001FFFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x001FFFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x001FFFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - - Package(){0x001CFFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x001CFFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x001CFFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x001CFFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x001AFFFF, 0, 0, PCH_IRQ_16 }, - - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - - Package(){0x0017FFFF, 0, 0, PCH_IRQ_16 }, - - Package(){0x0016FFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x0016FFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x0016FFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x0016FFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - - Package(){0x0014FFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x0014FFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x0014FFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x0014FFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x0012FFFF, 1, 0, LPSS_SPI2_IRQ }, + //D31 + Package () { 0x001FFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001FFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001FFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001FFFFF, 3, 0, PCH_IRQ_D }, + //D30 + Package () { 0x001EFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001EFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001EFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001EFFFF, 3, 0, PCH_IRQ_D }, + //D29 + Package () { 0x001DFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001DFFFF, 1, 0, PCH_IRQ34 }, + Package () { 0x001DFFFF, 2, 0, PCH_IRQ35 }, + Package () { 0x001DFFFF, 3, 0, PCH_IRQ36 }, + //D28 + Package () { 0x001CFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001CFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001CFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001CFFFF, 3, 0, PCH_IRQ_D }, + //D27 + Package () { 0x001BFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001BFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001BFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001BFFFF, 3, 0, PCH_IRQ_D }, + //D26 + Package () { 0x001AFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001AFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001AFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001AFFFF, 3, 0, PCH_IRQ_D }, + //D25 + Package () { 0x0019FFFF, 0, 0, PCH_IRQ31 }, + Package () { 0x0019FFFF, 1, 0, PCH_IRQ32 }, + Package () { 0x0019FFFF, 2, 0, PCH_IRQ33 }, + //D24 + Package () { 0x0018FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0018FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0018FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0018FFFF, 3, 0, PCH_IRQ_D }, + //D23 + Package () { 0x0017FFFF, 0, 0, PCH_IRQ_A }, + //D22 + Package () { 0x0016FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0016FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0016FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0016FFFF, 3, 0, PCH_IRQ_D }, + //D21 + Package () { 0x0015FFFF, 0, 0, PCH_IRQ27 }, + Package () { 0x0015FFFF, 1, 0, PCH_IRQ28 }, + Package () { 0x0015FFFF, 2, 0, PCH_IRQ29 }, + Package () { 0x0015FFFF, 3, 0, PCH_IRQ30 }, + //D20 + Package () { 0x0014FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0014FFFF, 1, 0, PCH_IRQ_B }, + //D19 + Package () { 0x0013FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0013FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0013FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0013FFFF, 3, 0, PCH_IRQ_D }, + //D18 + Package () { 0x0012FFFF, 0, 0, PCH_IRQ24 }, + Package () { 0x0012FFFF, 1, 0, PCH_IRQ25 }, + Package () { 0x0012FFFF, 2, 0, PCH_IRQ26 }, + //D17 + Package () { 0x0011FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0011FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0011FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0011FFFF, 3, 0, PCH_IRQ_D }, + //D16 + Package () { 0x0010FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0010FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0010FFFF, 2, 0, PCH_IRQ_C }, /* SA GNA Device */ - Package(){0x0008FFFF, 0, 0, PCH_IRQ_16 }, - /* SA IPU Device */ - Package(){0x0005FFFF, 0, 0, PCH_IRQ_16 }, + Package () { 0x0008FFFF, 0, 0, PCH_IRQ_A }, /* SA Thermal Device */ - Package(){0x0004FFFF, 0, 0, PCH_IRQ_16 }, + Package () { 0x0004FFFF, 0, 0, PCH_IRQ_A }, /* SA IGFX Device */ - Package(){0x0002FFFF, 0, 0, PCH_IRQ_16 }, + Package () { 0x0002FFFF, 0, 0, PCH_IRQ_A }, }) Name (PICN, Package () { + //D31 Package () { 0x001FFFFF, 0, 0, PCH_IRQ11 }, Package () { 0x001FFFFF, 1, 0, PCH_IRQ10 }, Package () { 0x001FFFFF, 2, 0, PCH_IRQ11 }, Package () { 0x001FFFFF, 3, 0, PCH_IRQ11 }, - + //D30 Package () { 0x001EFFFF, 0, 0, PCH_IRQ11 }, Package () { 0x001EFFFF, 1, 0, PCH_IRQ10 }, Package () { 0x001EFFFF, 2, 0, PCH_IRQ11 }, Package () { 0x001EFFFF, 3, 0, PCH_IRQ11 }, - + //D29 + Package () { 0x001DFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001DFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001DFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001DFFFF, 3, 0, PCH_IRQ11 }, + //D28 Package () { 0x001CFFFF, 0, 0, PCH_IRQ11 }, Package () { 0x001CFFFF, 1, 0, PCH_IRQ10 }, Package () { 0x001CFFFF, 2, 0, PCH_IRQ11 }, Package () { 0x001CFFFF, 3, 0, PCH_IRQ11 }, - + //D27 + Package () { 0x001BFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001BFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001BFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001BFFFF, 3, 0, PCH_IRQ11 }, + //D26 Package () { 0x001AFFFF, 0, 0, PCH_IRQ11 }, - + Package () { 0x001AFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001AFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001AFFFF, 3, 0, PCH_IRQ11 }, + //D25 Package () { 0x0019FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0019FFFF, 1, 0, PCH_IRQ10 }, Package () { 0x0019FFFF, 2, 0, PCH_IRQ11 }, - + //D24 + Package () { 0x0018FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0018FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0018FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0018FFFF, 3, 0, PCH_IRQ11 }, + //D23 Package () { 0x0017FFFF, 0, 0, PCH_IRQ11 }, - + //D22 Package () { 0x0016FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0016FFFF, 1, 0, PCH_IRQ10 }, Package () { 0x0016FFFF, 2, 0, PCH_IRQ11 }, Package () { 0x0016FFFF, 3, 0, PCH_IRQ11 }, - + //D21 Package () { 0x0015FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0015FFFF, 1, 0, PCH_IRQ10 }, Package () { 0x0015FFFF, 2, 0, PCH_IRQ11 }, Package () { 0x0015FFFF, 3, 0, PCH_IRQ11 }, - + //D20 Package () { 0x0014FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0014FFFF, 1, 0, PCH_IRQ10 }, - Package () { 0x0014FFFF, 2, 0, PCH_IRQ11 }, - Package () { 0x0014FFFF, 3, 0, PCH_IRQ11 }, - + //D19 + Package () { 0x0013FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0013FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0013FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0013FFFF, 3, 0, PCH_IRQ11 }, + //D18 + Package () { 0x0012FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0012FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0012FFFF, 2, 0, PCH_IRQ11 }, + //D17 + Package () { 0x0011FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0011FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0011FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0011FFFF, 3, 0, PCH_IRQ11 }, + //D16 + Package () { 0x0010FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0010FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0010FFFF, 2, 0, PCH_IRQ11 }, /* SA GNA Device */ Package () { 0x0008FFFF, 0, 0, PCH_IRQ11 }, - /* SA IPU Device */ - Package () { 0x0005FFFF, 0, 0, PCH_IRQ11 }, /* SA Thermal Device */ Package () { 0x0004FFFF, 0, 0, PCH_IRQ11 }, /* SA IGFX Device */ diff --git a/src/soc/intel/elkhartlake/include/soc/irq.h b/src/soc/intel/elkhartlake/include/soc/irq.h index ac45424..432b7ae 100644 --- a/src/soc/intel/elkhartlake/include/soc/irq.h +++ b/src/soc/intel/elkhartlake/include/soc/irq.h @@ -8,29 +8,33 @@ #define PCH_IRQ10 10 #define PCH_IRQ11 11 - -/* LPSS Device IRQs */ -#define LPSS_I2C0_IRQ 16 -#define LPSS_I2C1_IRQ 17 -#define LPSS_I2C2_IRQ 18 -#define LPSS_I2C3_IRQ 19 -#define LPSS_I2C4_IRQ 32 -#define LPSS_I2C5_IRQ 33 -#define LPSS_SPI0_IRQ 22 -#define LPSS_SPI1_IRQ 23 -#define LPSS_SPI2_IRQ 24 -#define LPSS_UART0_IRQ 20 -#define LPSS_UART1_IRQ 21 -#define LPSS_UART2_IRQ 34 +#define PCH_IRQ24 24 +#define PCH_IRQ25 25 +#define PCH_IRQ26 26 +#define PCH_IRQ27 27 +#define PCH_IRQ28 28 +#define PCH_IRQ29 29 +#define PCH_IRQ30 30 +#define PCH_IRQ31 31 +#define PCH_IRQ32 32 +#define PCH_IRQ33 33 +#define PCH_IRQ34 34 +#define PCH_IRQ35 35 +#define PCH_IRQ36 36 /* PCI shared IRQs */ -#define PCH_IRQ_16 16 -#define PCH_IRQ_17 17 -#define PCH_IRQ_18 18 -#define PCH_IRQ_19 19 -#define PCH_IRQ_20 20 -#define PCH_IRQ_21 21 -#define PCH_IRQ_22 22 -#define PCH_IRQ_23 23 +#define PCH_IRQ_A 16 +#define PCH_IRQ_B 17 +#define PCH_IRQ_C 18 +#define PCH_IRQ_D 19 +#define PCH_IRQ_E 20 +#define PCH_IRQ_F 21 +#define PCH_IRQ_G 22 +#define PCH_IRQ_H 23 + +/* LPSS Device IRQs */ +#define LPSS_UART0_IRQ 16 +#define LPSS_UART1_IRQ 17 +#define LPSS_UART2_IRQ 33 #endif /* _EHL_IRQ_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53feeab81e82c539fa8e39bf90d3f662f75e6d53 Gerrit-Change-Number: 48543 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/intel/elkhartlake: Update USB & PCIe devices in ASL files
by Lean Sheng Tan (Code Review) 13 Dec '20

13 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48542 ) Change subject: soc/intel/elkhartlake: Update USB & PCIe devices in ASL files ...................................................................... soc/intel/elkhartlake: Update USB & PCIe devices in ASL files Update USB & PCIe devices in ASL files as per EHL EDS. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I8b567127fbdd880ccc0a5e0ca334162f9f4f5164 --- M src/soc/intel/elkhartlake/acpi/pcie.asl M src/soc/intel/elkhartlake/acpi/xhci.asl 2 files changed, 9 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/48542/1 diff --git a/src/soc/intel/elkhartlake/acpi/pcie.asl b/src/soc/intel/elkhartlake/acpi/pcie.asl index a19feb7..464f8d6 100644 --- a/src/soc/intel/elkhartlake/acpi/pcie.asl +++ b/src/soc/intel/elkhartlake/acpi/pcie.asl @@ -214,88 +214,3 @@ Return (IRQM (RPPN)) } } - -Device (RP08) -{ - Name (_ADR, 0x001C0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP09) -{ - Name (_ADR, 0x001D0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP10) -{ - Name (_ADR, 0x001D0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP11) -{ - Name (_ADR, 0x001D0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP12) -{ - Name (_ADR, 0x001D0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} diff --git a/src/soc/intel/elkhartlake/acpi/xhci.asl b/src/soc/intel/elkhartlake/acpi/xhci.asl index 445c7db..eae21da 100644 --- a/src/soc/intel/elkhartlake/acpi/xhci.asl +++ b/src/soc/intel/elkhartlake/acpi/xhci.asl @@ -38,13 +38,15 @@ Device (HS06) { Name (_ADR, 6) } Device (HS07) { Name (_ADR, 7) } Device (HS08) { Name (_ADR, 8) } - + Device (HS09) { Name (_ADR, 9) } + Device (HS10) { Name (_ADR, 10) } + Device (HS11) { Name (_ADR, 11) } + Device (HS12) { Name (_ADR, 12) } + /* USB3 */ - Device (SS01) { Name (_ADR, 9) } - Device (SS02) { Name (_ADR, 10) } - Device (SS03) { Name (_ADR, 11) } - Device (SS04) { Name (_ADR, 12) } - Device (SS05) { Name (_ADR, 13) } - Device (SS06) { Name (_ADR, 14) } + Device (SS01) { Name (_ADR, 13) } + Device (SS02) { Name (_ADR, 14) } + Device (SS03) { Name (_ADR, 15) } + Device (SS04) { Name (_ADR, 16) } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b567127fbdd880ccc0a5e0ca334162f9f4f5164 Gerrit-Change-Number: 48542 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/elkhartlake: Update USB_PORT_MID pin settings
by Lean Sheng Tan (Code Review) 13 Dec '20

13 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48541 ) Change subject: soc/intel/elkhartlake: Update USB_PORT_MID pin settings ...................................................................... soc/intel/elkhartlake: Update USB_PORT_MID pin settings Update Pre-emphasis, Transmitter Emphasis & Preemphasis Bias values for USB_PORT_MID. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I43eeb0fc410197a559df97b340135fac65c00aa5 --- M src/soc/intel/elkhartlake/include/soc/usb.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/48541/1 diff --git a/src/soc/intel/elkhartlake/include/soc/usb.h b/src/soc/intel/elkhartlake/include/soc/usb.h index 247b0ba..3cef823 100644 --- a/src/soc/intel/elkhartlake/include/soc/usb.h +++ b/src/soc/intel/elkhartlake/include/soc/usb.h @@ -79,9 +79,9 @@ .enable = 1, \ .ocpin = (pin), \ .tx_bias = USB2_BIAS_0MV, \ - .tx_emp_enable = USB2_PRE_EMP_ON, \ - .pre_emp_bias = USB2_BIAS_56P3MV, \ - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_45MV, \ + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ } /* Length = 3"-5.99" */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43eeb0fc410197a559df97b340135fac65c00aa5 Gerrit-Change-Number: 48541 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/elkhartlake: Update SerialIO devices details
by Lean Sheng Tan (Code Review) 13 Dec '20

13 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48540 ) Change subject: soc/intel/elkhartlake: Update SerialIO devices details ...................................................................... soc/intel/elkhartlake: Update SerialIO devices details Add I2C #6 & #7, and remove GSPI #3 as per EHL EDS. Also update Device Function number for GSPI #2 in asl file. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: If166fefe567a857ca29527d0367197139efbf6c7 --- M src/soc/intel/elkhartlake/acpi/serialio.asl M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/elkhartlake/i2c.c M src/soc/intel/elkhartlake/include/soc/serialio.h 4 files changed, 25 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48540/1 diff --git a/src/soc/intel/elkhartlake/acpi/serialio.asl b/src/soc/intel/elkhartlake/acpi/serialio.asl index f7bf452..ac628d2 100644 --- a/src/soc/intel/elkhartlake/acpi/serialio.asl +++ b/src/soc/intel/elkhartlake/acpi/serialio.asl @@ -38,6 +38,18 @@ Name (_DDN, "Serial IO I2C Controller 5") } +Device (I2C6) +{ + Name (_ADR, 0x00100000) + Name (_DDN, "Serial IO I2C Controller 6") +} + +Device (I2C7) +{ + Name (_ADR, 0x00100001) + Name (_DDN, "Serial IO I2C Controller 7") +} + Device (SPI0) { Name (_ADR, 0x001e0002) @@ -52,16 +64,10 @@ Device (SPI2) { - Name (_ADR, 0x00120006) + Name (_ADR, 0x00120000) Name (_DDN, "Serial IO SPI Controller 2") } -Device (SPI3) -{ - Name (_ADR, 0x00130000) - Name (_DDN, "Serial IO SPI Controller 3") -} - Device (UAR0) { Name (_ADR, 0x001e0000) diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 83a3699..3aed1ac 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -34,6 +34,8 @@ PCH_DEVFN_I2C3, PCH_DEVFN_I2C4, PCH_DEVFN_I2C5, + PCH_DEVFN_I2C6, + PCH_DEVFN_I2C7, PCH_DEVFN_GSPI0, PCH_DEVFN_GSPI1, PCH_DEVFN_GSPI2, diff --git a/src/soc/intel/elkhartlake/i2c.c b/src/soc/intel/elkhartlake/i2c.c index c13a1a6..78ee37b 100644 --- a/src/soc/intel/elkhartlake/i2c.c +++ b/src/soc/intel/elkhartlake/i2c.c @@ -19,6 +19,10 @@ return 4; case PCH_DEVFN_I2C5: return 5; + case PCH_DEVFN_I2C6: + return 6; + case PCH_DEVFN_I2C7: + return 7; } return -1; } @@ -38,6 +42,10 @@ return PCH_DEVFN_I2C4; case 5: return PCH_DEVFN_I2C5; + case 6: + return PCH_DEVFN_I2C6; + case 7: + return PCH_DEVFN_I2C7; } return -1; } diff --git a/src/soc/intel/elkhartlake/include/soc/serialio.h b/src/soc/intel/elkhartlake/include/soc/serialio.h index e42af5f..bee96f0 100644 --- a/src/soc/intel/elkhartlake/include/soc/serialio.h +++ b/src/soc/intel/elkhartlake/include/soc/serialio.h @@ -18,13 +18,14 @@ PchSerialIoIndexI2C3, PchSerialIoIndexI2C4, PchSerialIoIndexI2C5, + PchSerialIoIndexI2C6, + PchSerialIoIndexI2C7, }; enum { PchSerialIoIndexGSPI0, PchSerialIoIndexGSPI1, PchSerialIoIndexGSPI2, - PchSerialIoIndexGSPI3, }; enum { -- To view, visit https://review.coreboot.org/c/coreboot/+/48540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If166fefe567a857ca29527d0367197139efbf6c7 Gerrit-Change-Number: 48540 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

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