coreboot-gerrit December 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: WIP: coreboot: Enable ANALOGIX_ANX7625
by yongqiang niu (Code Review) 14 Dec '20

14 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46576 ) Change subject: WIP: coreboot: Enable ANALOGIX_ANX7625 ...................................................................... WIP: coreboot: Enable ANALOGIX_ANX7625 Enable ANALOGIX_ANX7625 to support display in coreboot Signed-off-by: Huijuan Xie <huijuan.xie(a)mediatek.corp-partner.google.com> Change-Id: I837e56ba4e98cc94c33484e79c4d5ff45a62becd --- M src/mainboard/google/asurada/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46576/1 diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig index 7c93815..3a825b6 100644 --- a/src/mainboard/google/asurada/Kconfig +++ b/src/mainboard/google/asurada/Kconfig @@ -27,6 +27,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select DRIVER_ANALOGIX_ANX7625 if BOARD_GOOGLE_ASURADA config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/46576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I837e56ba4e98cc94c33484e79c4d5ff45a62becd Gerrit-Change-Number: 46576 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Furquan Shaikh (Code Review) 14 Dec '20

14 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48583 ) Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… File src/soc/intel/alderlake/chip.c: https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… PS7, Line 202: else if (dev->path.type == DEVICE_PATH_GPIO) : dev->ops = &soc_gpio_ops; Rather than adding this to every SoC, I think this can be handled within soc/intel/common/block/gpio driver. i.e. add something like: static void intel_gpio_enable(struct device *dev) { assert(dev->path.type == DEVICE_PATH_GPIO); dev->ops = &soc_gpio_ops; } struct chip_operations soc_gpio_ctrlr_ops = { CHIP_NAME("Intel GPIO controller") .enable_dev = intel_gpio_enable, } In addition to this, you will need a chip.h in that driver. -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Dec 2020 06:07:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/ehlcrb: Remove unrelated Kconfig settings
by Lean Sheng Tan (Code Review) 14 Dec '20

14 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48544 ) Change subject: mb/intel/ehlcrb: Remove unrelated Kconfig settings ...................................................................... mb/intel/ehlcrb: Remove unrelated Kconfig settings Update Kconfig to remove unrelated configs inheritted from JSL_RVP. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: Ia744b57302f7c8310c42e12cf019b7f6e7b8f9e9 --- M src/mainboard/intel/elkhartlake_crb/Kconfig 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48544/1 diff --git a/src/mainboard/intel/elkhartlake_crb/Kconfig b/src/mainboard/intel/elkhartlake_crb/Kconfig index 7cf727c..e8206ad 100644 --- a/src/mainboard/intel/elkhartlake_crb/Kconfig +++ b/src/mainboard/intel/elkhartlake_crb/Kconfig @@ -3,12 +3,9 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 - select DPTF_USE_EISA_HID - select DRIVERS_I2C_DA7219 select DRIVERS_I2C_HID select DRIVERS_INTEL_DPTF select DRIVERS_I2C_GENERIC - select DRIVERS_I2C_MAX98373 select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select EC_ACPI @@ -16,7 +13,6 @@ select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select SOC_INTEL_ELKHARTLAKE - select SOC_INTEL_COMMON_BLOCK_DTT config MAINBOARD_DIR string @@ -51,7 +47,4 @@ default 2 if INTEL_LPSS_UART_FOR_CONSOLE default 0 -config TPM_TIS_ACPI_INTERRUPT - int - default 45 # GPE0_DW1_13 (GPP_H13) endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia744b57302f7c8310c42e12cf019b7f6e7b8f9e9 Gerrit-Change-Number: 48544 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/elkhartlake: Update IRQ routing settings
by Lean Sheng Tan (Code Review) 14 Dec '20

14 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48543 ) Change subject: soc/intel/elkhartlake: Update IRQ routing settings ...................................................................... soc/intel/elkhartlake: Update IRQ routing settings Update IRQ routing settings. Extra reference: - ACPI spec 6.2.13 _PRT Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I53feeab81e82c539fa8e39bf90d3f662f75e6d53 --- M src/soc/intel/elkhartlake/acpi/pci_irqs.asl M src/soc/intel/elkhartlake/include/soc/irq.h 2 files changed, 145 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/48543/1 diff --git a/src/soc/intel/elkhartlake/acpi/pci_irqs.asl b/src/soc/intel/elkhartlake/acpi/pci_irqs.asl index aa494a7..8f511f2 100644 --- a/src/soc/intel/elkhartlake/acpi/pci_irqs.asl +++ b/src/soc/intel/elkhartlake/acpi/pci_irqs.asl @@ -3,99 +3,161 @@ #include <soc/irq.h> Name (PICP, Package () { - Package(){0x001FFFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x001FFFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x001FFFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x001FFFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - - Package(){0x001CFFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x001CFFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x001CFFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x001CFFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x001AFFFF, 0, 0, PCH_IRQ_16 }, - - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - - Package(){0x0017FFFF, 0, 0, PCH_IRQ_16 }, - - Package(){0x0016FFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x0016FFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x0016FFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x0016FFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - - Package(){0x0014FFFF, 0, 0, PCH_IRQ_16 }, - Package(){0x0014FFFF, 1, 0, PCH_IRQ_17 }, - Package(){0x0014FFFF, 2, 0, PCH_IRQ_18 }, - Package(){0x0014FFFF, 3, 0, PCH_IRQ_19 }, - - Package(){0x0012FFFF, 1, 0, LPSS_SPI2_IRQ }, + //D31 + Package () { 0x001FFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001FFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001FFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001FFFFF, 3, 0, PCH_IRQ_D }, + //D30 + Package () { 0x001EFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001EFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001EFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001EFFFF, 3, 0, PCH_IRQ_D }, + //D29 + Package () { 0x001DFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001DFFFF, 1, 0, PCH_IRQ34 }, + Package () { 0x001DFFFF, 2, 0, PCH_IRQ35 }, + Package () { 0x001DFFFF, 3, 0, PCH_IRQ36 }, + //D28 + Package () { 0x001CFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001CFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001CFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001CFFFF, 3, 0, PCH_IRQ_D }, + //D27 + Package () { 0x001BFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001BFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001BFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001BFFFF, 3, 0, PCH_IRQ_D }, + //D26 + Package () { 0x001AFFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x001AFFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x001AFFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x001AFFFF, 3, 0, PCH_IRQ_D }, + //D25 + Package () { 0x0019FFFF, 0, 0, PCH_IRQ31 }, + Package () { 0x0019FFFF, 1, 0, PCH_IRQ32 }, + Package () { 0x0019FFFF, 2, 0, PCH_IRQ33 }, + //D24 + Package () { 0x0018FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0018FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0018FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0018FFFF, 3, 0, PCH_IRQ_D }, + //D23 + Package () { 0x0017FFFF, 0, 0, PCH_IRQ_A }, + //D22 + Package () { 0x0016FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0016FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0016FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0016FFFF, 3, 0, PCH_IRQ_D }, + //D21 + Package () { 0x0015FFFF, 0, 0, PCH_IRQ27 }, + Package () { 0x0015FFFF, 1, 0, PCH_IRQ28 }, + Package () { 0x0015FFFF, 2, 0, PCH_IRQ29 }, + Package () { 0x0015FFFF, 3, 0, PCH_IRQ30 }, + //D20 + Package () { 0x0014FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0014FFFF, 1, 0, PCH_IRQ_B }, + //D19 + Package () { 0x0013FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0013FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0013FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0013FFFF, 3, 0, PCH_IRQ_D }, + //D18 + Package () { 0x0012FFFF, 0, 0, PCH_IRQ24 }, + Package () { 0x0012FFFF, 1, 0, PCH_IRQ25 }, + Package () { 0x0012FFFF, 2, 0, PCH_IRQ26 }, + //D17 + Package () { 0x0011FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0011FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0011FFFF, 2, 0, PCH_IRQ_C }, + Package () { 0x0011FFFF, 3, 0, PCH_IRQ_D }, + //D16 + Package () { 0x0010FFFF, 0, 0, PCH_IRQ_A }, + Package () { 0x0010FFFF, 1, 0, PCH_IRQ_B }, + Package () { 0x0010FFFF, 2, 0, PCH_IRQ_C }, /* SA GNA Device */ - Package(){0x0008FFFF, 0, 0, PCH_IRQ_16 }, - /* SA IPU Device */ - Package(){0x0005FFFF, 0, 0, PCH_IRQ_16 }, + Package () { 0x0008FFFF, 0, 0, PCH_IRQ_A }, /* SA Thermal Device */ - Package(){0x0004FFFF, 0, 0, PCH_IRQ_16 }, + Package () { 0x0004FFFF, 0, 0, PCH_IRQ_A }, /* SA IGFX Device */ - Package(){0x0002FFFF, 0, 0, PCH_IRQ_16 }, + Package () { 0x0002FFFF, 0, 0, PCH_IRQ_A }, }) Name (PICN, Package () { + //D31 Package () { 0x001FFFFF, 0, 0, PCH_IRQ11 }, Package () { 0x001FFFFF, 1, 0, PCH_IRQ10 }, Package () { 0x001FFFFF, 2, 0, PCH_IRQ11 }, Package () { 0x001FFFFF, 3, 0, PCH_IRQ11 }, - + //D30 Package () { 0x001EFFFF, 0, 0, PCH_IRQ11 }, Package () { 0x001EFFFF, 1, 0, PCH_IRQ10 }, Package () { 0x001EFFFF, 2, 0, PCH_IRQ11 }, Package () { 0x001EFFFF, 3, 0, PCH_IRQ11 }, - + //D29 + Package () { 0x001DFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001DFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001DFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001DFFFF, 3, 0, PCH_IRQ11 }, + //D28 Package () { 0x001CFFFF, 0, 0, PCH_IRQ11 }, Package () { 0x001CFFFF, 1, 0, PCH_IRQ10 }, Package () { 0x001CFFFF, 2, 0, PCH_IRQ11 }, Package () { 0x001CFFFF, 3, 0, PCH_IRQ11 }, - + //D27 + Package () { 0x001BFFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x001BFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001BFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001BFFFF, 3, 0, PCH_IRQ11 }, + //D26 Package () { 0x001AFFFF, 0, 0, PCH_IRQ11 }, - + Package () { 0x001AFFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x001AFFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x001AFFFF, 3, 0, PCH_IRQ11 }, + //D25 Package () { 0x0019FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0019FFFF, 1, 0, PCH_IRQ10 }, Package () { 0x0019FFFF, 2, 0, PCH_IRQ11 }, - + //D24 + Package () { 0x0018FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0018FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0018FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0018FFFF, 3, 0, PCH_IRQ11 }, + //D23 Package () { 0x0017FFFF, 0, 0, PCH_IRQ11 }, - + //D22 Package () { 0x0016FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0016FFFF, 1, 0, PCH_IRQ10 }, Package () { 0x0016FFFF, 2, 0, PCH_IRQ11 }, Package () { 0x0016FFFF, 3, 0, PCH_IRQ11 }, - + //D21 Package () { 0x0015FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0015FFFF, 1, 0, PCH_IRQ10 }, Package () { 0x0015FFFF, 2, 0, PCH_IRQ11 }, Package () { 0x0015FFFF, 3, 0, PCH_IRQ11 }, - + //D20 Package () { 0x0014FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0014FFFF, 1, 0, PCH_IRQ10 }, - Package () { 0x0014FFFF, 2, 0, PCH_IRQ11 }, - Package () { 0x0014FFFF, 3, 0, PCH_IRQ11 }, - + //D19 + Package () { 0x0013FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0013FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0013FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0013FFFF, 3, 0, PCH_IRQ11 }, + //D18 + Package () { 0x0012FFFF, 0, 0, PCH_IRQ11 }, Package () { 0x0012FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0012FFFF, 2, 0, PCH_IRQ11 }, + //D17 + Package () { 0x0011FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0011FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0011FFFF, 2, 0, PCH_IRQ11 }, + Package () { 0x0011FFFF, 3, 0, PCH_IRQ11 }, + //D16 + Package () { 0x0010FFFF, 0, 0, PCH_IRQ11 }, + Package () { 0x0010FFFF, 1, 0, PCH_IRQ10 }, + Package () { 0x0010FFFF, 2, 0, PCH_IRQ11 }, /* SA GNA Device */ Package () { 0x0008FFFF, 0, 0, PCH_IRQ11 }, - /* SA IPU Device */ - Package () { 0x0005FFFF, 0, 0, PCH_IRQ11 }, /* SA Thermal Device */ Package () { 0x0004FFFF, 0, 0, PCH_IRQ11 }, /* SA IGFX Device */ diff --git a/src/soc/intel/elkhartlake/include/soc/irq.h b/src/soc/intel/elkhartlake/include/soc/irq.h index ac45424..432b7ae 100644 --- a/src/soc/intel/elkhartlake/include/soc/irq.h +++ b/src/soc/intel/elkhartlake/include/soc/irq.h @@ -8,29 +8,33 @@ #define PCH_IRQ10 10 #define PCH_IRQ11 11 - -/* LPSS Device IRQs */ -#define LPSS_I2C0_IRQ 16 -#define LPSS_I2C1_IRQ 17 -#define LPSS_I2C2_IRQ 18 -#define LPSS_I2C3_IRQ 19 -#define LPSS_I2C4_IRQ 32 -#define LPSS_I2C5_IRQ 33 -#define LPSS_SPI0_IRQ 22 -#define LPSS_SPI1_IRQ 23 -#define LPSS_SPI2_IRQ 24 -#define LPSS_UART0_IRQ 20 -#define LPSS_UART1_IRQ 21 -#define LPSS_UART2_IRQ 34 +#define PCH_IRQ24 24 +#define PCH_IRQ25 25 +#define PCH_IRQ26 26 +#define PCH_IRQ27 27 +#define PCH_IRQ28 28 +#define PCH_IRQ29 29 +#define PCH_IRQ30 30 +#define PCH_IRQ31 31 +#define PCH_IRQ32 32 +#define PCH_IRQ33 33 +#define PCH_IRQ34 34 +#define PCH_IRQ35 35 +#define PCH_IRQ36 36 /* PCI shared IRQs */ -#define PCH_IRQ_16 16 -#define PCH_IRQ_17 17 -#define PCH_IRQ_18 18 -#define PCH_IRQ_19 19 -#define PCH_IRQ_20 20 -#define PCH_IRQ_21 21 -#define PCH_IRQ_22 22 -#define PCH_IRQ_23 23 +#define PCH_IRQ_A 16 +#define PCH_IRQ_B 17 +#define PCH_IRQ_C 18 +#define PCH_IRQ_D 19 +#define PCH_IRQ_E 20 +#define PCH_IRQ_F 21 +#define PCH_IRQ_G 22 +#define PCH_IRQ_H 23 + +/* LPSS Device IRQs */ +#define LPSS_UART0_IRQ 16 +#define LPSS_UART1_IRQ 17 +#define LPSS_UART2_IRQ 33 #endif /* _EHL_IRQ_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48543 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53feeab81e82c539fa8e39bf90d3f662f75e6d53 Gerrit-Change-Number: 48543 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/intel/elkhartlake: Update USB & PCIe devices in ASL files
by Lean Sheng Tan (Code Review) 14 Dec '20

14 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48542 ) Change subject: soc/intel/elkhartlake: Update USB & PCIe devices in ASL files ...................................................................... soc/intel/elkhartlake: Update USB & PCIe devices in ASL files Update USB & PCIe devices in ASL files as per EHL EDS. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I8b567127fbdd880ccc0a5e0ca334162f9f4f5164 --- M src/soc/intel/elkhartlake/acpi/pcie.asl M src/soc/intel/elkhartlake/acpi/xhci.asl 2 files changed, 9 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/48542/1 diff --git a/src/soc/intel/elkhartlake/acpi/pcie.asl b/src/soc/intel/elkhartlake/acpi/pcie.asl index a19feb7..464f8d6 100644 --- a/src/soc/intel/elkhartlake/acpi/pcie.asl +++ b/src/soc/intel/elkhartlake/acpi/pcie.asl @@ -214,88 +214,3 @@ Return (IRQM (RPPN)) } } - -Device (RP08) -{ - Name (_ADR, 0x001C0007) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP09) -{ - Name (_ADR, 0x001D0000) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP10) -{ - Name (_ADR, 0x001D0001) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP11) -{ - Name (_ADR, 0x001D0002) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP12) -{ - Name (_ADR, 0x001D0003) - - OperationRegion (RPCS, PCI_Config, 0x4c, 4) - Field (RPCS, AnyAcc, NoLock, Preserve) - { - , 24, - RPPN, 8, /* Root Port Number */ - } - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} diff --git a/src/soc/intel/elkhartlake/acpi/xhci.asl b/src/soc/intel/elkhartlake/acpi/xhci.asl index 445c7db..eae21da 100644 --- a/src/soc/intel/elkhartlake/acpi/xhci.asl +++ b/src/soc/intel/elkhartlake/acpi/xhci.asl @@ -38,13 +38,15 @@ Device (HS06) { Name (_ADR, 6) } Device (HS07) { Name (_ADR, 7) } Device (HS08) { Name (_ADR, 8) } - + Device (HS09) { Name (_ADR, 9) } + Device (HS10) { Name (_ADR, 10) } + Device (HS11) { Name (_ADR, 11) } + Device (HS12) { Name (_ADR, 12) } + /* USB3 */ - Device (SS01) { Name (_ADR, 9) } - Device (SS02) { Name (_ADR, 10) } - Device (SS03) { Name (_ADR, 11) } - Device (SS04) { Name (_ADR, 12) } - Device (SS05) { Name (_ADR, 13) } - Device (SS06) { Name (_ADR, 14) } + Device (SS01) { Name (_ADR, 13) } + Device (SS02) { Name (_ADR, 14) } + Device (SS03) { Name (_ADR, 15) } + Device (SS04) { Name (_ADR, 16) } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48542 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b567127fbdd880ccc0a5e0ca334162f9f4f5164 Gerrit-Change-Number: 48542 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/elkhartlake: Update USB_PORT_MID pin settings
by Lean Sheng Tan (Code Review) 14 Dec '20

14 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48541 ) Change subject: soc/intel/elkhartlake: Update USB_PORT_MID pin settings ...................................................................... soc/intel/elkhartlake: Update USB_PORT_MID pin settings Update Pre-emphasis, Transmitter Emphasis & Preemphasis Bias values for USB_PORT_MID. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I43eeb0fc410197a559df97b340135fac65c00aa5 --- M src/soc/intel/elkhartlake/include/soc/usb.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/48541/1 diff --git a/src/soc/intel/elkhartlake/include/soc/usb.h b/src/soc/intel/elkhartlake/include/soc/usb.h index 247b0ba..3cef823 100644 --- a/src/soc/intel/elkhartlake/include/soc/usb.h +++ b/src/soc/intel/elkhartlake/include/soc/usb.h @@ -79,9 +79,9 @@ .enable = 1, \ .ocpin = (pin), \ .tx_bias = USB2_BIAS_0MV, \ - .tx_emp_enable = USB2_PRE_EMP_ON, \ - .pre_emp_bias = USB2_BIAS_56P3MV, \ - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ + .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ + .pre_emp_bias = USB2_BIAS_45MV, \ + .pre_emp_bit = USB2_FULL_BIT_PRE_EMP, \ } /* Length = 3"-5.99" */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43eeb0fc410197a559df97b340135fac65c00aa5 Gerrit-Change-Number: 48541 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/elkhartlake: Update SerialIO devices details
by Lean Sheng Tan (Code Review) 14 Dec '20

14 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48540 ) Change subject: soc/intel/elkhartlake: Update SerialIO devices details ...................................................................... soc/intel/elkhartlake: Update SerialIO devices details Add I2C #6 & #7, and remove GSPI #3 as per EHL EDS. Also update Device Function number for GSPI #2 in asl file. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: If166fefe567a857ca29527d0367197139efbf6c7 --- M src/soc/intel/elkhartlake/acpi/serialio.asl M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/elkhartlake/i2c.c M src/soc/intel/elkhartlake/include/soc/serialio.h 4 files changed, 25 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48540/1 diff --git a/src/soc/intel/elkhartlake/acpi/serialio.asl b/src/soc/intel/elkhartlake/acpi/serialio.asl index f7bf452..ac628d2 100644 --- a/src/soc/intel/elkhartlake/acpi/serialio.asl +++ b/src/soc/intel/elkhartlake/acpi/serialio.asl @@ -38,6 +38,18 @@ Name (_DDN, "Serial IO I2C Controller 5") } +Device (I2C6) +{ + Name (_ADR, 0x00100000) + Name (_DDN, "Serial IO I2C Controller 6") +} + +Device (I2C7) +{ + Name (_ADR, 0x00100001) + Name (_DDN, "Serial IO I2C Controller 7") +} + Device (SPI0) { Name (_ADR, 0x001e0002) @@ -52,16 +64,10 @@ Device (SPI2) { - Name (_ADR, 0x00120006) + Name (_ADR, 0x00120000) Name (_DDN, "Serial IO SPI Controller 2") } -Device (SPI3) -{ - Name (_ADR, 0x00130000) - Name (_DDN, "Serial IO SPI Controller 3") -} - Device (UAR0) { Name (_ADR, 0x001e0000) diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 83a3699..3aed1ac 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -34,6 +34,8 @@ PCH_DEVFN_I2C3, PCH_DEVFN_I2C4, PCH_DEVFN_I2C5, + PCH_DEVFN_I2C6, + PCH_DEVFN_I2C7, PCH_DEVFN_GSPI0, PCH_DEVFN_GSPI1, PCH_DEVFN_GSPI2, diff --git a/src/soc/intel/elkhartlake/i2c.c b/src/soc/intel/elkhartlake/i2c.c index c13a1a6..78ee37b 100644 --- a/src/soc/intel/elkhartlake/i2c.c +++ b/src/soc/intel/elkhartlake/i2c.c @@ -19,6 +19,10 @@ return 4; case PCH_DEVFN_I2C5: return 5; + case PCH_DEVFN_I2C6: + return 6; + case PCH_DEVFN_I2C7: + return 7; } return -1; } @@ -38,6 +42,10 @@ return PCH_DEVFN_I2C4; case 5: return PCH_DEVFN_I2C5; + case 6: + return PCH_DEVFN_I2C6; + case 7: + return PCH_DEVFN_I2C7; } return -1; } diff --git a/src/soc/intel/elkhartlake/include/soc/serialio.h b/src/soc/intel/elkhartlake/include/soc/serialio.h index e42af5f..bee96f0 100644 --- a/src/soc/intel/elkhartlake/include/soc/serialio.h +++ b/src/soc/intel/elkhartlake/include/soc/serialio.h @@ -18,13 +18,14 @@ PchSerialIoIndexI2C3, PchSerialIoIndexI2C4, PchSerialIoIndexI2C5, + PchSerialIoIndexI2C6, + PchSerialIoIndexI2C7, }; enum { PchSerialIoIndexGSPI0, PchSerialIoIndexGSPI1, PchSerialIoIndexGSPI2, - PchSerialIoIndexGSPI3, }; enum { -- To view, visit https://review.coreboot.org/c/coreboot/+/48540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If166fefe567a857ca29527d0367197139efbf6c7 Gerrit-Change-Number: 48540 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/elkhartlake: Update HECI Control Status Register settings
by Lean Sheng Tan (Code Review) 14 Dec '20

14 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48539 ) Change subject: soc/intel/elkhartlake: Update HECI Control Status Register settings ...................................................................... soc/intel/elkhartlake: Update HECI Control Status Register settings For EHL, SpiProtectionMode is added to HFSTS register #1. The original Menufacturing Mode is detected via FpfSocConfigLock instead. If FpfSocConfigLock=1, means it is in Menufacturing Mode, and it is in EOM (End Of Manufacturing) when FpfSocConfigLock=0. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I9d1d004a6b5b276e33be80f02cd1197b88d379ae --- M src/soc/intel/elkhartlake/include/soc/me.h M src/soc/intel/elkhartlake/me.c 2 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/48539/1 diff --git a/src/soc/intel/elkhartlake/include/soc/me.h b/src/soc/intel/elkhartlake/include/soc/me.h index d845629..8d1021f 100644 --- a/src/soc/intel/elkhartlake/include/soc/me.h +++ b/src/soc/intel/elkhartlake/include/soc/me.h @@ -8,7 +8,7 @@ uint32_t data; struct { uint32_t working_state: 4; - uint32_t mfg_mode: 1; + uint32_t spi_protection_mode: 1; uint32_t fpt_bad: 1; uint32_t operation_state: 3; uint32_t fw_init_complete: 1; diff --git a/src/soc/intel/elkhartlake/me.c b/src/soc/intel/elkhartlake/me.c index d00702e..5087781 100644 --- a/src/soc/intel/elkhartlake/me.c +++ b/src/soc/intel/elkhartlake/me.c @@ -31,8 +31,8 @@ printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); - printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - hfsts1.fields.mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: SPI Protection Mode : %s\n", + hfsts1.fields.spi_protection_mode ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfsts1.fields.fpt_bad ? "BAD" : "OK"); printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", @@ -61,6 +61,8 @@ hfsts1.fields.error_code); printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n", hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfsts6.fields.fpf_soc_lock ? "NO" : "YES"); printk(BIOS_DEBUG, "ME: TXT Support : %s\n", hfsts6.fields.txt_support ? "YES" : "NO"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d1d004a6b5b276e33be80f02cd1197b88d379ae Gerrit-Change-Number: 48539 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/elkhartlake: Update pci dev definition
by Lean Sheng Tan (Code Review) 14 Dec '20

14 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48444 ) Change subject: soc/intel/elkhartlake: Update pci dev definition ...................................................................... soc/intel/elkhartlake: Update pci dev definition This change updates pci dev definition according to EHL EDS. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: Ibf7ef3c30deab5398361bc18fc63ac39fc914d8c --- M src/soc/intel/elkhartlake/chip.c M src/soc/intel/elkhartlake/include/soc/pci_devs.h 2 files changed, 63 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48444/1 diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c index cd65260..8b4cf0c 100644 --- a/src/soc/intel/elkhartlake/chip.c +++ b/src/soc/intel/elkhartlake/chip.c @@ -17,7 +17,7 @@ #include <soc/soc_chip.h> static const struct pcie_rp_group pch_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE, .count = 7 }, { 0 } }; @@ -64,16 +64,17 @@ switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_IPU: return "IPU0"; - case PCH_DEVFN_ISH: return "ISHB"; + case PCH_DEVFN_I2C6: return "I2C6"; + case PCH_DEVFN_I2C7: return "I2C7"; case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_I2C0: return "I2C0"; case PCH_DEVFN_I2C1: return "I2C1"; case PCH_DEVFN_I2C2: return "I2C2"; case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_SATA: return "SATA"; + case PCH_DEVFN_UART2: return "UAR2"; case PCH_DEVFN_I2C4: return "I2C4"; case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_SATA: return "SATA"; case PCH_DEVFN_PCIE1: return "RP01"; case PCH_DEVFN_PCIE2: return "RP02"; case PCH_DEVFN_PCIE3: return "RP03"; @@ -81,23 +82,16 @@ case PCH_DEVFN_PCIE5: return "RP05"; case PCH_DEVFN_PCIE6: return "RP06"; case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_UART2: return "UAR2"; case PCH_DEVFN_GSPI0: return "SPI0"; case PCH_DEVFN_GSPI1: return "SPI1"; + case PCH_DEVFN_GBE: return "GLAN"; case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_GSPI3: return "SPI3"; case PCH_DEVFN_EMMC: return "EMMC"; case PCH_DEVFN_SDCARD: return "SDXC"; case PCH_DEVFN_HDA: return "HDAS"; case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_GBE: return "GLAN"; } return NULL; diff --git a/src/soc/intel/elkhartlake/include/soc/pci_devs.h b/src/soc/intel/elkhartlake/include/soc/pci_devs.h index 0ae7db8..851832d 100644 --- a/src/soc/intel/elkhartlake/include/soc/pci_devs.h +++ b/src/soc/intel/elkhartlake/include/soc/pci_devs.h @@ -30,76 +30,58 @@ #define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) #define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) -#define SA_DEV_SLOT_TBT 0x07 -#define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) -#define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) -#define SA_DEVFN_TBT2 PCI_DEVFN(SA_DEV_SLOT_TBT, 2) -#define SA_DEVFN_TBT3 PCI_DEVFN(SA_DEV_SLOT_TBT, 3) -#define SA_DEV_TBT0 PCI_DEV(0, SA_DEV_SLOT_TBT, 0) -#define SA_DEV_TBT1 PCI_DEV(0, SA_DEV_SLOT_TBT, 1) -#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) -#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) +#define SA_DEV_SLOT_GNA 0x08 +#define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0) +#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0) -#define SA_DEV_SLOT_IPU 0x05 -#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) -#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) +#define SA_DEV_SLOT_TRACEHUB 0x09 +#define SA_DEVFN_TRACEHUB PCI_DEVFN(SA_DEV_SLOT_TRACEHUB, 0) +#define SA_DEV_TRACEHUB PCI_DEV(0, SA_DEV_SLOT_TRACEHUB, 0) /* PCH Devices */ -#define PCH_DEV_SLOT_SIO0 0x10 -#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2) -#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6) -#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7) -#define PCH_DEV_CNVI_BT _PCH_DEV(SIO0, 2) -#define PCH_DEV_THC0 _PCH_DEV(SIO0, 6) -#define PCH_DEV_THC1 _PCH_DEV(SIO0, 7) +#define PCH_DEV_SLOT_IEH 0x10 +#define PCH_DEVFN_I2C6 _PCH_DEVFN(IEH, 0) +#define PCH_DEVFN_I2C7 _PCH_DEVFN(IEH, 1) +#define PCH_DEVFN_IEH _PCH_DEVFN(IEH, 5) +#define PCH_DEV_I2C6 _PCH_DEV(IEH, 0) +#define PCH_DEV_I2C7 _PCH_DEV(IEH, 1) +#define PCH_DEV_IEH _PCH_DEV(IEH, 5) -#define PCH_DEV_SLOT_SIO1 0x11 -#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO1, 0) -#define PCH_DEV_UART3 _PCH_DEV(SIO1, 0) - -#define PCH_DEV_SLOT_ISH 0x12 -#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) -#define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6) -#define PCH_DEV_ISH _PCH_DEV(ISH, 0) -#define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6) - -#define PCH_DEV_SLOT_SIO2 0x13 -#define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO2, 0) -#define PCH_DEV_GSPI3 _PCH_DEV(SIO2, 0) +#define PCH_DEV_SLOT_SIO0 0x12 +#define PCH_DEVFN_GSPI2 _PCH_DEVFN(SIO0, 0) +#define PCH_DEVFN_CSE_UMA _PCH_DEVFN(SIO0, 3) +#define PCH_DEVFN_CSE_DMA _PCH_DEVFN(SIO0, 4) +#define PCH_DEVFN_UFS0 _PCH_DEVFN(SIO0, 5) +#define PCH_DEVFN_UFS1 _PCH_DEVFN(SIO0, 7) +#define PCH_DEV_GSPI2 _PCH_DEV(SIO0, 0) +#define PCH_DEV_CSE_UMA _PCH_DEV(SIO0, 3) +#define PCH_DEV_CSE_DMA _PCH_DEV(SIO0, 4) +#define PCH_DEV_UFS0 _PCH_DEV(SIO0, 5) +#define PCH_DEV_UFS1 _PCH_DEV(SIO0, 7) #define PCH_DEV_SLOT_XHCI 0x14 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) #define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) -#define PCH_DEVFN_SRAM _PCH_DEVFN(XHCI, 2) -#define PCH_DEVFN_CNVI_WIFI _PCH_DEVFN(XHCI, 3) #define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) #define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) -#define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) -#define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3) -#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) -#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) -#define PCH_DEV_SLOT_SIO3 0x15 -#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) -#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1) -#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO3, 2) -#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO3, 3) -#define PCH_DEV_I2C0 _PCH_DEV(SIO3, 0) -#define PCH_DEV_I2C1 _PCH_DEV(SIO3, 1) -#define PCH_DEV_I2C2 _PCH_DEV(SIO3, 2) -#define PCH_DEV_I2C3 _PCH_DEV(SIO3, 3) +#define PCH_DEV_SLOT_SIO1 0x15 +#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO1, 0) +#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO1, 1) +#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO1, 2) +#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO1, 3) +#define PCH_DEV_I2C0 _PCH_DEV(SIO1, 0) +#define PCH_DEV_I2C1 _PCH_DEV(SIO1, 1) +#define PCH_DEV_I2C2 _PCH_DEV(SIO1, 2) +#define PCH_DEV_I2C3 _PCH_DEV(SIO1, 3) #define PCH_DEV_SLOT_CSE 0x16 #define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) #define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1) -#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2) -#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3) #define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4) #define PCH_DEVFN_CSE_4 _PCH_DEVFN(CSE, 5) #define PCH_DEV_CSE _PCH_DEV(CSE, 0) #define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) -#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2) -#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3) #define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) #define PCH_DEV_CSE_4 _PCH_DEV(CSE, 5) @@ -107,17 +89,19 @@ #define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) #define PCH_DEV_SATA _PCH_DEV(SATA, 0) -#define PCH_DEV_SLOT_SIO4 0x19 -#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO4, 0) -#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO4, 1) -#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO4, 2) -#define PCH_DEV_I2C4 _PCH_DEV(SIO4, 0) -#define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) -#define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) +#define PCH_DEV_SLOT_SIO2 0x19 +#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0) +#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1) +#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 2) +#define PCH_DEV_I2C4 _PCH_DEV(SIO2, 0) +#define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1) +#define PCH_DEV_UART2 _PCH_DEV(SIO2, 2) #define PCH_DEV_SLOT_STORAGE 0x1a #define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) +#define PCH_DEVFN_SDCARD _PCH_DEVFN(STORAGE, 1) #define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) +#define PCH_DEV_SDCARD _PCH_DEV(STORAGE, 1) #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) @@ -127,7 +111,6 @@ #define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4) #define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5) #define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6) -#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7) #define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0) #define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1) #define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2) @@ -135,27 +118,22 @@ #define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4) #define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) #define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6) -#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7) -#define PCH_DEV_SLOT_PCIE_1 0x1d -#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0) -#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) -#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) -#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) -#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) -#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) -#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) -#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) - -#define PCH_DEV_SLOT_SIO5 0x1e -#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0) -#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO5, 1) -#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO5, 2) -#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO5, 3) -#define PCH_DEV_UART0 _PCH_DEV(SIO5, 0) -#define PCH_DEV_UART1 _PCH_DEV(SIO5, 1) -#define PCH_DEV_GSPI0 _PCH_DEV(SIO5, 2) -#define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3) +#define PCH_DEV_SLOT_SIO3 0x1e +#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0) +#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1) +#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO3, 2) +#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO3, 3) +#define PCH_DEVFN_GBE _PCH_DEVFN(SIO3, 4) +#define PCH_DEVFN_HPET _PCH_DEVFN(SIO3, 6) +#define PCH_DEVFN_IOAPIC _PCH_DEVFN(SIO3, 7) +#define PCH_DEV_UART0 _PCH_DEV(SIO3, 0) +#define PCH_DEV_UART1 _PCH_DEV(SIO3, 1) +#define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2) +#define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3) +#define PCH_DEV_GBE _PCH_DEV(SIO3, 4) +#define PCH_DEV_HPET _PCH_DEV(SIO3, 6) +#define PCH_DEV_IOAPIC _PCH_DEV(SIO3, 7) #define PCH_DEV_SLOT_ESPI 0x1f #define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI @@ -165,7 +143,6 @@ #define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3) #define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4) #define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) -#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) #define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) #define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) #define PCH_DEV_LPC PCH_DEV_ESPI @@ -186,7 +163,6 @@ #define PCH_DEV_HDA _PCH_DEV(ESPI, 3) #define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) #define PCH_DEV_SPI _PCH_DEV(ESPI, 5) -#define PCH_DEV_GBE _PCH_DEV(ESPI, 6) #define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7) #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf7ef3c30deab5398361bc18fc63ac39fc914d8c Gerrit-Change-Number: 48444 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
by Furquan Shaikh (Code Review) 14 Dec '20

14 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48281 ) Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage ...................................................................... Patch Set 6: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/48281/6/src/soc/intel/tigerlake/ro… File src/soc/intel/tigerlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/48281/6/src/soc/intel/tigerlake/ro… PS6, Line 140: /* cse_fw_sync() must be called after DRAM initialization */ Same comment as JSL. -- To view, visit https://review.coreboot.org/c/coreboot/+/48281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856 Gerrit-Change-Number: 48281 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Dec 2020 04:57:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2020