coreboot-gerrit December 2020

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Change in coreboot[master]: soc/intel/elkhartlake: Update HECI Control Status Register settings
by Lean Sheng Tan (Code Review) 13 Dec '20

13 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48539 ) Change subject: soc/intel/elkhartlake: Update HECI Control Status Register settings ...................................................................... soc/intel/elkhartlake: Update HECI Control Status Register settings For EHL, SpiProtectionMode is added to HFSTS register #1. The original Menufacturing Mode is detected via FpfSocConfigLock instead. If FpfSocConfigLock=1, means it is in Menufacturing Mode, and it is in EOM (End Of Manufacturing) when FpfSocConfigLock=0. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I9d1d004a6b5b276e33be80f02cd1197b88d379ae --- M src/soc/intel/elkhartlake/include/soc/me.h M src/soc/intel/elkhartlake/me.c 2 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/48539/1 diff --git a/src/soc/intel/elkhartlake/include/soc/me.h b/src/soc/intel/elkhartlake/include/soc/me.h index d845629..8d1021f 100644 --- a/src/soc/intel/elkhartlake/include/soc/me.h +++ b/src/soc/intel/elkhartlake/include/soc/me.h @@ -8,7 +8,7 @@ uint32_t data; struct { uint32_t working_state: 4; - uint32_t mfg_mode: 1; + uint32_t spi_protection_mode: 1; uint32_t fpt_bad: 1; uint32_t operation_state: 3; uint32_t fw_init_complete: 1; diff --git a/src/soc/intel/elkhartlake/me.c b/src/soc/intel/elkhartlake/me.c index d00702e..5087781 100644 --- a/src/soc/intel/elkhartlake/me.c +++ b/src/soc/intel/elkhartlake/me.c @@ -31,8 +31,8 @@ printk(BIOS_DEBUG, "ME: HFSTS5 : 0x%08X\n", hfsts5.data); printk(BIOS_DEBUG, "ME: HFSTS6 : 0x%08X\n", hfsts6.data); - printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", - hfsts1.fields.mfg_mode ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: SPI Protection Mode : %s\n", + hfsts1.fields.spi_protection_mode ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: FW Partition Table : %s\n", hfsts1.fields.fpt_bad ? "BAD" : "OK"); printk(BIOS_DEBUG, "ME: Bringup Loader Failure : %s\n", @@ -61,6 +61,8 @@ hfsts1.fields.error_code); printk(BIOS_DEBUG, "ME: CPU Debug Disabled : %s\n", hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); + printk(BIOS_DEBUG, "ME: Manufacturing Mode : %s\n", + hfsts6.fields.fpf_soc_lock ? "NO" : "YES"); printk(BIOS_DEBUG, "ME: TXT Support : %s\n", hfsts6.fields.txt_support ? "YES" : "NO"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d1d004a6b5b276e33be80f02cd1197b88d379ae Gerrit-Change-Number: 48539 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/elkhartlake: Update pci dev definition
by Lean Sheng Tan (Code Review) 13 Dec '20

13 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48444 ) Change subject: soc/intel/elkhartlake: Update pci dev definition ...................................................................... soc/intel/elkhartlake: Update pci dev definition This change updates pci dev definition according to EHL EDS. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: Ibf7ef3c30deab5398361bc18fc63ac39fc914d8c --- M src/soc/intel/elkhartlake/chip.c M src/soc/intel/elkhartlake/include/soc/pci_devs.h 2 files changed, 63 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48444/1 diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c index cd65260..8b4cf0c 100644 --- a/src/soc/intel/elkhartlake/chip.c +++ b/src/soc/intel/elkhartlake/chip.c @@ -17,7 +17,7 @@ #include <soc/soc_chip.h> static const struct pcie_rp_group pch_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, + { .slot = PCH_DEV_SLOT_PCIE, .count = 7 }, { 0 } }; @@ -64,16 +64,17 @@ switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; - case SA_DEVFN_IPU: return "IPU0"; - case PCH_DEVFN_ISH: return "ISHB"; + case PCH_DEVFN_I2C6: return "I2C6"; + case PCH_DEVFN_I2C7: return "I2C7"; case PCH_DEVFN_XHCI: return "XHCI"; case PCH_DEVFN_I2C0: return "I2C0"; case PCH_DEVFN_I2C1: return "I2C1"; case PCH_DEVFN_I2C2: return "I2C2"; case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_SATA: return "SATA"; + case PCH_DEVFN_UART2: return "UAR2"; case PCH_DEVFN_I2C4: return "I2C4"; case PCH_DEVFN_I2C5: return "I2C5"; - case PCH_DEVFN_SATA: return "SATA"; case PCH_DEVFN_PCIE1: return "RP01"; case PCH_DEVFN_PCIE2: return "RP02"; case PCH_DEVFN_PCIE3: return "RP03"; @@ -81,23 +82,16 @@ case PCH_DEVFN_PCIE5: return "RP05"; case PCH_DEVFN_PCIE6: return "RP06"; case PCH_DEVFN_PCIE7: return "RP07"; - case PCH_DEVFN_PCIE8: return "RP08"; - case PCH_DEVFN_PCIE9: return "RP09"; - case PCH_DEVFN_PCIE10: return "RP10"; - case PCH_DEVFN_PCIE11: return "RP11"; - case PCH_DEVFN_PCIE12: return "RP12"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; - case PCH_DEVFN_UART2: return "UAR2"; case PCH_DEVFN_GSPI0: return "SPI0"; case PCH_DEVFN_GSPI1: return "SPI1"; + case PCH_DEVFN_GBE: return "GLAN"; case PCH_DEVFN_GSPI2: return "SPI2"; - case PCH_DEVFN_GSPI3: return "SPI3"; case PCH_DEVFN_EMMC: return "EMMC"; case PCH_DEVFN_SDCARD: return "SDXC"; case PCH_DEVFN_HDA: return "HDAS"; case PCH_DEVFN_SMBUS: return "SBUS"; - case PCH_DEVFN_GBE: return "GLAN"; } return NULL; diff --git a/src/soc/intel/elkhartlake/include/soc/pci_devs.h b/src/soc/intel/elkhartlake/include/soc/pci_devs.h index 0ae7db8..851832d 100644 --- a/src/soc/intel/elkhartlake/include/soc/pci_devs.h +++ b/src/soc/intel/elkhartlake/include/soc/pci_devs.h @@ -30,76 +30,58 @@ #define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0) #define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0) -#define SA_DEV_SLOT_TBT 0x07 -#define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0) -#define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1) -#define SA_DEVFN_TBT2 PCI_DEVFN(SA_DEV_SLOT_TBT, 2) -#define SA_DEVFN_TBT3 PCI_DEVFN(SA_DEV_SLOT_TBT, 3) -#define SA_DEV_TBT0 PCI_DEV(0, SA_DEV_SLOT_TBT, 0) -#define SA_DEV_TBT1 PCI_DEV(0, SA_DEV_SLOT_TBT, 1) -#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2) -#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) +#define SA_DEV_SLOT_GNA 0x08 +#define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0) +#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0) -#define SA_DEV_SLOT_IPU 0x05 -#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0) -#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0) +#define SA_DEV_SLOT_TRACEHUB 0x09 +#define SA_DEVFN_TRACEHUB PCI_DEVFN(SA_DEV_SLOT_TRACEHUB, 0) +#define SA_DEV_TRACEHUB PCI_DEV(0, SA_DEV_SLOT_TRACEHUB, 0) /* PCH Devices */ -#define PCH_DEV_SLOT_SIO0 0x10 -#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2) -#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6) -#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7) -#define PCH_DEV_CNVI_BT _PCH_DEV(SIO0, 2) -#define PCH_DEV_THC0 _PCH_DEV(SIO0, 6) -#define PCH_DEV_THC1 _PCH_DEV(SIO0, 7) +#define PCH_DEV_SLOT_IEH 0x10 +#define PCH_DEVFN_I2C6 _PCH_DEVFN(IEH, 0) +#define PCH_DEVFN_I2C7 _PCH_DEVFN(IEH, 1) +#define PCH_DEVFN_IEH _PCH_DEVFN(IEH, 5) +#define PCH_DEV_I2C6 _PCH_DEV(IEH, 0) +#define PCH_DEV_I2C7 _PCH_DEV(IEH, 1) +#define PCH_DEV_IEH _PCH_DEV(IEH, 5) -#define PCH_DEV_SLOT_SIO1 0x11 -#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO1, 0) -#define PCH_DEV_UART3 _PCH_DEV(SIO1, 0) - -#define PCH_DEV_SLOT_ISH 0x12 -#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) -#define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6) -#define PCH_DEV_ISH _PCH_DEV(ISH, 0) -#define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6) - -#define PCH_DEV_SLOT_SIO2 0x13 -#define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO2, 0) -#define PCH_DEV_GSPI3 _PCH_DEV(SIO2, 0) +#define PCH_DEV_SLOT_SIO0 0x12 +#define PCH_DEVFN_GSPI2 _PCH_DEVFN(SIO0, 0) +#define PCH_DEVFN_CSE_UMA _PCH_DEVFN(SIO0, 3) +#define PCH_DEVFN_CSE_DMA _PCH_DEVFN(SIO0, 4) +#define PCH_DEVFN_UFS0 _PCH_DEVFN(SIO0, 5) +#define PCH_DEVFN_UFS1 _PCH_DEVFN(SIO0, 7) +#define PCH_DEV_GSPI2 _PCH_DEV(SIO0, 0) +#define PCH_DEV_CSE_UMA _PCH_DEV(SIO0, 3) +#define PCH_DEV_CSE_DMA _PCH_DEV(SIO0, 4) +#define PCH_DEV_UFS0 _PCH_DEV(SIO0, 5) +#define PCH_DEV_UFS1 _PCH_DEV(SIO0, 7) #define PCH_DEV_SLOT_XHCI 0x14 #define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) #define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1) -#define PCH_DEVFN_SRAM _PCH_DEVFN(XHCI, 2) -#define PCH_DEVFN_CNVI_WIFI _PCH_DEVFN(XHCI, 3) #define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) #define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1) -#define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) -#define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3) -#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) -#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) -#define PCH_DEV_SLOT_SIO3 0x15 -#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) -#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1) -#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO3, 2) -#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO3, 3) -#define PCH_DEV_I2C0 _PCH_DEV(SIO3, 0) -#define PCH_DEV_I2C1 _PCH_DEV(SIO3, 1) -#define PCH_DEV_I2C2 _PCH_DEV(SIO3, 2) -#define PCH_DEV_I2C3 _PCH_DEV(SIO3, 3) +#define PCH_DEV_SLOT_SIO1 0x15 +#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO1, 0) +#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO1, 1) +#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO1, 2) +#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO1, 3) +#define PCH_DEV_I2C0 _PCH_DEV(SIO1, 0) +#define PCH_DEV_I2C1 _PCH_DEV(SIO1, 1) +#define PCH_DEV_I2C2 _PCH_DEV(SIO1, 2) +#define PCH_DEV_I2C3 _PCH_DEV(SIO1, 3) #define PCH_DEV_SLOT_CSE 0x16 #define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) #define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1) -#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2) -#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3) #define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4) #define PCH_DEVFN_CSE_4 _PCH_DEVFN(CSE, 5) #define PCH_DEV_CSE _PCH_DEV(CSE, 0) #define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) -#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2) -#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3) #define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4) #define PCH_DEV_CSE_4 _PCH_DEV(CSE, 5) @@ -107,17 +89,19 @@ #define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) #define PCH_DEV_SATA _PCH_DEV(SATA, 0) -#define PCH_DEV_SLOT_SIO4 0x19 -#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO4, 0) -#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO4, 1) -#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO4, 2) -#define PCH_DEV_I2C4 _PCH_DEV(SIO4, 0) -#define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) -#define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) +#define PCH_DEV_SLOT_SIO2 0x19 +#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0) +#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1) +#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 2) +#define PCH_DEV_I2C4 _PCH_DEV(SIO2, 0) +#define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1) +#define PCH_DEV_UART2 _PCH_DEV(SIO2, 2) #define PCH_DEV_SLOT_STORAGE 0x1a #define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) +#define PCH_DEVFN_SDCARD _PCH_DEVFN(STORAGE, 1) #define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) +#define PCH_DEV_SDCARD _PCH_DEV(STORAGE, 1) #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) @@ -127,7 +111,6 @@ #define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4) #define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5) #define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6) -#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7) #define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0) #define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1) #define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2) @@ -135,27 +118,22 @@ #define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4) #define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5) #define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6) -#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7) -#define PCH_DEV_SLOT_PCIE_1 0x1d -#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0) -#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) -#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) -#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) -#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) -#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) -#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) -#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) - -#define PCH_DEV_SLOT_SIO5 0x1e -#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0) -#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO5, 1) -#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO5, 2) -#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO5, 3) -#define PCH_DEV_UART0 _PCH_DEV(SIO5, 0) -#define PCH_DEV_UART1 _PCH_DEV(SIO5, 1) -#define PCH_DEV_GSPI0 _PCH_DEV(SIO5, 2) -#define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3) +#define PCH_DEV_SLOT_SIO3 0x1e +#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0) +#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1) +#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO3, 2) +#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO3, 3) +#define PCH_DEVFN_GBE _PCH_DEVFN(SIO3, 4) +#define PCH_DEVFN_HPET _PCH_DEVFN(SIO3, 6) +#define PCH_DEVFN_IOAPIC _PCH_DEVFN(SIO3, 7) +#define PCH_DEV_UART0 _PCH_DEV(SIO3, 0) +#define PCH_DEV_UART1 _PCH_DEV(SIO3, 1) +#define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2) +#define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3) +#define PCH_DEV_GBE _PCH_DEV(SIO3, 4) +#define PCH_DEV_HPET _PCH_DEV(SIO3, 6) +#define PCH_DEV_IOAPIC _PCH_DEV(SIO3, 7) #define PCH_DEV_SLOT_ESPI 0x1f #define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI @@ -165,7 +143,6 @@ #define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3) #define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4) #define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) -#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) #define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) #define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) #define PCH_DEV_LPC PCH_DEV_ESPI @@ -186,7 +163,6 @@ #define PCH_DEV_HDA _PCH_DEV(ESPI, 3) #define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) #define PCH_DEV_SPI _PCH_DEV(ESPI, 5) -#define PCH_DEV_GBE _PCH_DEV(ESPI, 6) #define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7) #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf7ef3c30deab5398361bc18fc63ac39fc914d8c Gerrit-Change-Number: 48444 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
by Furquan Shaikh (Code Review) 13 Dec '20

13 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48281 ) Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage ...................................................................... Patch Set 6: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/48281/6/src/soc/intel/tigerlake/ro… File src/soc/intel/tigerlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/48281/6/src/soc/intel/tigerlake/ro… PS6, Line 140: /* cse_fw_sync() must be called after DRAM initialization */ Same comment as JSL. -- To view, visit https://review.coreboot.org/c/coreboot/+/48281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856 Gerrit-Change-Number: 48281 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Dec 2020 04:57:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the...
by Furquan Shaikh (Code Review) 13 Dec '20

13 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48280 ) Change subject: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage ...................................................................... Patch Set 6: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/48280/6/src/soc/intel/jasperlake/r… File src/soc/intel/jasperlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/48280/6/src/soc/intel/jasperlake/r… PS6, Line 140: cse_fw_sync() must be called after DRAM initialization It would be helpful to also add the information that HMRFPO (which is used by cse_fw_sync()) is expected to be executed only after DRAM initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/48280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a Gerrit-Change-Number: 48280 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Dec 2020 04:55:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Sugnan Prabhu S (Code Review) 13 Dec '20

13 Dec '20

Sugnan Prabhu S has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 70: (3 comments) https://review.coreboot.org/c/coreboot/+/27369/70/Documentation/soc/intel/u… File Documentation/soc/intel/ucode_update/microcode_update_model.md: PS70: > I haven't got a chance to go through the doc and the changes again. […] Ack https://review.coreboot.org/c/coreboot/+/27369/70/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/70/src/soc/intel/common/base… PS70, Line 131: 0x32 > This needs to be added to vboot library first. Ack https://review.coreboot.org/c/coreboot/+/27369/70/src/soc/intel/common/base… PS70, Line 264: BS_PRE_DEVICE > Why is this stage chosen for ucode update? CSE update is moving to romstage. […] It will moved form here and called from https://review.coreboot.org/c/coreboot/+/46819/6/src/soc/intel/common/basec… -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 70 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Mon, 14 Dec 2020 04:53:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Move CSE Lite driver functionality into romstage
by Furquan Shaikh (Code Review) 13 Dec '20

13 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48279 ) Change subject: soc/intel/common: Move CSE Lite driver functionality into romstage ...................................................................... Patch Set 6: Code-Review+2 (1 comment) Just a note - this CL will have to be cherry-picked along with the follow-up changes in chromium tree to ensure we don't break the behavior on any TGL/JSL boards. https://review.coreboot.org/c/coreboot/+/48279/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/48279/2//COMMIT_MSG@13 PS2, Line 13: Verified on JSL and TGL platforms > Ack Can you please add that detail to the commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/48279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73 Gerrit-Change-Number: 48279 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Dec 2020 04:49:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: WIP: soc/mediatek/mt8192: Add display controller driver
by yongqiang niu (Code Review) 13 Dec '20

13 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46577 ) Change subject: WIP: soc/mediatek/mt8192: Add display controller driver ...................................................................... WIP: soc/mediatek/mt8192: Add display controller driver The MT8192 SOC has a DISP (display controller) that supports overlay, read/write DMA, ... etc. The output of DISP goes to display interface DSI, DPI or DBI directly. BUG=b:80501386,b:155713214 BRANCH=none TEST=Boots correctly on asurada Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/ddp.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ddp.h 4 files changed, 485 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46577/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index b2a8a9e..119d999 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -59,6 +59,7 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c +ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/dsi.c dsi.c MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 diff --git a/src/soc/mediatek/mt8192/ddp.c b/src/soc/mediatek/mt8192/ddp.c new file mode 100644 index 0000000..0d5eab5 --- /dev/null +++ b/src/soc/mediatek/mt8192/ddp.c @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <edid.h> +#include <soc/addressmap.h> +#include <soc/ddp.h> + +static void disp_config_main_path_connection(void) +{ + /* ovl0->ovl0_2l */ + write32(&mmsys_cfg->mmsys_ovl_mout_en, + (DISP_OVL0_GO_BG | DISP_OVL0_2L_GO_BLEND)); + write32(&mmsys_cfg->ovl0_2l_mout_en, OVL0_MOUT_EN_DISP_RDMA0); + write32(&mmsys_cfg->rdma0_sel_in, RDMA0_SEL_IN_OVL0_2L); + write32(&mmsys_cfg->rdma0_sout_sel, RDMA0_SOUT_COLOR0); + write32(&mmsys_cfg->ccorr0_sout_sel, CCORR0_SOUT_AAL0); + write32(&mmsys_cfg->aal0_sel_in, AAL0_SEL_IN_CCORR0); + write32(&mmsys_cfg->dither0_mout_en, DITHER0_MOUT_DSI0); + write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0); +} + +static void disp_config_main_path_mutex(void) +{ + write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); + + /* Clock source from DSI0 */ + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6)); + write32(&disp_mutex->mutex[0].en, BIT(0)); +} + +static void ovl_bgclr_in_sel(u32 idx) +{ + setbits32(&disp_ovl[idx]->datapath_con, BIT(2)); +} + +static void ovl_layer_smi_id_en(u32 idx) +{ + printk(BIOS_INFO, "%s\n", __func__); + + setbits32(&disp_ovl[idx]->datapath_con, BIT(0)); +} + +static void ccorr_config(u32 width, u32 height) +{ + struct disp_ccorr_regs *const regs = disp_ccorr; + int enable_relay = 0; + + printk(BIOS_INFO, "%s\n", __func__); + + write32(&regs->size, width << 16 | height); + + if (enable_relay) { + setbits32(&regs->cfg, PQ_RELAY_MODE); + clrbits32(&regs->cfg, PQ_ENGINE_EN); + } else { + clrbits32(&regs->cfg, PQ_RELAY_MODE); + setbits32(&regs->cfg, PQ_ENGINE_EN); + } + + write32(&regs->en, PQ_EN); +} + +static void aal_config(u32 width, u32 height) +{ + struct disp_aal_regs *const regs = disp_aal; + int enable_relay = 1; + + printk(BIOS_INFO, "%s\n", __func__); + + write32(&regs->size, width << 16 | height); + write32(&regs->output_size, width << 16 | height); + + if (enable_relay) { + setbits32(&regs->cfg, PQ_RELAY_MODE); + clrbits32(&regs->cfg, PQ_ENGINE_EN); + } else { + clrbits32(&regs->cfg, PQ_RELAY_MODE); + setbits32(&regs->cfg, PQ_ENGINE_EN); + } + + write32(&regs->en, PQ_EN); +} + +static void gamma_config(u32 width, u32 height) +{ + struct disp_gamma_regs *const regs = disp_gamma; + int enable_relay = 0; + + printk(BIOS_INFO, "%s\n", __func__); + + write32(&regs->size, width << 16 | height); + + if (enable_relay) + setbits32(&regs->cfg, PQ_RELAY_MODE); + else + clrbits32(&regs->cfg, PQ_RELAY_MODE); + + write32(&regs->en, PQ_EN); +} + +static void postmask_config(u32 width, u32 height) +{ + struct disp_postmask_regs *const regs = disp_postmask; + int enable_relay = 1; + + printk(BIOS_INFO, "%s\n", __func__); + + write32(&regs->size, width << 16 | height); + + if (enable_relay) + setbits32(&regs->cfg, PQ_RELAY_MODE); + else + clrbits32(&regs->cfg, PQ_RELAY_MODE); + + write32(&regs->en, PQ_EN); +} + +static void dither_config(u32 width, u32 height) +{ + struct disp_dither_regs *const regs = disp_dither; + int enable_relay = 1; + + printk(BIOS_INFO, "%s\n", __func__); + + write32(&regs->size, width << 16 | height); + + if (enable_relay) + setbits32(&regs->cfg, PQ_RELAY_MODE); + else + clrbits32(&regs->cfg, PQ_RELAY_MODE); + + write32(&regs->en, PQ_EN); +} + + +static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) +{ + u32 idx = 0; + u32 pixel_clk = width * height * vrefresh; + + printk(BIOS_INFO, "%s\n", __func__); + + for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) { + ovl_set_roi(idx, width, height, idx ? 0 : 0xff0000ff); + ovl_layer_smi_id_en(idx); + } + + rdma_config(width, height, pixel_clk, 5 * KiB); + color_start(width, height); + ccorr_config(width, height); + aal_config(width, height); + gamma_config(width, height); + postmask_config(width, height); + dither_config(width, height); + disp_config_main_path_connection(); + disp_config_main_path_mutex(); +} + +static void disp_clock_on(void) +{ + clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); + + clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_ALL); + + clrbits32(&mmsys_cfg->mmsys_cg_con2, CG_CON2_DISP_ALL); +} + +void mtk_ddp_init(void) +{ + disp_clock_on(); + /* Turn off M4U port. */ + write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_DISP_POSTMASK0), 0); + write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0_HDR), 0); + write32((void *)(SMI_LARB0 + SMI_LARB_L0_OVL_RDMA0), 0); +} + +void mtk_ddp_mode_set(const struct edid *edid) +{ + u32 fmt = OVL_INFMT_RGBA8888; + u32 bpp = edid->framebuffer_bits_per_pixel / 8; + u32 width = edid->mode.ha; + u32 height = edid->mode.va; + u32 vrefresh = edid->mode.refresh; + + printk(BIOS_INFO, "%s display resolution: %dx%d@%d bpp %d\n", + __func__, width, height, vrefresh, bpp); + + if (!vrefresh) { + vrefresh = 60; + printk(BIOS_INFO, "%s invalid vrefresh %d\n", + __func__, vrefresh); + } + + main_disp_path_setup(width, height, vrefresh); + rdma_start(); + ovl_layer_config(fmt, bpp, width, height); + ovl_bgclr_in_sel(1); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index eac4a9a..198beaa 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -65,6 +65,19 @@ MSDC0_BASE = IO_PHYS + 0x01F60000, DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000, MIPITX_BASE = IO_PHYS + 0x01E50000, + MMSYS_BASE = IO_PHYS + 0x04000000, + DISP_MUTEX_BASE = IO_PHYS + 0x04001000, + SMI_BASE = IO_PHYS + 0x04002000, + SMI_LARB0 = IO_PHYS + 0x04003000, + DISP_OVL0_BASE = IO_PHYS + 0x04005000, /* ovl0 */ + DISP_OVL1_BASE = IO_PHYS + 0x04006000, /* ovl0_2l */ + DISP_RDMA0_BASE = IO_PHYS + 0x04007000, + DISP_COLOR0_BASE = IO_PHYS + 0x04009000, + DISP_CCORR0_BASE = IO_PHYS + 0x0400A000, + DISP_AAL0_BASE = IO_PHYS + 0x0400B000, + DISP_GAMMA0_BASE = IO_PHYS + 0x0400C000, + DISP_POSTMASK0_BASE = IO_PHYS + 0x0400D000, + DISP_DITHER0_BASE = IO_PHYS + 0x0400E000, DSI0_BASE = IO_PHYS + 0x04010000, }; diff --git a/src/soc/mediatek/mt8192/include/soc/ddp.h b/src/soc/mediatek/mt8192/include/soc/ddp.h new file mode 100644 index 0000000..18b2e27 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/ddp.h @@ -0,0 +1,272 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MT8183_SOC_DDP_H_ +#define _MT8183_SOC_DDP_H_ + +#include <soc/addressmap.h> +#include <soc/ddp_common.h> +#include <types.h> + +#define MAIN_PATH_OVL_NR 2 + +struct mmsys_cfg_regs { + u32 reserved_0x000[64]; /* 0x000 */ + u32 mmsys_cg_con0; /* 0x100 */ + u32 mmsys_cg_set0; /* 0x104 */ + u32 mmsys_cg_clr0; /* 0x108 */ + u32 reserved_0x10C; /* 0x10C */ + u32 mmsys_cg_con1; /* 0x110 */ + u32 mmsys_cg_set1; /* 0x114 */ + u32 mmsys_cg_clr1; /* 0x118 */ + u32 reserved_0x11C[33]; /* 0x11C */ + u32 mmsys_cg_con2; /* 0x1A0 */ + u32 mmsys_cg_set2; /* 0x1A4 */ + u32 mmsys_cg_clr2; /* 0x1A8 */ + u32 reserved_0x1AC[853]; /* 0x1AC */ + u32 reserved_0xF00; /* 0xF00 */ + u32 mmsys_ovl_mout_en; /* 0xF04 */ + u32 reserved_0xF08; /* 0xF08 */ + u32 reserved_0xF0C; /* 0xF0C */ + u32 reserved_0xF10; /* 0xF10 */ + u32 reserved_0xF14; /* 0xF14 */ + u32 ovl0_2l_mout_en; /* 0xF18 */ + u32 ovl0_mout_en; /* 0xF1C */ + u32 reserved_0xF20; /* 0xF20 */ + u32 reserved_0xF24; /* 0xF24 */ + u32 reserved_0xF28; /* 0xF28 */ + u32 rdma0_sel_in; /* 0xF2C */ + u32 rdma0_sout_sel; /* 0xF30 */ + u32 ccorr0_sout_sel; /* 0xF34 */ + u32 aal0_sel_in; /* 0xF38 */ + u32 dither0_mout_en; /* 0xF3C*/ + u32 dsi0_sel_in; /* 0xF40*/ +}; + +check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100); +check_member(mmsys_cfg_regs, mmsys_cg_con1, 0x110); +check_member(mmsys_cfg_regs, mmsys_cg_con2, 0x1A0); +check_member(mmsys_cfg_regs, mmsys_ovl_mout_en, 0xF04); +check_member(mmsys_cfg_regs, ovl0_2l_mout_en, 0xF18); +check_member(mmsys_cfg_regs, dsi0_sel_in, 0xF40); +static struct mmsys_cfg_regs *const mmsys_cfg = + (void *)MMSYS_BASE; + + +/* DISP_REG_CONFIG_MMSYS_CG_CON0 + Configures free-run clock gating 0 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON0_DISP_MUTEX0 = BIT(0), + CG_CON0_DISPSYS_CONFIG = BIT(1), + CG_CON0_DISP_OVL0 = BIT(2), + CG_CON0_DISP_RDMA0 = BIT(3), + CG_CON0_DISP_OVL0_2L = BIT(4), + CG_CON0_DISP_AAL0 = BIT(8), + CG_CON0_DISP_CCORR0 = BIT(9), + CG_CON0_DISP_DITHER0 = BIT(10), + CG_CON0_SMI_INFRA = BIT(11), + CG_CON0_DISP_GAMMA0 = BIT(12), + CG_CON0_DISP_POSTMASK0 = BIT(13), + CG_CON0_DISP_DSI0 = BIT(15), + CG_CON0_DISP_COLOR0 = BIT(16), + CG_CON0_SMI_COMMON = BIT(17), + + CG_CON0_SMI_GALS = BIT(27), + CG_CON0_DISP_ALL = CG_CON0_SMI_INFRA | + CG_CON0_SMI_COMMON | + CG_CON0_SMI_GALS | + CG_CON0_DISP_MUTEX0 | + CG_CON0_DISPSYS_CONFIG | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_OVL0_2L | + CG_CON0_DISP_AAL0 | + CG_CON0_DISP_CCORR0 | + CG_CON0_DISP_DITHER0 | + CG_CON0_DISP_GAMMA0 | + CG_CON0_DISP_POSTMASK0 | + CG_CON0_DISP_DSI0 | + CG_CON0_DISP_COLOR0, + CG_CON0_ALL = 0xffffffff +}; + +/* DISP_REG_CONFIG_MMSYS_CG_CON1 + Configures free-run clock gating 1 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON1_SMI_IOMMU = BIT(0), + CG_CON1_DISP_ALL = CG_CON1_SMI_IOMMU, + CG_CON1_ALL = 0xffffffff +}; + +enum { + CG_CON2_DSI_DSI0 = BIT(0), + CG_CON2_DPI_DPI0 = BIT(8), + CG_CON2_MM_26MHZ = BIT(24), + CG_CON2_DISP_ALL = CG_CON2_DSI_DSI0 | + CG_CON2_MM_26MHZ, + CG_CON2_ALL = 0xffffffff +}; + + +enum { + DISP_OVL0_GO_BLEND = BIT(0), + DISP_OVL0_GO_BG = BIT(1), + DISP_OVL0_2L_GO_BLEND = BIT(2), + DISP_OVL0_2L_GO_BG = BIT(3), + OVL0_MOUT_EN_DISP_RDMA0 = BIT(0), + DITHER0_MOUT_DSI0 = BIT(0), +}; + +enum { + RDMA0_SEL_IN_OVL0_2L = 0x3, + RDMA0_SOUT_COLOR0 = 0x1, + CCORR0_SOUT_AAL0 = 0x1, + AAL0_SEL_IN_CCORR0 = 0x1, + DSI0_SEL_IN_DITHER0 = 0x1, +}; + +struct disp_mutex_regs { + u32 inten; + u32 intsta; + u32 reserved0[6]; + struct { + u32 en; + u32 dummy; + u32 rst; + u32 ctl; + u32 mod; + u32 reserved[3]; + } mutex[12]; +}; + +static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE; + +enum { + MUTEX_MOD_DISP_OVL0 = BIT(0), + MUTEX_MOD_DISP_OVL0_2L = BIT(1), + MUTEX_MOD_DISP_RDMA0 = BIT(2), + MUTEX_MOD_DISP_COLOR0 = BIT(4), + MUTEX_MOD_DISP_CCORR0 = BIT(5), + MUTEX_MOD_DISP_AAL0 = BIT(6), + MUTEX_MOD_DISP_GAMMA0 = BIT(7), + MUTEX_MOD_DISP_POSTMASK0 = BIT(8), + MUTEX_MOD_DISP_DITHER0 = BIT(9), + MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | + MUTEX_MOD_DISP_OVL0_2L | + MUTEX_MOD_DISP_RDMA0 | + MUTEX_MOD_DISP_COLOR0 | + MUTEX_MOD_DISP_CCORR0 | + MUTEX_MOD_DISP_AAL0 | + MUTEX_MOD_DISP_GAMMA0 | + MUTEX_MOD_DISP_POSTMASK0 | + MUTEX_MOD_DISP_DITHER0, +}; + +enum { + MUTEX_SOF_SINGLE_MODE = 0, + MUTEX_SOF_DSI0 = 1, + MUTEX_SOF_DPI0 = 2, +}; + +struct disp_ccorr_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[27]; + u32 shadow; +}; +check_member(disp_ccorr_regs, shadow, 0xA0); + +struct disp_gamma_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; +check_member(disp_gamma_regs, size, 0x30); + +struct disp_aal_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[47]; + u32 shadow; + u32 reserved3[249]; + u32 output_size; +}; +check_member(disp_aal_regs, shadow, 0xF0); +check_member(disp_aal_regs, output_size, 0x4D8); + +struct disp_postmask_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 reserved0[4]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; +check_member(disp_postmask_regs, size, 0x30); + +struct disp_dither_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[51]; + u32 shadow; +}; +check_member(disp_dither_regs, shadow, 0x100); + +enum { + PQ_EN = BIT(0), + PQ_RELAY_MODE = BIT(0), + PQ_ENGINE_EN = BIT(1), +}; + +static struct disp_ccorr_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE; + +static struct disp_aal_regs *const disp_aal = (void *)DISP_AAL0_BASE; + +static struct disp_gamma_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE; + +static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE; + +static struct disp_postmask_regs *const disp_postmask = (void *)DISP_POSTMASK0_BASE; + +enum { + SMI_LARB_PORT_L0_DISP_POSTMASK0 = 0x380, + SMI_LARB_PORT_L0_OVL_RDMA0_HDR = 0x384, + SMI_LARB_L0_OVL_RDMA0 = 0x388, +}; + +void mtk_ddp_init(void); +void mtk_ddp_mode_set(const struct edid *edid); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154 Gerrit-Change-Number: 46577 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: DO-NOT-SUBMIT: Asurada ToT - Load firmware API
by Yidi Lin (Code Review) 13 Dec '20

13 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48442 ) Change subject: DO-NOT-SUBMIT: Asurada ToT - Load firmware API ...................................................................... DO-NOT-SUBMIT: Asurada ToT - Load firmware API Snapshot of dev ToT #44 excluding mcu patches. Change-Id: Ia76eacef6c22c3ed882e4ef72e94576098baa20c Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M 3rdparty/qc_blobs M README.md M src/mainboard/google/asurada/Kconfig M src/mainboard/google/asurada/Makefile.inc M src/mainboard/google/asurada/mainboard.c A src/mainboard/google/asurada/panel.h A src/mainboard/google/asurada/panel_anx7625.c M src/mainboard/google/asurada/sdram_configs.c M src/mainboard/google/asurada/sdram_params/Makefile.inc A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c A src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c M src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZAD8GQFSL-046-4GB.c M src/mainboard/google/asurada/sdram_params/sdram-lpddr4x-MT29VZZZBD9DQKPR-046-6GB.c M src/soc/mediatek/common/i2c.c M src/soc/mediatek/common/include/soc/i2c_common.h M src/soc/mediatek/common/include/soc/rtc_common.h M src/soc/mediatek/common/rtc.c M src/soc/mediatek/mt8192/Kconfig M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c A src/soc/mediatek/mt8192/clkbuf.c A src/soc/mediatek/mt8192/ddp.c A src/soc/mediatek/mt8192/devapc.c A src/soc/mediatek/mt8192/dramc_ana_init_config.c A src/soc/mediatek/mt8192/dramc_dig_config.c A src/soc/mediatek/mt8192/dramc_dvfs.c A src/soc/mediatek/mt8192/dramc_pi_basic_api.c A src/soc/mediatek/mt8192/dramc_pi_calibration_api.c A src/soc/mediatek/mt8192/dramc_pi_main.c A src/soc/mediatek/mt8192/dramc_power.c A src/soc/mediatek/mt8192/dramc_subsys_config.c A src/soc/mediatek/mt8192/dramc_tracking.c A src/soc/mediatek/mt8192/dramc_utility.c A src/soc/mediatek/mt8192/dsi.c A src/soc/mediatek/mt8192/eint_event.c M src/soc/mediatek/mt8192/emi.c A src/soc/mediatek/mt8192/i2c.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/clkbuf.h A src/soc/mediatek/mt8192/include/soc/ddp.h A src/soc/mediatek/mt8192/include/soc/devapc.h A src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h M src/soc/mediatek/mt8192/include/soc/dramc_param.h A src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h A src/soc/mediatek/mt8192/include/soc/dramc_power.h A src/soc/mediatek/mt8192/include/soc/dramc_register.h A src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h A src/soc/mediatek/mt8192/include/soc/dsi.h A src/soc/mediatek/mt8192/include/soc/eint_event.h A src/soc/mediatek/mt8192/include/soc/i2c.h M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/include/soc/pmif.h A src/soc/mediatek/mt8192/include/soc/rtc.h A src/soc/mediatek/mt8192/include/soc/srclken_rc.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/memory.c M src/soc/mediatek/mt8192/mt6359p.c M src/soc/mediatek/mt8192/pll.c M src/soc/mediatek/mt8192/pmif.c A src/soc/mediatek/mt8192/rtc.c M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/srclken_rc.c A src/soc/mediatek/mt8192/ufs.c 66 files changed, 22,780 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/48442/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/48442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia76eacef6c22c3ed882e4ef72e94576098baa20c Gerrit-Change-Number: 48442 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: WIP: coreboot: Add dsi file
by yongqiang niu (Code Review) 13 Dec '20

13 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46574 ) Change subject: WIP: coreboot: Add dsi file ...................................................................... WIP: coreboot: Add dsi file Add dsi APIs for coreboot display Signed-off-by: Huijuan Xie <huijuan.xie(a)mediatek.corp-partner.google.com> Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dsi.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dsi.h 4 files changed, 129 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46574/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 04d57dc..b2a8a9e 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -59,6 +59,8 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c +ramstage-y += ../common/dsi.c dsi.c + MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 cbfs-files-y += dpm.dm diff --git a/src/soc/mediatek/mt8192/dsi.c b/src/soc/mediatek/mt8192/dsi.c new file mode 100644 index 0000000..9f54f49 --- /dev/null +++ b/src/soc/mediatek/mt8192/dsi.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <device/mmio.h> +#include <delay.h> +#include <soc/dsi.h> +#include <soc/pll.h> + +void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes) +{ + unsigned int txdiv0, txdiv1; + u64 pcw; + + if (data_rate >= 2000 * MHz) { + txdiv0 = 0; + txdiv1 = 0; + } else if (data_rate >= 1000 * MHz) { + txdiv0 = 1; + txdiv1 = 0; + } else if (data_rate >= 500 * MHz) { + txdiv0 = 2; + txdiv1 = 0; + } else if (data_rate > 250 * MHz) { + /* (data_rate == 250MHz) is a special case that should go to the + else-block below (txdiv0 = 4) */ + txdiv0 = 3; + txdiv1 = 0; + } else { + /* MIN = 125 */ + assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz); + txdiv0 = 4; + txdiv1 = 0; + } + + clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10)); + setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON); + udelay(30); + clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN); + + pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1); + pcw <<= 24; + pcw /= CLK26M_HZ; + + write32(&mipi_tx->pll_con0, pcw); + clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8); + udelay(30); + setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN); + + /* BG_LPF_EN / BG_CORE_EN */ + write32(&mipi_tx->lane_con, 0x3fff0180); + udelay(40); + write32(&mipi_tx->lane_con, 0x3fff00c0); + + /* Switch OFF each Lane */ + clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN); + + setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN); +} + +void mtk_dsi_reset(void) +{ + write32(&dsi0->dsi_force_commit, + DSI_FORCE_COMMIT_USE_MMSYS | DSI_FORCE_COMMIT_ALWAYS); + write32(&dsi0->dsi_con_ctrl, 1); + write32(&dsi0->dsi_con_ctrl, 0); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 3fd2bca..eac4a9a 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -64,6 +64,8 @@ MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, MSDC0_BASE = IO_PHYS + 0x01F60000, DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000, + MIPITX_BASE = IO_PHYS + 0x01E50000, + DSI0_BASE = IO_PHYS + 0x04010000, }; #endif diff --git a/src/soc/mediatek/mt8192/include/soc/dsi.h b/src/soc/mediatek/mt8192/include/soc/dsi.h new file mode 100644 index 0000000..4535d90 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dsi.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8183_DSI_H +#define SOC_MEDIATEK_MT8183_DSI_H + +#include <soc/dsi_common.h> + +/* DSI features */ +#define MTK_DSI_MIPI_RATIO_NUMERATOR 100 +#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 +#define MTK_DSI_DATA_RATE_MIN_MHZ 125 +#define MTK_DSI_HAVE_SIZE_CON 1 +#define PIXEL_STREAM_CUSTOM_HEADER 0xb + +/* MIPITX is SOC specific and cannot live in common. */ + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 reserved0[3]; + u32 lane_con; + u32 reserved1[6]; + u32 pll_pwr; + u32 pll_con0; + u32 pll_con1; + u32 pll_con2; + u32 pll_con3; + u32 pll_con4; + u32 reserved2[65]; + u32 d2_sw_ctl_en; + u32 reserved3[63]; + u32 d0_sw_ctl_en; + u32 reserved4[56]; + u32 ck_ckmode_en; + u32 reserved5[6]; + u32 ck_sw_ctl_en; + u32 reserved6[63]; + u32 d1_sw_ctl_en; + u32 reserved7[63]; + u32 d3_sw_ctl_en; +}; + +check_member(mipi_tx_regs, pll_con4, 0x3c); +check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544); +static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE; + +/* Register values */ +#define DSI_CK_CKMODE_EN BIT(0) +#define DSI_SW_CTL_EN BIT(0) +#define AD_DSI_PLL_SDM_PWR_ON BIT(0) +#define AD_DSI_PLL_SDM_ISO_EN BIT(1) + +#define RG_DSI_PLL_EN BIT(4) +#define RG_DSI_PLL_POSDIV (0x7 << 8) + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a Gerrit-Change-Number: 46574 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: soc/mediatek/mt8183: Move dsi driver to common/
by Yidi Lin (Code Review) 13 Dec '20

13 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48530 ) Change subject: soc/mediatek/mt8183: Move dsi driver to common/ ...................................................................... soc/mediatek/mt8183: Move dsi driver to common/ The mt8183 dsi driver can be shared with mt819x SoC. Move dsi.c to common/ folder and rename it to dis_v2.c to differentiate it from mt8173's dsi driver. TEST=emerge-kukuki coreboot Change-Id: I722d3e67f230ab8eb729900cdf15b922eb91a072 Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> --- R src/soc/mediatek/common/dsi_v2.c M src/soc/mediatek/mt8183/Makefile.inc 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/48530/1 diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/common/dsi_v2.c similarity index 100% rename from src/soc/mediatek/mt8183/dsi.c rename to src/soc/mediatek/common/dsi_v2.c diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index b5d5173..6309363 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -47,7 +47,7 @@ ramstage-y += emi.c ramstage-y += ../common/auxadc.c ramstage-y += ../common/ddp.c ddp.c -ramstage-y += ../common/dsi.c dsi.c +ramstage-y += ../common/dsi.c ../common/dsi_v2.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/mcu.c -- To view, visit https://review.coreboot.org/c/coreboot/+/48530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I722d3e67f230ab8eb729900cdf15b922eb91a072 Gerrit-Change-Number: 48530 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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