Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48583 )
Change subject: soc/intel: hook up new gpio device in the soc chips
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch…
File src/soc/intel/alderlake/chip.c:
https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch…
PS7, Line 202: else if (dev->path.type == DEVICE_PATH_GPIO)
: dev->ops = &soc_gpio_ops;
> Rather than adding this to every SoC, I think this can be handled within soc/intel/common/block/gpio […]
Ah thanks, that could indeed work - I tried this before but wasn't sure how we get the ops assigned to the right device then. However, I'm unsure if `assert` is a good thing here. Wouldn't that halt the machine on the first device if "halt on assertion fail" is selected? What about a simple `if`?
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6
Gerrit-Change-Number: 48583
Gerrit-PatchSet: 7
Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48589 )
Change subject: nb/intel/ironlake: Add comment about MCH scan chains
......................................................................
nb/intel/ironlake: Add comment about MCH scan chains
Change-Id: I3e60cfc1fd3352b8b0c7460503179425cc593d36
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/northbridge/intel/ironlake/raminit.c
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/48589/1
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index ecf8ef8..beb2244 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -101,6 +101,15 @@
out[1] = ret.hi;
}
+/*
+ * Ironlake memory I/O timings are located in scan chains, accessible
+ * through MCHBAR register groups. Each channel has a scan chain, and
+ * there's a global scan chain too. Each chain is broken into smaller
+ * sections of N bits, where N <= 32. Each section allows reading and
+ * writing a certain parameter. Each section contains N - 2 data bits
+ * and two additional bits: a Mask bit, and a Halt bit.
+ */
+
/* OK */
static void write_1d0(u32 val, u16 addr, int bits, int flag)
{
--
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Gerrit-Change-Id: I3e60cfc1fd3352b8b0c7460503179425cc593d36
Gerrit-Change-Number: 48589
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48520 )
Change subject: src/lib: Add Kconfig option for SPD cache in FMAP
......................................................................
src/lib: Add Kconfig option for SPD cache in FMAP
Currently, the option to cache sodimm SPD data in an FMAP region
is closely coupled to a single board (google/hatch) and requires
a custom FMAP to utilize.
Loosen this coupling by introducing a Kconfig option which adds
a correctly sized and aligned RW_SPD_CACHE region to the default FMAP.
Change the inclusion of spd_cache.c to use this new Kconfig, rather than
the board-specific one currently used. Lastly, have google/hatch select
the new Kconfig when appropriate to ensure no change in current functionality.
Test: build/boot WYVERN google/hatch variant with default FMAP, verify
FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log.
Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc
Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm>
---
M Makefile.inc
M src/lib/Kconfig
M src/lib/Makefile.inc
M src/mainboard/google/hatch/Kconfig
M util/cbfstool/default-x86.fmd
5 files changed, 24 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/48520/1
diff --git a/Makefile.inc b/Makefile.inc
index dee4a2e..f8beae0 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -976,6 +976,16 @@
FMAP_SMMSTORE_ENTRY :=
endif
+ifeq ($(CONFIG_SPD_CACHE_IN_FMAP),y)
+FMAP_SPD_CACHE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x4000)
+FMAP_SPD_CACHE_SIZE := $(call int-multiply, $(CONFIG_DIMM_MAX) $(CONFIG_DIMM_SPD_SIZE))
+FMAP_SPD_CACHE_SIZE := $(call int-align, $(FMAP_SPD_CACHE_SIZE), 0x1000)
+FMAP_SPD_CACHE_ENTRY := RW_SPD_CACHE@$(FMAP_SPD_CACHE_BASE) $(FMAP_SPD_CACHE_SIZE)
+FMAP_CURRENT_BASE := $(call int-add, $(FMAP_SPD_CACHE_BASE) $(FMAP_SPD_CACHE_SIZE))
+else
+FMAP_SPD_CACHE_ENTRY :=
+endif
+
#
# X86 FMAP region
#
@@ -1052,6 +1062,7 @@
-e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \
-e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \
-e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \
+ -e "s,##SPD_CACHE_ENTRY##,$(FMAP_SPD_CACHE_ENTRY)," \
-e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \
-e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \
$(DEFAULT_FLASHMAP) > $@.tmp
diff --git a/src/lib/Kconfig b/src/lib/Kconfig
index ab0182c..9bc0b2d 100644
--- a/src/lib/Kconfig
+++ b/src/lib/Kconfig
@@ -54,6 +54,16 @@
config SPD_READ_BY_WORD
bool
+config SPD_CACHE_IN_FMAP
+ bool
+ default n
+ help
+ Enables capability to cache SODIMM SPDs in a dedicated FMAP region
+ to speed loading of SPD data. Requires board-level implementation to
+ read/write/utilize cached SPD data.
+ When the default FMAP is used, will create a region named RW_SPD_CACHE
+ to store the cached SPD data.
+
if RAMSTAGE_LIBHWBASE
config HWBASE_DYNAMIC_MMIO
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 9e601eb..8b2ec2d 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -374,4 +374,4 @@
ramstage-y += uuid.c
-romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += spd_cache.c
+romstage-$(CONFIG_SPD_CACHE_IN_FMAP) += spd_cache.c
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 20b7103..a4e91b6 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -86,6 +86,7 @@
config ROMSTAGE_SPD_SMBUS
bool
default n
+ select SPD_CACHE_IN_FMAP
config DRIVER_TPM_SPI_BUS
default 0x1
diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd
index f0143e9..25c5096 100644
--- a/util/cbfstool/default-x86.fmd
+++ b/util/cbfstool/default-x86.fmd
@@ -12,6 +12,7 @@
##CONSOLE_ENTRY##
##MRC_CACHE_ENTRY##
##SMMSTORE_ENTRY##
+ ##SPD_CACHE_ENTRY##
FMAP@##FMAP_BASE## ##FMAP_SIZE##
COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
}
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc
Gerrit-Change-Number: 48520
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-MessageType: newchange
Hello Felix Singer, V Sowmya, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/48572
to review the following change.
Change subject: soc/intel/tigerlake: Drop unreferenced devicetree settings
......................................................................
soc/intel/tigerlake: Drop unreferenced devicetree settings
No mainboard uses these settings, nor does SoC code. Drop them.
Change-Id: I5f5da8dfcec7dd35981611830b555cab5d6af3e3
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/tigerlake/chip.h
1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/48572/1
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 5c124de..fe10d0d 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -263,10 +263,8 @@
uint8_t SmbusEnable;
/* Gfx related */
- uint8_t IgdDvmt50PreAlloc;
uint8_t SkipExtGfxScan;
- uint32_t GraphicsConfigPtr;
uint8_t Device4Enable;
/* HeciEnabled decides the state of Heci1 at end of boot
--
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