coreboot-gerrit December 2020

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Change in coreboot[master]: soc/intel/skylake: Drop unreferenced PttSwitch dt setting
by Angel Pons (Code Review) 14 Dec '20

14 Dec '20

Hello Felix Singer, V Sowmya, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48573 to review the following change. Change subject: soc/intel/skylake: Drop unreferenced PttSwitch dt setting ...................................................................... soc/intel/skylake: Drop unreferenced PttSwitch dt setting The value for this setting is not used anywhere. Drop it. Change-Id: I75f6cdec6c69b374a07519bf9058b8f6e4916307 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.h 14 files changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/48573/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 49e2964..0e408f8 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -47,7 +47,6 @@ register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 6c1144b..f8a92d8 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -43,7 +43,6 @@ register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 22935f4..430334a 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -74,7 +74,6 @@ register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index ba3f204..4f8beef 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -42,7 +42,6 @@ register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 2f230fa..4fd71d5 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -49,7 +49,6 @@ register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index ed846f6..9383642 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -39,7 +39,6 @@ register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 5117c54..65ecc8f 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -38,7 +38,6 @@ register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index b1340f8..ec55645 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -39,7 +39,6 @@ register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 2d077c2..6b58e0b 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -44,7 +44,6 @@ register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 2a916fc..8418231 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -49,7 +49,6 @@ register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index a3ee45c..8e5caf3 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -39,7 +39,6 @@ register "IoBufferOwnership" = "3" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "1" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index b796fbb..6d98772 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -53,7 +53,6 @@ register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 15ea785..8f3e0d6 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -33,7 +33,6 @@ register "IoBufferOwnership" = "0" register "SsicPortEnable" = "0" register "ScsEmmcHs400Enabled" = "0" - register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" register "HeciEnabled" = "1" register "SaGv" = "SaGv_Enabled" diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index d76c079..710c08d 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -299,8 +299,6 @@ u8 ScsEmmcHs400RxStrobeDll1; u8 ScsEmmcHs400TxDataDll; - u8 PttSwitch; - enum { Display_iGFX, Display_PEG, -- To view, visit https://review.coreboot.org/c/coreboot/+/48573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75f6cdec6c69b374a07519bf9058b8f6e4916307 Gerrit-Change-Number: 48573 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Drop unreferenced devicetree settings
by Angel Pons (Code Review) 14 Dec '20

14 Dec '20

6 15

Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Michael Niewöhner (Code Review) 14 Dec '20

14 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48583 ) Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… File src/soc/intel/alderlake/chip.c: https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… PS7, Line 202: else if (dev->path.type == DEVICE_PATH_GPIO) : dev->ops = &soc_gpio_ops; > Ah thanks, that could indeed work - I tried this before but wasn't sure how we get the ops assigned […] Uhm, wait... no. That will *not* work.... Example: chip soc/intel/whateverlake dev gpio 0 alias soc_gpio on end chip this/is/another/chip dev gpio 0 alias chip_gpio on end end chip blah/bmc use chip_gpio as gpio end chip no/idea use soc_gpio as gpio end end With your code the block gpio driver will get assigned to both gpio devices which is obviously wrong. -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Dec 2020 09:02:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Michael Niewöhner (Code Review) 14 Dec '20

14 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48583 ) Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… File src/soc/intel/alderlake/chip.c: https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… PS7, Line 202: else if (dev->path.type == DEVICE_PATH_GPIO) : dev->ops = &soc_gpio_ops; > Rather than adding this to every SoC, I think this can be handled within soc/intel/common/block/gpio […] Ah thanks, that could indeed work - I tried this before but wasn't sure how we get the ops assigned to the right device then. However, I'm unsure if `assert` is a good thing here. Wouldn't that halt the machine on the first device if "halt on assertion fail" is selected? What about a simple `if`? -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Dec 2020 08:59:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/purism/librem_cnl: move setting of FSP-M UPDs into variant.c
by Matt DeVillier (Code Review) 14 Dec '20

14 Dec '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48519 ) Change subject: mb/purism/librem_cnl: move setting of FSP-M UPDs into variant.c ...................................................................... mb/purism/librem_cnl: move setting of FSP-M UPDs into variant.c The upcoming Librem 14 variant will not use the same SATA HSIO adjustments as the Librem Mini, so move these settings into a variant-specific file. Rename existing gpio.h to variant.h and use for all variant-specific declarations; adjust references as needed. Add variant.c to Makefile. Test: build/boot Librem Mini, verify SATA functionality unchanged. Change-Id: Ie8f714cc759675c692ad6e3f20e50adad8d09d4b Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/Makefile.inc M src/mainboard/purism/librem_cnl/ramstage.c M src/mainboard/purism/librem_cnl/romstage.c M src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c D src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/gpio.h A src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/variant.h A src/mainboard/purism/librem_cnl/variants/librem_mini/variant.c 7 files changed, 33 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/48519/1 diff --git a/src/mainboard/purism/librem_cnl/Makefile.inc b/src/mainboard/purism/librem_cnl/Makefile.inc index ba157df..fa28c52 100644 --- a/src/mainboard/purism/librem_cnl/Makefile.inc +++ b/src/mainboard/purism/librem_cnl/Makefile.inc @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += variants/$(VARIANT_DIR)/variant.c + ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-y += ramstage.c diff --git a/src/mainboard/purism/librem_cnl/ramstage.c b/src/mainboard/purism/librem_cnl/ramstage.c index 56ed1b7..3936a18 100644 --- a/src/mainboard/purism/librem_cnl/ramstage.c +++ b/src/mainboard/purism/librem_cnl/ramstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/ramstage.h> -#include <variant/gpio.h> +#include <variant/variant.h> void mainboard_silicon_init_params(FSP_S_CONFIG *params) { diff --git a/src/mainboard/purism/librem_cnl/romstage.c b/src/mainboard/purism/librem_cnl/romstage.c index 3a3ca6b..a926d19 100644 --- a/src/mainboard/purism/librem_cnl/romstage.c +++ b/src/mainboard/purism/librem_cnl/romstage.c @@ -2,6 +2,7 @@ #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <variant/variant.h> static const struct cnl_mb_cfg memcfg = { @@ -50,10 +51,5 @@ { FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; cannonlake_memcfg_init(mem_cfg, &memcfg); - - /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ - mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; - mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; - mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 2; - mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; + variant_memory_init_params(mem_cfg); } diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index 8fa4ac5..270ef2d 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <variant/gpio.h> +#include <variant/variant.h> /* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/gpio.h b/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/gpio.h deleted file mode 100644 index 9094b04..0000000 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/gpio.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef VARIANT_GPIO_H -#define VARIANT_GPIO_H - -#include <soc/gpe.h> -#include <soc/gpio.h> - -const struct pad_config *variant_gpio_table(size_t *num); - -#endif diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/variant.h b/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/variant.h new file mode 100644 index 0000000..79a3241 --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/include/variant/variant.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_H +#define VARIANT_H + +#include <soc/gpe.h> +#include <soc/gpio.h> +#include <soc/romstage.h> + +const struct pad_config *variant_gpio_table(size_t *num); + +void variant_memory_init_params(FSP_M_CONFIG *mem_cfg); + +#endif diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/variant.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/variant.c new file mode 100644 index 0000000..c086e8d --- /dev/null +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/variant.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variant/variant.h> + +void variant_memory_init_params(FSP_M_CONFIG *mem_cfg) +{ + /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 2; + mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8f714cc759675c692ad6e3f20e50adad8d09d4b Gerrit-Change-Number: 48519 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: cbfs: Enable CBFS mcache on (almost) all boards
by Julius Werner (Code Review) 14 Dec '20

14 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38424 to review the following change. Change subject: cbfs: Enable CBFS mcache on (almost) all boards ...................................................................... cbfs: Enable CBFS mcache on (almost) all boards This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Only a few boards with notoriously little space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/cpu/ti/am335x/memlayout.ld M src/lib/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/google/octopus/Kconfig M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M src/soc/samsung/exynos5420/include/soc/memlayout.ld M src/soc/sifive/fu540/include/soc/memlayout.ld 25 files changed, 51 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 1c55bdb..7cf049d 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -155,6 +155,13 @@ help Increase this value if preram cbmem console is getting truncated +config CBFS_MCACHE_SIZE + hex + depends on !NO_CBFS_MCACHE + default 0x2000 + help + Increase this value if you see CBFS mcache overflow warnings + config PC80_SYSTEM bool default y if ARCH_X86 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 2e29112..52e081a 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -60,6 +60,9 @@ #if !CONFIG(NO_FMAP_CACHE) FMAP_CACHE(., FMAP_SIZE) #endif +#if !CONFIG(NO_CBFS_MCACHE) + CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) +#endif _car_ehci_dbg_info = .; /* Reserve sizeof(struct ehci_dbg_info). */ diff --git a/src/cpu/ti/am335x/memlayout.ld b/src/cpu/ti/am335x/memlayout.ld index f69a315..9bc7b75 100644 --- a/src/cpu/ti/am335x/memlayout.ld +++ b/src/cpu/ti/am335x/memlayout.ld @@ -19,7 +19,8 @@ { DRAM_START(0x40000000) BOOTBLOCK(0x402f0400, 20K) - ROMSTAGE(0x402f5400, 88K) + ROMSTAGE(0x402f5400, 80K) + CBFS_MCACHE(0x40309400, 8K) FMAP_CACHE(0x4030b400, 2K) STACK(0x4030be00, 4K) RAMSTAGE(0x80200000, 192K) diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 26bf0be..4d2bf80 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -78,7 +78,6 @@ config NO_CBFS_MCACHE bool - default y help Disables the CBFS metadata cache. This means that your platform does not need to provide a CBFS_MCACHE section in memlayout and can save diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld index aba4205..544f89f 100644 --- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -24,7 +24,8 @@ DRAM_START(0x40000000) BOOTBLOCK(0x60010000, 64K) - STACK(0x60020000, 62K) + STACK(0x60020000, 54K) + CBFS_MCACHE(0x6002D800, 8K) FMAP_CACHE(0x6002F800, 2K) ROMSTAGE(0x60030000, 128K) RAMSTAGE(0x60070000, 16M) diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 2b33cb3..de09cbb 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -43,6 +43,7 @@ BOOTBLOCK(0x00000, 64K) FMAP_CACHE(0x10000, 2K) + CBFS_MCACHE(0x10800, 8K) DRAM_START(0x60000000) STACK(0x60000000, 64K) diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld index c22d3e4..81fe7f4 100644 --- a/src/mainboard/emulation/qemu-power8/memlayout.ld +++ b/src/mainboard/emulation/qemu-power8/memlayout.ld @@ -27,5 +27,6 @@ STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) FMAP_CACHE(0x82000, 2K) + CBFS_MCACHE(0x82800, 8K) RAMSTAGE(0x100000, 16M) } diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index e53df38..7eb0f00 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -38,6 +38,7 @@ #endif PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) FMAP_CACHE(STAGES_START + 136K, 2K) + CBFS_MCACHE(STAGES_START + 138K, 8K) RAMSTAGE(STAGES_START + 200K, 16M) STACK(STAGES_START + 200K + 16M, 4K) } diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index b6e4d9d..376b9b1 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -24,7 +24,8 @@ DRAM_START(START) BOOTBLOCK(START, 64K) STACK(START + 8M, 4K) - FMAP_CACHE(START + 8M + 4K, 2K) + FMAP_CACHE(START + 12M, 2K) + CBFS_CACHE(START + 14M, 8K) /* hole at (START + 8M + 6K, 58K) */ ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 3139716..8a33b5f 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -23,6 +23,7 @@ select MAINBOARD_HAS_TPM2 select GOOGLE_SMBIOS_MAINBOARD_VERSION select NO_FMAP_CACHE + select NO_CBFS_MCACHE if BOARD_GOOGLE_BASEBOARD_OCTOPUS diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index 1a0eb15..e78aa20 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -34,7 +34,8 @@ PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K) FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K) PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) - BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) + BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 56K) + CBFS_MCACHE(BOOTROM_OFFSET + 0x2e000, 8K) VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) VBOOT2_TPM_LOG(BOOTROM_OFFSET + 0x33000, 2K) VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K) diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld index 2358c39..2d364b5 100644 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -43,7 +43,8 @@ FMAP_CACHE(0x00103800, 2K) PRERAM_CBMEM_CONSOLE(0x00104000, 12K) WATCHDOG_TOMBSTONE(0x00107000, 4) - PRERAM_CBFS_CACHE(0x00107004, 16K - 4) + PRERAM_CBFS_CACHE(0x00107004, 8K - 4) + CBFS_MCACHE(0x00109000, 8K) TIMESTAMP(0x0010B000, 4K) ROMSTAGE(0x0010C000, 92K) STACK(0x00124000, 16K) diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index 996d2ec..0d20e31 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -43,7 +43,8 @@ SRAM_L2C_START(0x00200000) OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K) - BOOTBLOCK(0x00230000, 64K) + BOOTBLOCK(0x00230000, 56K) + CBFS_MCACHE(0x0023e000, 8K) DRAM_INIT_CODE(0x00240000, 208K) PRERAM_CBFS_CACHE(0x00274000, 48K) SRAM_L2C_END(0x00280000) diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 7e2cc7a..a342f6a 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -29,7 +29,8 @@ TTB(0x40000000, 16K + 32) PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32) FMAP_CACHE(0x40005800, 2K) - PRERAM_CBFS_CACHE(0x40006000, 14K) + CBFS_MCACHE(0x40006000, 8K) + PRERAM_CBFS_CACHE(0x40008000, 6K) VBOOT2_WORK(0x40009800, 12K) VBOOT2_TPM_LOG(0x4000D800, 2K) STACK(0x4000E000, 8K) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index b7268d1..44f0153 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -30,7 +30,8 @@ SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 2K) FMAP_CACHE(0x40000800, 2K) - PRERAM_CBFS_CACHE(0x40001000, 28K) + PRERAM_CBFS_CACHE(0x40001000, 20K) + CBFS_MCACHE(0x40006000, 8K) VBOOT2_WORK(0x40008000, 12K) VBOOT2_TPM_LOG(0x4000B000, 2K) #if ENV_ARM64 diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld index 6ff1018..76685cf 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld @@ -34,7 +34,8 @@ /* This includes bootblock image, can be reused after bootblock starts */ /* UBER_SBL(0x0A0C0000, 48K) */ - PRERAM_CBFS_CACHE(0x0A0C0000, 92K) + PRERAM_CBFS_CACHE(0x0A0C0000, 84K) + CBFS_MCACHE(0x0A0ED800, 8K) FMAP_CACHE(0x0A0EF800, 2K) TTB(0x0A0F0000, 16K) diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index 595d939..6e309c0 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -38,7 +38,8 @@ QCA_SHARED_RAM(2A03F000, 4K) */ STACK(0x2A040000, 16K) - PRERAM_CBFS_CACHE(0x2A044000, 91K) + PRERAM_CBFS_CACHE(0x2A044000, 83K) + CBFS_MCACHE(0x2A059000, 8K) FMAP_CACHE(0x2A05B000, 2K) TTB_SUBTABLES(0x2A05B800, 2K) TTB(0x2A05C000, 16K) diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index dd013b5..9d92949 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -38,7 +38,8 @@ STACK(0x8C4B000, 16K) TIMESTAMP(0x8C4F000, 1K) PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) - PRERAM_CBFS_CACHE(0x8C57400, 70K) + PRERAM_CBFS_CACHE(0x8C57400, 62K) + CBFS_MCACHE(0x8C66C00, 8K) FMAP_CACHE(0x8C68C00, 2K) REGION(bsram_unused, 0x8C69400, 0xA1C00, 0x100) BSRAM_END(0x8D80000) diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index 7323119..838fda3 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -52,6 +52,7 @@ REGION(qclib_serial_log, 0x14852000, 4K, 4K) REGION(ddr_information, 0x14853000, 1K, 1K) FMAP_CACHE(0x14853400, 2K) + CBFS_MCACHE(0x14853C00, 8K) REGION(dcb, 0x14870000, 16K, 4K) REGION(pmic, 0x14874000, 44K, 4K) REGION(limits_cfg, 0x1487F000, 4K, 4K) diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index c3a3b4c..5ea3e96 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -58,7 +58,8 @@ PRERAM_CBMEM_CONSOLE(0x14836400, 32K) PRERAM_CBFS_CACHE(0x1483E400, 70K) FMAP_CACHE(0x1484FC00, 2K) - REGION(bsram_unused, 0x14850400, 0x9DB00, 0x100) + CBFS_MCACHE(0x1485400, 8K) + REGION(bsram_unused, 0x14852400, 0x9BB00, 0x100) REGION(ddr_information, 0x148EDF00, 256, 256) REGION(limits_cfg, 0x148EE000, 4K, 4K) REGION(qclib_serial_log, 0x148EF000, 4K, 4K) diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 6a44ccd..e36a8e8 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -30,6 +30,7 @@ select HAVE_LINEAR_FRAMEBUFFER select NO_BOOTBLOCK_CONSOLE select NO_FMAP_CACHE + select NO_CBFS_MCACHE if SOC_ROCKCHIP_RK3288 diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index 4e46e2d..2c7be29 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -37,11 +37,12 @@ FMAP_CACHE(0xFF8C1400, 2K) TIMESTAMP(0xFF8C1C00, 1K) /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4) - BOOTBLOCK(0xFF8D8000, 40K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 84K - 4) + BOOTBLOCK(0xFF8D7000, 40K) #endif - VBOOT2_WORK(0XFF8E2000, 12K) - TTB(0xFF8E5000, 24K) + CBFS_MCACHE(0xFF8E1000, 8K) + VBOOT2_WORK(0XFF8E3000, 12K) + TTB(0xFF8E6000, 20K) PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) STACK(0xFF8ED000, 12K) SRAM_END(0xFF8F0000) diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index 7e052f0..e97fcb0 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -31,7 +31,8 @@ ROMSTAGE(0x2030000, 128K) /* 32K hole */ TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 76K) + PRERAM_CBFS_CACHE(0x205C000, 68K) + CBFS_MCACHE(0x206D000, 8K) FMAP_CACHE(0x206F000, 2K) VBOOT2_TPM_LOG(0x206F800, 2K) VBOOT2_WORK(0x2070000, 12K) diff --git a/src/soc/samsung/exynos5420/include/soc/memlayout.ld b/src/soc/samsung/exynos5420/include/soc/memlayout.ld index ff781d2..e2e51c0 100644 --- a/src/soc/samsung/exynos5420/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5420/include/soc/memlayout.ld @@ -32,7 +32,8 @@ ROMSTAGE(0x2030000, 128K) /* 32K hole */ TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 74K) + PRERAM_CBFS_CACHE(0x205C000, 66K) + CBFS_MCACHE(0x206C800, 8K) FMAP_CACHE(0x206E800, 2K) STACK(0x206F000, 16K) /* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index 46c559c..cc4f900 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -26,7 +26,8 @@ L2LIM_START(FU540_L2LIM) BOOTBLOCK(FU540_L2LIM, 64K) CAR_STACK(FU540_L2LIM + 64K, 20K) - PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) + PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 76K, 8K) + CBFS_MCACHE(FU540_L2LIM + 84K, 8K) FMAP_CACHE(FU540_L2LIM + 92K, 2K) ROMSTAGE(FU540_L2LIM + 128K, 128K) PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) -- To view, visit https://review.coreboot.org/c/coreboot/+/38424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Gerrit-Change-Number: 38424 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

10 44

Change in coreboot[master]: soc/intel/xeon_sp: Configure DPR on all stacks
by Arthur Heymans (Code Review) 14 Dec '20

14 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46818 ) Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ...................................................................... soc/intel/xeon_sp: Configure DPR on all stacks Configure DPR to span the region between TSEG_BASE and the cbmem_top. This region was already unavailable to the OS. Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/uncore.c 3 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46818/1 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index a28fac6..bbeee1f 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -79,6 +79,7 @@ #define VMD_FUNC_NUM 0x05 #define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034 #define VTD_DEV_NUM 0x5 #define VTD_FUNC_NUM 0x0 diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 32c316d..6523b6d 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -128,6 +128,7 @@ #define HPET0_FUNC_NUM 0x00 #define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034 #define VTD_DEV_NUM 0x5 #define VTD_FUNC_NUM 0x0 diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 332b9a4..c9ffeb6 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -11,6 +11,8 @@ #include <soc/ramstage.h> #include <soc/util.h> #include <fsp/util.h> +#include <security/intel/txt/txt_platform.h> +#include <soc/pci_devs.h> struct map_entry { uint32_t reg; @@ -88,6 +90,17 @@ } } +static void configure_dpr(struct device *dev) +{ + const uintptr_t cbmem_top_mb = ALIGN_UP((uintptr_t)cbmem_top(), MiB) / MiB; + union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; + + dpr.size = dpr.top - cbmem_top_mb; + dpr.lock = 1; + dpr.epm = 1; + pci_write_config32(dev, VTD_LTDPR, dpr.raw); +} + /* * Host Memory Map: * @@ -127,6 +140,8 @@ * | MEseg (relocatable) | 32, 64, 128 or 256 MB (0x78000000 - 0x7fffffff, 0x20000) * +--------------------------+ * | Tseg (relocatable) | N x 8MB (0x70000000 - 0x77ffffff, 0x20000) + * +--------------------------+ + * | DPR | * +--------------------------+ cbmem_top * | Reserved - CBMEM | (0x6fffe000 - 0x6fffffff, 0x2000) * +--------------------------+ @@ -199,6 +214,13 @@ LOG_MEM_RESOURCE("mmio_tseg", dev, index, base_kb, size_kb); reserved_ram_resource(dev, index++, base_kb, size_kb); + /* Reserve and set up DPR */ + configure_dpr(dev); + union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; + if (dpr.size) + reserved_ram_resource(dev, index++, (dpr.top - dpr.size) << 10, dpr.size << 10); + + /* Mark region between TSEG - TOLM (eg. MESEG) as reserved */ if (mc_values[TSEG_LIMIT_REG] < mc_values[TOLM_REG]) { base_kb = ((mc_values[TSEG_LIMIT_REG] + 1) >> 10); @@ -290,3 +312,25 @@ .vendor = PCI_VENDOR_ID_INTEL, .devices = mmapvtd_ids }; + +static void vtd_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + configure_dpr(dev); +} + +static struct device_operations vtd_ops = { + .read_resources = vtd_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, +// .init = mmapvtd_init, + .ops_pci = &soc_pci_ops, +}; + +/* VTD devices on other stacks */ +static const struct pci_driver vtd_driver __pci_driver = { + .ops = &vtd_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = MMAP_VTD_STACK_CFG_REG_DEVID, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/46818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b Gerrit-Change-Number: 46818 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: [WIP] arch/x86: Combine bootblock linker scripts
by Kyösti Mälkki (Code Review) 14 Dec '20

14 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47597 ) Change subject: [WIP] arch/x86: Combine bootblock linker scripts ...................................................................... [WIP] arch/x86: Combine bootblock linker scripts Change-Id: Ie8629a89fa47a28db63ecc33c631b29ac5a77448 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- D src/arch/x86/id.ld M src/arch/x86/memlayout.ld D src/cpu/intel/fit/fit.ld D src/cpu/x86/16bit/entry16.ld M src/cpu/x86/16bit/reset16.ld 5 files changed, 24 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47597/1 diff --git a/src/arch/x86/id.ld b/src/arch/x86/id.ld deleted file mode 100644 index b69a8dc..0000000 --- a/src/arch/x86/id.ld +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -SECTIONS { - . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; - .id (.): { - KEEP(*(.id)) - } -} diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index cbf887c..b487e48 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -40,10 +40,5 @@ #if ENV_BOOTBLOCK /* Bootblock specific scripts which provide more SECTION directives. */ -#include <cpu/x86/16bit/entry16.ld> #include <cpu/x86/16bit/reset16.ld> -#include <arch/x86/id.ld> -#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) -#include <cpu/intel/fit/fit.ld> -#endif #endif /* ENV_BOOTBLOCK */ diff --git a/src/cpu/intel/fit/fit.ld b/src/cpu/intel/fit/fit.ld deleted file mode 100644 index 2e8749b..0000000 --- a/src/cpu/intel/fit/fit.ld +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -SECTIONS { - . = 0xffffffc0; - .fit_pointer (.): { - KEEP(*(.fit_pointer)) - } -} diff --git a/src/cpu/x86/16bit/entry16.ld b/src/cpu/x86/16bit/entry16.ld deleted file mode 100644 index bc456e7..0000000 --- a/src/cpu/x86/16bit/entry16.ld +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -gdtptr16_offset = gdtptr16 & 0xffff; -nullidt_offset = nullidt & 0xffff; - -/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with - * Startup IPI message without RAM. - */ -#if CONFIG(SIPI_VECTOR_IN_ROM) -_bogus = ASSERT((_start16bit & 0xfff) == 0, "Symbol _start16bit is not at 4 KiB boundary"); -ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff; -#endif diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index e00e0b4..1c7e40f 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -1,5 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +gdtptr16_offset = gdtptr16 & 0xffff; +nullidt_offset = nullidt & 0xffff; + +/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with + * Startup IPI message without RAM. + */ +#if CONFIG(SIPI_VECTOR_IN_ROM) +_bogus = ASSERT((_start16bit & 0xfff) == 0, "Symbol _start16bit is not at 4 KiB boundary"); +ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff; +#endif + /* * _ROMTOP : The top of the ROM used where we * need to put the reset vector. @@ -8,6 +19,19 @@ SECTIONS { /* Trigger an error if I have an unuseable start address */ _bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); + + . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; + .id (.): { + KEEP(*(.id)) + } + +#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) + . = 0xffffffc0; + .fit_pointer (.): { + KEEP(*(.fit_pointer)) + } +#endif + _ROMTOP = 0xfffffff0; . = _ROMTOP; .reset . : { -- To view, visit https://review.coreboot.org/c/coreboot/+/47597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8629a89fa47a28db63ecc33c631b29ac5a77448 Gerrit-Change-Number: 47597 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: nb/intel/ironlake: Add comment about MCH scan chains
by Angel Pons (Code Review) 14 Dec '20

14 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48589 ) Change subject: nb/intel/ironlake: Add comment about MCH scan chains ...................................................................... nb/intel/ironlake: Add comment about MCH scan chains Change-Id: I3e60cfc1fd3352b8b0c7460503179425cc593d36 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/48589/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index ecf8ef8..beb2244 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -101,6 +101,15 @@ out[1] = ret.hi; } +/* + * Ironlake memory I/O timings are located in scan chains, accessible + * through MCHBAR register groups. Each channel has a scan chain, and + * there's a global scan chain too. Each chain is broken into smaller + * sections of N bits, where N <= 32. Each section allows reading and + * writing a certain parameter. Each section contains N - 2 data bits + * and two additional bits: a Mask bit, and a Halt bit. + */ + /* OK */ static void write_1d0(u32 val, u16 addr, int bits, int flag) { -- To view, visit https://review.coreboot.org/c/coreboot/+/48589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e60cfc1fd3352b8b0c7460503179425cc593d36 Gerrit-Change-Number: 48589 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: nb/intel/ironlake: Remove unused constant
by Angel Pons (Code Review) 14 Dec '20

14 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48562 ) Change subject: nb/intel/ironlake: Remove unused constant ...................................................................... nb/intel/ironlake: Remove unused constant Change-Id: I0a32295e72270cde2e9bd2f8f00358b47ffd3e33 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/48562/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 05323f1..ecf8ef8 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -330,8 +330,6 @@ return ret; } -const int cached_config = 0; - #define NUM_CHANNELS 2 #define NUM_SLOTS 2 #define NUM_RANKS 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a32295e72270cde2e9bd2f8f00358b47ffd3e33 Gerrit-Change-Number: 48562 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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