coreboot-gerrit December 2020

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Change in coreboot[master]: soc/amd/common: Complete ACPIMMIO GPIO bank separation
by Kyösti Mälkki (Code Review) 14 Dec '20

14 Dec '20

Kyösti Mälkki has restored this change. ( https://review.coreboot.org/c/coreboot/+/42690 ) Change subject: soc/amd/common: Complete ACPIMMIO GPIO bank separation ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/42690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6 Gerrit-Change-Number: 42690 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: restore

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Change in coreboot[master]: soc/inte/common: Replace #if macro with if C-language constuct
by Sridhar Siricilla (Code Review) 14 Dec '20

14 Dec '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48494 ) Change subject: soc/inte/common: Replace #if macro with if C-language constuct ...................................................................... soc/inte/common: Replace #if macro with if C-language constuct This patch modifies CSE Lite driver to use 'if' C-lanugage construct instead of #if macro. TEST=Built the code for drawcia Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Iecd5cf56ecd280de920f479e174762fe6b4164b0 --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse_lite.c 2 files changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/48494/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index d3b7288..c562ea3 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -29,7 +29,6 @@ This config will enable CSE RW firmware update feature and also will be used ensure all the required configs are provided by mainboard. -if SOC_INTEL_CSE_RW_UPDATE config SOC_INTEL_CSE_FMAP_NAME string "Name of CSE Region in FMAP" default "SI_ME" @@ -75,4 +74,3 @@ This config contains the Intel CSE RW version of the blob that is provided by SOC_INTEL_CSE_RW_FILE config and the version must be set in the format major.minor.hotfix.build (ex: 14.0.40.1209). -endif diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index d173b6a..c7dac38 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -429,7 +429,6 @@ return cse_boot_to_rw(cse_bp_info); } -#if CONFIG(SOC_INTEL_CSE_RW_UPDATE) static const struct fw_version *cse_get_bp_entry_version(enum boot_partition_id bp, const struct cse_bp_info *bp_info) { @@ -772,7 +771,6 @@ return 0; } -#endif void cse_fw_sync(void *unused) { @@ -801,12 +799,12 @@ * If SOC_INTEL_CSE_RW_UPDATE is defined , then trigger CSE firmware update. The driver * triggers recovery if CSE CBFS RW metadata or CSE CBFS RW blob is not available. */ -#if CONFIG(SOC_INTEL_CSE_RW_UPDATE) - uint8_t rv; - rv = cse_fw_update(&cse_bp_info.bp_info); - if (rv) - cse_trigger_recovery(rv); -#endif + if (CONFIG(SOC_INTEL_CSE_RW_UPDATE)) { + uint8_t rv; + rv = cse_fw_update(&cse_bp_info.bp_info); + if (rv) + cse_trigger_recovery(rv); + } if (!cse_boot_to_rw(&cse_bp_info.bp_info)) { printk(BIOS_ERR, "cse_lite: Failed to switch to RW\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/48494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecd5cf56ecd280de920f479e174762fe6b4164b0 Gerrit-Change-Number: 48494 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Check sizes of CSE CBFS RW blob and CSE RW BP
by Sridhar Siricilla (Code Review) 14 Dec '20

14 Dec '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48423 ) Change subject: soc/intel/common: Check sizes of CSE CBFS RW blob and CSE RW BP ...................................................................... soc/intel/common: Check sizes of CSE CBFS RW blob and CSE RW BP The patch triggeres CrOS recovery mode if the sizes of CSE CBFS RW blob and CSE RW boot are different. TEST=Verified on drawcia. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I8be589eae905b1a54a8cf981ccd3a00bd5e733f5 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/48423/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index eb4be6e..535b9fd 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -74,6 +74,9 @@ /* CSE CBFS RW metadata is not found */ CSE_LITE_SKU_RW_METADATA_NOT_FOUND = 10, + + /* CSE CBFS RW blob layout is not correct */ + CSE_LITE_SKU_LAYOUT_MISMATCH_ERROR = 11, }; /* @@ -674,6 +677,8 @@ const void *cse_cbfs_rw, const size_t cse_blob_sz, struct region_device *target_rdev) { + if (region_device_sz(target_rdev) != cse_blob_sz) + return CSE_LITE_SKU_LAYOUT_MISMATCH_ERROR; if (!cse_erase_rw_region(target_rdev)) return CSE_LITE_SKU_FW_UPDATE_ERROR; -- To view, visit https://review.coreboot.org/c/coreboot/+/48423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8be589eae905b1a54a8cf981ccd3a00bd5e733f5 Gerrit-Change-Number: 48423 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] sb/amd/pi/hudson: Fixes for common GPIO API
by Kyösti Mälkki (Code Review) 14 Dec '20

14 Dec '20

Kyösti Mälkki has restored this change. ( https://review.coreboot.org/c/coreboot/+/42733 ) Change subject: [WIP] sb/amd/pi/hudson: Fixes for common GPIO API ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/42733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Gerrit-Change-Number: 42733 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: restore

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Change in coreboot[master]: soc/intel/braswell: Use Kconfig value for TSEG size
by Angel Pons (Code Review) 14 Dec '20

14 Dec '20

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Change in coreboot[master]: soc/intel/braswell: Clean up devicetree settings
by Angel Pons (Code Review) 14 Dec '20

14 Dec '20

Hello Felix Singer, V Sowmya, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48577 to review the following change. Change subject: soc/intel/braswell: Clean up devicetree settings ...................................................................... soc/intel/braswell: Clean up devicetree settings Remove unreferenced settings and factor out common settings. Many of these are not mainboard-specific, and all boards use the same value. Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/facebook/fbg1701/devicetree.cb M src/mainboard/google/cyan/devicetree.cb M src/mainboard/intel/strago/devicetree.cb M src/mainboard/portwell/m107/devicetree.cb M src/mainboard/protectli/vault_bsw/devicetree.cb M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/chip.h M src/soc/intel/braswell/romstage/romstage.c 8 files changed, 11 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/48577/1 diff --git a/src/mainboard/facebook/fbg1701/devicetree.cb b/src/mainboard/facebook/fbg1701/devicetree.cb index 70e950c..a340fdc 100644 --- a/src/mainboard/facebook/fbg1701/devicetree.cb +++ b/src/mainboard/facebook/fbg1701/devicetree.cb @@ -4,14 +4,9 @@ # Set the parameters for MemoryInit ############################################################ - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_64MB" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" register "PcdCaMirrorEn" = "1" @@ -37,9 +32,6 @@ register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "1" register "PcdEmmcMode" = "PCH_PCI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" register "PcdEnableSata" = "0" # Disable SATA register "Usb2Port0PerPortPeTxiSet" = "7" register "Usb2Port0PerPortTxiSet" = "5" @@ -65,9 +57,7 @@ register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index 91e9795..cec1682 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -7,14 +7,9 @@ # Set the parameters for MemoryInit ############################################################ - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" register "PcdDvfsEnable" = "1" register "PcdCaMirrorEn" = "1" @@ -40,9 +35,6 @@ register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "SVID_PMIC_CONFIG" register "PcdEmmcMode" = "PCH_PCI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" register "PcdEnableSata" = "0" # Disable SATA register "Usb2Port0PerPortPeTxiSet" = "7" register "Usb2Port0PerPortTxiSet" = "5" @@ -68,9 +60,7 @@ register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "1" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index 9133787..77b07d2 100644 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -4,14 +4,9 @@ # Set the parameters for MemoryInit ############################################################ - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" register "PcdIgdDvmt50PreAlloc" = "1" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" register "PcdCaMirrorEn" = "1" @@ -37,9 +32,6 @@ register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "SVID_PMIC_CONFIG" register "PcdEmmcMode" = "PCH_ACPI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" register "PcdEnableSata" = "0" # Disable SATA register "Usb2Port0PerPortPeTxiSet" = "7" register "Usb2Port0PerPortTxiSet" = "5" @@ -65,9 +57,7 @@ register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" diff --git a/src/mainboard/portwell/m107/devicetree.cb b/src/mainboard/portwell/m107/devicetree.cb index f68b071..d779672 100644 --- a/src/mainboard/portwell/m107/devicetree.cb +++ b/src/mainboard/portwell/m107/devicetree.cb @@ -4,14 +4,9 @@ # Set the parameters for MemoryInit ############################################################ - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" register "PcdCaMirrorEn" = "1" @@ -37,9 +32,6 @@ register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "1" register "PcdEmmcMode" = "PCH_PCI_MODE" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" register "PcdEnableSata" = "1" register "Usb2Port0PerPortPeTxiSet" = "7" register "Usb2Port0PerPortTxiSet" = "5" @@ -65,9 +57,7 @@ register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" diff --git a/src/mainboard/protectli/vault_bsw/devicetree.cb b/src/mainboard/protectli/vault_bsw/devicetree.cb index 94c083d..4b750c0 100644 --- a/src/mainboard/protectli/vault_bsw/devicetree.cb +++ b/src/mainboard/protectli/vault_bsw/devicetree.cb @@ -4,14 +4,9 @@ # Set the parameters for MemoryInit ############################################################ - register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB - - register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB" - register "PcdApertureSize" = "2" - register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" register "PcdCaMirrorEn" = "1" @@ -37,9 +32,6 @@ register "PunitPwrConfigDisable" = "1" # Disable SVID register "ChvSvidConfig" = "SVID_PMIC_CONFIG" register "PcdEmmcMode" = "PCH_DISABLED" - register "PcdUsb3ClkSsc" = "1" - register "PcdDispClkSsc" = "1" - register "PcdSataClkSsc" = "1" register "PcdEnableSata" = "1" register "Usb2Port0PerPortPeTxiSet" = "7" register "Usb2Port0PerPortTxiSet" = "6" @@ -65,9 +57,7 @@ register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" - register "PcdSataInterfaceSpeed" = "3" register "PcdPchSsicEnable" = "1" - register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 25965a0..2adda54 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -81,9 +81,9 @@ params->ChvSvidConfig = config->ChvSvidConfig; params->DptfDisable = config->DptfDisable; params->PcdEmmcMode = config->PcdEmmcMode; - params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc; - params->PcdDispClkSsc = config->PcdDispClkSsc; - params->PcdSataClkSsc = config->PcdSataClkSsc; + params->PcdUsb3ClkSsc = 1; + params->PcdDispClkSsc = 1; + params->PcdSataClkSsc = 1; params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet; params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet; @@ -115,14 +115,14 @@ params->Usb3Lane2Ow2tapgen2deemph3p5 = config->Usb3Lane2Ow2tapgen2deemph3p5; params->Usb3Lane3Ow2tapgen2deemph3p5 = config->Usb3Lane3Ow2tapgen2deemph3p5; - params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed; + params->PcdSataInterfaceSpeed = 3; params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort; params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort; - params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed; + params->PcdPcieRootPortSpeed = 0; params->PcdPchSsicEnable = config->PcdPchSsicEnable; params->PcdLogoPtr = config->PcdLogoPtr; params->PcdLogoSize = config->PcdLogoSize; - params->PcdRtcLock = config->PcdRtcLock; + params->PcdRtcLock = 0; params->PMIC_I2CBus = config->PMIC_I2CBus; params->ISPEnable = config->ISPEnable; params->ISPPciDevConfig = config->ISPPciDevConfig; diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 99a1f30..c27ee49 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -41,7 +41,6 @@ struct soc_intel_braswell_config { uint8_t enable_xdp_tap; - uint8_t clkreq_enable; enum serirq_mode serirq_mode; @@ -75,14 +74,9 @@ * The following fields come from fsp_vpd.h .aka. VpdHeader.h. * These are configuration values that are passed to FSP during MemoryInit. */ - uint16_t PcdMrcInitTsegSize; - uint16_t PcdMrcInitMmioSize; uint8_t PcdMrcInitSpdAddr1; uint8_t PcdMrcInitSpdAddr2; uint8_t PcdIgdDvmt50PreAlloc; - uint8_t PcdApertureSize; - uint8_t PcdGttSize; - uint8_t PcdLegacySegDecode; uint8_t PcdDvfsEnable; uint8_t PcdCaMirrorEn; /* Command Address Mirroring Enabled */ @@ -110,9 +104,6 @@ uint8_t ChvSvidConfig; uint8_t DptfDisable; uint8_t PcdEmmcMode; - uint8_t PcdUsb3ClkSsc; - uint8_t PcdDispClkSsc; - uint8_t PcdSataClkSsc; uint8_t Usb2Port0PerPortPeTxiSet; uint8_t Usb2Port0PerPortTxiSet; uint8_t Usb2Port0IUsbTxEmphasisEn; @@ -137,14 +128,11 @@ uint8_t Usb3Lane1Ow2tapgen2deemph3p5; uint8_t Usb3Lane2Ow2tapgen2deemph3p5; uint8_t Usb3Lane3Ow2tapgen2deemph3p5; - uint8_t PcdSataInterfaceSpeed; uint8_t PcdPchUsbSsicPort; uint8_t PcdPchUsbHsicPort; - uint8_t PcdPcieRootPortSpeed; uint8_t PcdPchSsicEnable; uint32_t PcdLogoPtr; uint32_t PcdLogoSize; - uint8_t PcdRtcLock; uint8_t PMIC_I2CBus; uint8_t ISPEnable; uint8_t ISPPciDevConfig; diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index a82a4ab..37ee93c 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -113,14 +113,14 @@ config = config_of(dev); printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); - upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0; - upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize; + upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? 8 : 0; + upd->PcdMrcInitMmioSize = 0x800; upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1; upd->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2; upd->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc; - upd->PcdApertureSize = config->PcdApertureSize; - upd->PcdGttSize = config->PcdGttSize; - upd->PcdLegacySegDecode = config->PcdLegacySegDecode; + upd->PcdApertureSize = 2; + upd->PcdGttSize = 1; + upd->PcdLegacySegDecode = 0; upd->PcdDvfsEnable = config->PcdDvfsEnable; upd->PcdCaMirrorEn = config->PcdCaMirrorEn; } -- To view, visit https://review.coreboot.org/c/coreboot/+/48577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4 Gerrit-Change-Number: 48577 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: soc/intel/skylake: Drop always-zero ProbelessTrace dt setting
by Angel Pons (Code Review) 14 Dec '20

14 Dec '20

Hello Felix Singer, V Sowmya, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48576 to review the following change. Change subject: soc/intel/skylake: Drop always-zero ProbelessTrace dt setting ...................................................................... soc/intel/skylake: Drop always-zero ProbelessTrace dt setting This seems to be a debugging option. Since unset devicetree options default to zero, drop the setting. If it is needed in the future, a user-visible Kconfig option would probably make more sense. Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/romstage/romstage.c 17 files changed, 1 insertion(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/48576/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 0e408f8..43f272e 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -32,7 +32,6 @@ register "dptf_enable" = "0" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "1" register "SataMode" = "0" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index f8a92d8..0e76de1 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -35,7 +35,6 @@ register "gen3_dec" = "0x00fc0901" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 430334a..8c31f9ac 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -64,7 +64,6 @@ register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 4f8beef..127334e 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -34,7 +34,6 @@ register "dptf_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 4fd71d5..a14e927 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -41,7 +41,6 @@ register "CmdTriStateDis" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 9383642..4bfac6d 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -31,7 +31,6 @@ register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 65ecc8f..25d720e 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -31,7 +31,6 @@ register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "DspEnable" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index ec55645..9563298 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -31,7 +31,6 @@ register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 6b58e0b..899990d 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -36,7 +36,6 @@ register "CmdTriStateDis" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 8418231..ff117c8 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -41,7 +41,6 @@ register "CmdTriStateDis" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 8e5caf3..6a37b8a 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -31,7 +31,6 @@ register "s0ix_enable" = "1" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index f6e73c6..9fedde5 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -34,7 +34,6 @@ register "dptf_enable" = "0" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index d8e68a2..abbfda4 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -31,7 +31,6 @@ register "tcc_offset" = "5" # TCC of 95C # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "DspEnable" = "0" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 6d98772..c59df40 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -41,7 +41,6 @@ register "dptf_enable" = "0" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 8f3e0d6..44b3523 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -23,7 +23,6 @@ register "dptf_enable" = "0" # FSP Configuration - register "ProbelessTrace" = "0" register "SataSalpSupport" = "0" register "SataMode" = "0" register "SataPortsEnable[0]" = "0" diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 8d93ac0..e738179 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -90,9 +90,6 @@ /* Whether to ignore VT-d support of the SKU */ int ignore_vtd; - /* Probeless Trace function */ - u8 ProbelessTrace; - /* * System Agent dynamic frequency configuration * When enabled memory will be trained at two different frequencies. diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 79fb464..c826187 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -216,7 +216,7 @@ m_cfg->MmioSize = 0x800; /* 2GB in MB */ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->ProbelessTrace = config->ProbelessTrace; + m_cfg->ProbelessTrace = 0; m_cfg->SaGv = config->SaGv; m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->RMT = config->Rmt; -- To view, visit https://review.coreboot.org/c/coreboot/+/48576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb Gerrit-Change-Number: 48576 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/intel/skylake: Drop always-zero PowerLimit4 dt setting
by Angel Pons (Code Review) 14 Dec '20

14 Dec '20

4 5

Change in coreboot[master]: soc/intel/skylake: Drop never-set DdrFreqLimit dt setting
by Angel Pons (Code Review) 14 Dec '20

14 Dec '20

3 6

Change in coreboot[master]: soc/intel/xeon_sp/skx: Hook up microcode blob
by Arthur Heymans (Code Review) 14 Dec '20

14 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48559 ) Change subject: soc/intel/xeon_sp/skx: Hook up microcode blob ...................................................................... soc/intel/xeon_sp/skx: Hook up microcode blob TESTED on ocp/tiagopass: MCU are correctly updated (installed revision reported with an out of tree patch) Change-Id: I05ddc64090424aa333848d9a0f54f21538faf94c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.inc 3 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/48559/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 2028a5e..664f960 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -57,7 +57,6 @@ select TSC_MONOTONIC_TIMER select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS - select MICROCODE_BLOB_NOT_HOOKED_UP select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_CAR select CPU_INTEL_COMMON_SMM diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 369d474..43337b5 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -2,6 +2,10 @@ if SOC_INTEL_COOPERLAKE_SP +config SOC_SPECIFIC_OPTIONS + def_bool y + select MICROCODE_BLOB_NOT_HOOKED_UP + config FSP_HEADER_PATH string "Location of FSP headers" depends on MAINBOARD_USES_FSP2_0 diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index 6ee610e..085dd20 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -29,4 +29,6 @@ CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/skx/include -I$(src)/soc/intel/xeon_sp/skx +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-04 + endif ## CONFIG_SOC_INTEL_SKYLAKE_SP -- To view, visit https://review.coreboot.org/c/coreboot/+/48559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05ddc64090424aa333848d9a0f54f21538faf94c Gerrit-Change-Number: 48559 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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