coreboot-gerrit December 2020

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Change in coreboot[master]: sb/intel/common/smbus_ops.c: Clean up read resources
by Angel Pons (Code Review) 14 Dec '20

14 Dec '20

Hello Nico Huber, Arthur Heymans, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48538 to review the following change. Change subject: sb/intel/common/smbus_ops.c: Clean up read resources ...................................................................... sb/intel/common/smbus_ops.c: Clean up read resources UNTESTED. Change-Id: I1cb05131a82ebb7c45827eff8e09e445d9c695b3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/common/smbus_ops.c 1 file changed, 2 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/48538/1 diff --git a/src/southbridge/intel/common/smbus_ops.c b/src/southbridge/intel/common/smbus_ops.c index b0ecc1a..46fc58a 100644 --- a/src/southbridge/intel/common/smbus_ops.c +++ b/src/southbridge/intel/common/smbus_ops.c @@ -67,17 +67,12 @@ void smbus_read_resources(struct device *dev) { + pci_dev_read_resources(dev); + struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = CONFIG_FIXED_SMBUS_IO_BASE; res->size = 32; res->limit = res->base + res->size - 1; res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* The memory BAR does not exist for ICH7 and earlier */ - if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) - return; - - /* Also add MMIO resource */ - res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cb05131a82ebb7c45827eff8e09e445d9c695b3 Gerrit-Change-Number: 48538 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: configs: Add a weird config for Asus P8Z77-V LX2
by Angel Pons (Code Review) 14 Dec '20

14 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48546 ) Change subject: configs: Add a weird config for Asus P8Z77-V LX2 ...................................................................... configs: Add a weird config for Asus P8Z77-V LX2 This is not meant for actual use, but to build-test several options. Please do not try to use it on real hardware. Or maybe do try. The purpose of this config is to build-test the individual options, not their combination. So, for instance, if it would be hard to keep options x, y and z build together in the future, this config shouldn't block a change but should instead be adapted, e.g. split into multiple chunks. Change-Id: I80e8fe3982025b61148e7c2b05dd0727d65ee2f4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100 1 file changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/48546/1 diff --git a/configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100 b/configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100 new file mode 100644 index 0000000..167909d --- /dev/null +++ b/configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100 @@ -0,0 +1,38 @@ +# Not meant for actual use, but rather to build-test individual options. +# If keeping this combination of options buildable becomes too hard in +# the future, then this config can be split into several smaller chunks. +# Exercises, among other things: +# + PCIe hotplug +# + Fatal assertions +# + Debug options +# + SMMSTORE +# + YABEL +# + VESA framebuffer +# + EM100 support +CONFIG_VENDOR_ASUS=y +CONFIG_CBFS_SIZE=0x200000 +CONFIG_BOARD_ASUS_P8Z77_V_LX2=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +# CONFIG_S3_VGA_ROM_RUN is not set +CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES=y +CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS=y +CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF=y +CONFIG_VGA_ROM_RUN=y +CONFIG_PCI_OPTION_ROM_RUN_YABEL=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_VBE_LINEAR_FRAMEBUFFER=y +CONFIG_PCIEXP_HOTPLUG=y +CONFIG_SMMSTORE=y +CONFIG_FATAL_ASSERTS=y +CONFIG_DEBUG_CBFS=y +CONFIG_DEBUG_RAM_SETUP=y +CONFIG_DEBUG_SMBUS=y +CONFIG_DEBUG_SMI=y +CONFIG_DEBUG_MALLOC=y +CONFIG_DEBUG_CONSOLE_INIT=y +CONFIG_DEBUG_SPI_FLASH=y +CONFIG_DEBUG_BOOT_STATE=y +CONFIG_DEBUG_ADA_CODE=y +CONFIG_HAVE_EM100_SUPPORT=y +CONFIG_EM100=y -- To view, visit https://review.coreboot.org/c/coreboot/+/48546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80e8fe3982025b61148e7c2b05dd0727d65ee2f4 Gerrit-Change-Number: 48546 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/uart: rework to use dummy device
by Nico Huber (Code Review) 14 Dec '20

14 Dec '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48385 ) Change subject: soc/intel/common/block/uart: rework to use dummy device ...................................................................... Patch Set 3: > > Well, if we rework the driver/chip modeling like you proposed, we indeed can get rid of any fake devices. Also I'm not sure if we want to mix "drivers" and "chips" then, because it's not always certain which model needs to be used. Or would we keep chips for real devices then and only use "driver" when the port is the device? I would prefer to use `chip` for actual chips. `driver` just to attach `device_operations`, like we currently match device ids to attach a driver. But we can make it what we want. If we want options for these drivers, we can add structs for those too. > > > > Where would we place driver options then? > > I would be curious to understand how the new model would work too. We could just keep things as they are, options in the chip config structs, or add options to drivers too. The latter would also need changes to core- boot's structures, the former only to `sconfig` AFAICS. -- To view, visit https://review.coreboot.org/c/coreboot/+/48385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9c9398829b52e6b0523504b862aae9aff559bc7 Gerrit-Change-Number: 48385 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Dec 2020 20:54:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] sb/amd/pi/hudson: Fixes for common GPIO API
by Felix Held (Code Review) 14 Dec '20

14 Dec '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42733 ) Change subject: [WIP] sb/amd/pi/hudson: Fixes for common GPIO API ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/42733/8/src/southbridge/amd/pi/hud… File src/southbridge/amd/pi/hudson/soc/smi.h: PS8: for everything apart from the defines soc/amd/common/block/include/amdblocks/smi.h should probably be used instead -- To view, visit https://review.coreboot.org/c/coreboot/+/42733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Gerrit-Change-Number: 42733 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 14 Dec 2020 20:26:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: Enable CNVi Bluetooth for UP4
by Bora Guvendik (Code Review) 14 Dec '20

14 Dec '20

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48484 ) Change subject: mb/intel/tglrvp: Enable CNVi Bluetooth for UP4 ...................................................................... mb/intel/tglrvp: Enable CNVi Bluetooth for UP4 Turn on CNVi Bluetooth for UP4 in devicetree. BUG=none TEST=Boot to OS, check BT enumuration. Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I6a3ec7014c41713697e0fcc90e28bc7bbe6aa1e0 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/48484/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 56c3afa..70833ee 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -217,7 +217,7 @@ device pci 0e.0 off end # VMD 0x9A0B # From PCH EDS(576591) - device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 device pci 10.6 off end # THC0 0xA0D0 device pci 10.7 off end # THC1 0xA0D1 device pci 12.0 on # SensorHUB 0xA0FC -- To view, visit https://review.coreboot.org/c/coreboot/+/48484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a3ec7014c41713697e0fcc90e28bc7bbe6aa1e0 Gerrit-Change-Number: 48484 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/prodrive/hermes: Update PCIe slots in devicetree
by Patrick Rudolph (Code Review) 14 Dec '20

14 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47239 ) Change subject: mb/prodrive/hermes: Update PCIe slots in devicetree ...................................................................... mb/prodrive/hermes: Update PCIe slots in devicetree * Drop PcieRpSlotImplemented on internal slots * Add PCIe port 15 that connected to CNVi/M2.E Change-Id: Iaa05affa760b447fc1725e674b12366684a63720 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb 1 file changed, 9 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/47239/1 diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 2c0c26a..56348c2 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -187,30 +187,21 @@ smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X" register "PcieRpSlotImplemented[0]" = "1" end - device pci 1c.4 on # PCIe root port 5 (PHY 3) - register "PcieRpSlotImplemented[4]" = "1" - end - device pci 1c.5 on # PCIe root port 6 (PHY 4) - register "PcieRpSlotImplemented[5]" = "1" - end - device pci 1c.6 on # PCIe root port 7 (PHY 2) - register "PcieRpSlotImplemented[6]" = "1" - end - device pci 1c.7 on # PCIe root port 8 (PHY 1) - register "PcieRpSlotImplemented[7]" = "1" - end + device pci 1c.4 on end # PCIe root port 5 (PHY 3) + device pci 1c.5 on end # PCIe root port 6 (PHY 4) + device pci 1c.6 on end # PCIe root port 7 (PHY 2) + device pci 1c.7 on end # PCIe root port 8 (PHY 1) device pci 1d.0 on # PCIe root port 9 (M2 M) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X" register "PcieRpSlotImplemented[8]" = "1" end - device pci 1d.5 on # PCIe root port 14 (PHY 0) - register "PcieRpSlotImplemented[13]" = "1" + device pci 1d.5 on end # PCIe root port 14 (PHY 0) + device pci 1d.6 on end # PCIe root port 15 (BMC) + device pci 1d.7 on # PCIe root port 16 (M.2 E/CNVi) + # Disabled when CNVi is present + register "PcieRpSlotImplemented[15]" = "1" end - device pci 1d.6 on # PCIe root port 15 (BMC) - register "PcieRpSlotImplemented[14]" = "1" - end - device pci 1e.0 on end # UART #0 device pci 1e.1 on end # UART #1 device pci 1e.2 off end # GSPI #0 -- To view, visit https://review.coreboot.org/c/coreboot/+/47239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa05affa760b447fc1725e674b12366684a63720 Gerrit-Change-Number: 47239 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
by Furquan Shaikh (Code Review) 14 Dec '20

14 Dec '20

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48281 ) Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage ...................................................................... soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage This patch sets up cse_fw_sync() call in the romstage. The cse_fw_sync() must be called after DRAM initialization. BUG=b:174694480 Test=Verified on Tigerlake platform Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48281 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/tigerlake/romstage/romstage.c 1 file changed, 12 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index 1fa6c2d..8b7dc23 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -135,6 +135,17 @@ s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); - if (!s3wake) + if (!s3wake) { + /* + * cse_fw_sync() must be called after DRAM initialization as + * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) + * is expected to be executed after DRAM initialization. + */ + + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) + cse_fw_sync(); + save_dimm_info(); + } + } -- To view, visit https://review.coreboot.org/c/coreboot/+/48281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856 Gerrit-Change-Number: 48281 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the...
by Furquan Shaikh (Code Review) 14 Dec '20

14 Dec '20

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48280 ) Change subject: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage ...................................................................... soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage This patch sets up cse_fw_sync() call in the romstage.The cse_fw_sync() must be called after DRAM initialization. BUG=b:174694480 Test=Verified on Drawlet Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48280 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/jasperlake/romstage/romstage.c 1 file changed, 11 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index 1fa6c2d..6d34b43 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -135,6 +135,16 @@ s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); - if (!s3wake) + if (!s3wake) { + + /* + * cse_fw_sync() must be called after DRAM initialization as + * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) + * is expected to be executed after DRAM initialization. + */ + if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) + cse_fw_sync(); + save_dimm_info(); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a Gerrit-Change-Number: 48280 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Move CSE Lite driver functionality into romstage
by Furquan Shaikh (Code Review) 14 Dec '20

14 Dec '20

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48279 ) Change subject: soc/intel/common: Move CSE Lite driver functionality into romstage ...................................................................... soc/intel/common: Move CSE Lite driver functionality into romstage The patch sets up the CSE Lite driver in the romstage instead of ramstage. With this change, CSE Lite driver sets CSE's boot partition and triggers CSE FW update in the romstage. The cse_fw_sync() must be called after DRAM initialization as HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) is expected to be executed after DRAM initialization. With this change, it improves the cold boot time by ~154ms. Test=Verified on JSL and TGL platforms BUG=b:174694480 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48279 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 3 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index d2f94a4..30eb78e 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,7 +1,7 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c -ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c +romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c ifeq ($(CONFIG_SOC_INTEL_CSE_RW_UPDATE),y) diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 1d261ea..036a50a 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -775,7 +775,7 @@ return 0; } -void cse_fw_sync(void *unused) +void cse_fw_sync(void) { static struct get_bp_info_rsp cse_bp_info; @@ -814,5 +814,3 @@ cse_trigger_recovery(CSE_LITE_SKU_RW_SWITCH_ERROR); } } - -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 64ee0dd..1a95e2e 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -236,7 +236,7 @@ * In software triggered recovery mode, the function allows CSE to boot from whatever is * currently selected partition. */ -void cse_fw_sync(void *unused); +void cse_fw_sync(void); /* Perform a board-specific reset sequence for CSE RO<->RW jump */ void cse_board_reset(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/48279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73 Gerrit-Change-Number: 48279 Gerrit-PatchSet: 8 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
by Furquan Shaikh (Code Review) 14 Dec '20

14 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48281 ) Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856 Gerrit-Change-Number: 48281 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Dec 2020 17:57:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2020