coreboot-gerrit December 2020

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Change in em100[master]: Support 4-byte address mode in SPI traces
by Stefan Reinauer (Code Review) 14 Dec '20

14 Dec '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/48553 ) Change subject: Support 4-byte address mode in SPI traces ...................................................................... Support 4-byte address mode in SPI traces - Track address mode globally, so we can access the user presets when reading SPI traces. - Enable address mode switching based on the SPI opcodes 0xB7 / 0xE9 - Read additional address byte when appropriate and skip it in the data stream - Skip trace packets without valid data Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: Iec9f36356eb7e612a909855cda85dc0ce1b5adc0 --- M em100.c M em100.h M trace.c 3 files changed, 23 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/53/48553/1 diff --git a/em100.c b/em100.c index c4b6c01..ca6e683 100644 --- a/em100.c +++ b/em100.c @@ -29,6 +29,7 @@ TFILE *configs; char *database_version; int debug = 0; +int address_mode = 3; volatile sig_atomic_t exit_requested = 0; static struct em100 em100_state; @@ -835,7 +836,6 @@ int compatibility = 0; int bus = 0, device = 0; int firmware_is_dpfw = 0; - int address_mode = 0; unsigned int serial_number = 0; unsigned long address_offset = 0; unsigned int spi_start_address = 0; diff --git a/em100.h b/em100.h index d49339b..ecb74d2 100644 --- a/em100.h +++ b/em100.h @@ -197,6 +197,7 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) char *get_em100_file(const char *name); extern int debug; +extern int address_mode; extern volatile sig_atomic_t exit_requested; /* Chips */ diff --git a/trace.c b/trace.c index 0c6cdfd..108691b 100644 --- a/trace.c +++ b/trace.c @@ -128,6 +128,7 @@ {"exit 4-byte address mode", 0xe9, 0, 0}, {"enter quad i/o mode", 0x35, 0, 0}, {"exit quad i/o mode", 0xf5, 0, 0}, + {"read SFDP Table", 0x5a, 1, 0}, {"unknown command", 0xff, 0, 0} }; @@ -178,6 +179,11 @@ unsigned int j = additional_pad_bytes; additional_pad_bytes = 0; unsigned char cmd = data[2 + i*8]; + + if (cmd == 0x00) { + /* packet without valid data */ + continue; + } if (cmd == 0xff) { /* timestamp */ timestamp = data[2 + i*8 + 2]; @@ -201,16 +207,27 @@ if (counter == 0) start_timestamp = timestamp; + /* Special commands */ + switch (spi_command) { + case 0xb7: + address_mode = 4; + break; + case 0xe9: + address_mode = 3; + break; + } + /* set up address if used by this command*/ if (!spi_cmd_vals->uses_address) { j = 1; /* skip command byte */ } else { - address = (data[i * 8 + 5] << 16) + - (data[i * 8 + 6] << 8) + - data[i * 8 + 7]; + if (address_mode == 3) + address = (data[i * 8 + 5] << 16) + (data[i * 8 + 6] << 8) + data[i * 8 + 7]; + else + address = (data[i * 8 + 5] << 24) + (data[i * 8 + 6] << 16) + (data[i * 8 + 7] << 8) + data[i * 8 + 8]; /* skip command, address bytes, and padding */ - j = 4 + spi_cmd_vals->pad_bytes; + j = 1 + address_mode + spi_cmd_vals->pad_bytes; if (j > MAX_TRACE_BLOCKLENGTH) { additional_pad_bytes = j - MAX_TRACE_BLOCKLENGTH; -- To view, visit https://review.coreboot.org/c/em100/+/48553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Iec9f36356eb7e612a909855cda85dc0ce1b5adc0 Gerrit-Change-Number: 48553 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Furquan Shaikh (Code Review) 14 Dec '20

14 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48583 ) Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… File src/soc/intel/alderlake/chip.c: https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… PS7, Line 202: else if (dev->path.type == DEVICE_PATH_GPIO) : dev->ops = &soc_gpio_ops; > > > > It also relieves each SoC from duplicating the same code to set up GPIO device ops. […] I still think that it would be beneficial to have a separate chip for the GPIO device. Anyways, we can start with this and see how the use cases develop. -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 15 Dec 2020 00:57:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Michael Niewöhner (Code Review) 14 Dec '20

14 Dec '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48583 to look at the new patch set (#10). Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... soc/intel: hook up new gpio device in the soc chips This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/chip.c M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/common/block/gpio/Makefile.inc M src/soc/intel/common/block/gpio/gpio.c A src/soc/intel/common/block/gpio/gpio_dev.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/elkhartlake/chip.c M src/soc/intel/icelake/chip.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/skx/chip.c 14 files changed, 71 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48583/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Michael Niewöhner (Code Review) 14 Dec '20

14 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48583 ) Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… File src/soc/intel/alderlake/chip.c: https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… PS7, Line 202: else if (dev->path.type == DEVICE_PATH_GPIO) : dev->ops = &soc_gpio_ops; > > > It also relieves each SoC from duplicating the same code to set up GPIO device ops. > > Nico's solution does, too > > You have to add this to every SoC chip.c as done in the latest patchset which wouldn't be required if the GPIO block had its own chip: > > else if (dev->path.type == DEVICE_PATH_GPIO) > block_gpio_enable(dev); > Well, a chip would then require such construct: chip soc/outel/whateverlake chip soc/intel/common/block/gpio device generic 0 alias soc_gpio on end end chip drivers/iamachip chip drivers/iamachip/gpio device generic 0 alias whereever_gpio on end end end chip drivers/ipmi use whereever_gpio as gpio end chip drivers/sample use soc_gpio as gpio end end ... instead of: chip soc/outel/whateverlake device gpio 0 alias soc_gpio on end chip drivers/iamachip device gpio 0 alias whereever_gpio on end end chip drivers/ipmi use whereever_gpio as gpio end chip drivers/sample use soc_gpio as gpio end end > > Huh? block gpio is common code without any soc specific options, isn't it? > > Yes, it is. What I meant is if in the future, the common code required any configs to be set by mainboard or specific SoC, then it can have its own soc_intel_common_block_gpio_config {} rather than requiring each SoC config to add these. Then maybe let's revisit that, when it's actually required? -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 15 Dec 2020 00:55:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Michael Niewöhner (Code Review) 14 Dec '20

14 Dec '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48583 to look at the new patch set (#9). Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... soc/intel: hook up new gpio device in the soc chips This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/chip.c M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/common/block/gpio/Makefile.inc M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/elkhartlake/chip.c M src/soc/intel/icelake/chip.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/skx/chip.c 13 files changed, 43 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48583/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Furquan Shaikh (Code Review) 14 Dec '20

14 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48583 ) Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… File src/soc/intel/alderlake/chip.c: https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… PS7, Line 202: else if (dev->path.type == DEVICE_PATH_GPIO) : dev->ops = &soc_gpio_ops; > > It also relieves each SoC from duplicating the same code to set up GPIO device ops. > Nico's solution does, too You have to add this to every SoC chip.c as done in the latest patchset which wouldn't be required if the GPIO block had its own chip: else if (dev->path.type == DEVICE_PATH_GPIO) block_gpio_enable(dev); > Huh? block gpio is common code without any soc specific options, isn't it? Yes, it is. What I meant is if in the future, the common code required any configs to be set by mainboard or specific SoC, then it can have its own soc_intel_common_block_gpio_config {} rather than requiring each SoC config to add these. -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 15 Dec 2020 00:35:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/dnv_ns: hook up new gpio device operations
by Michael Niewöhner (Code Review) 14 Dec '20

14 Dec '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Mariusz Szafrański, Paul Menzel, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48618 to look at the new patch set (#2). Change subject: soc/intel/dnv_ns: hook up new gpio device operations ...................................................................... soc/intel/dnv_ns: hook up new gpio device operations This change hooks up the new gpio operations in DNV-NS. Change-Id: I2179e641153da7230467c5766e4ded58fdb90292 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/denverton_ns/chip.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/48618/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2179e641153da7230467c5766e4ded58fdb90292 Gerrit-Change-Number: 48618 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Michael Niewöhner (Code Review) 14 Dec '20

14 Dec '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48583 to look at the new patch set (#8). Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... soc/intel: hook up new gpio device in the soc chips This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/chip.c M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/elkhartlake/chip.c M src/soc/intel/icelake/chip.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/skx/chip.c 12 files changed, 62 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48583/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: device + util/sconfig: introduce new device `gpio`
by Michael Niewöhner (Code Review) 14 Dec '20

14 Dec '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Aaron Durbin, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48582 to look at the new patch set (#5). Change subject: device + util/sconfig: introduce new device `gpio` ...................................................................... device + util/sconfig: introduce new device `gpio` Introduce a new device `gpio` that is going to be used for generic abstraction of gpio operations in the devicetree. This change adds the nev device type to sconfig and adds generic gpio operations to the `device_operations` struct. Change-Id: Ic4572ad8b37bd1afd2fb213b2c67fb8aec536786 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/device/device_const.c M src/device/device_util.c M src/include/device/device.h A src/include/device/gpio.h M src/include/device/path.h M util/sconfig/lex.yy.c_shipped M util/sconfig/main.c M util/sconfig/sconfig.l M util/sconfig/sconfig.tab.c_shipped M util/sconfig/sconfig.tab.h_shipped M util/sconfig/sconfig.y 11 files changed, 335 insertions(+), 390 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/48582/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/48582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4572ad8b37bd1afd2fb213b2c67fb8aec536786 Gerrit-Change-Number: 48582 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Michael Niewöhner (Code Review) 14 Dec '20

14 Dec '20

1 0

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coreboot-gerrit December 2020