coreboot-gerrit December 2020

coreboot-gerrit@coreboot.org

1 participants
3165 discussions

Change in coreboot[master]: soc/amd/common: Redo ACPIMMIO_BASE and _BANK
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42894 ) Change subject: soc/amd/common: Redo ACPIMMIO_BASE and _BANK ...................................................................... soc/amd/common: Redo ACPIMMIO_BASE and _BANK Change-Id: I31f2d04d9fc8bdd9e270fb3cb48d71f215999a50 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h M src/soc/amd/common/block/smbus/sm.c M src/soc/amd/common/block/smbus/smbus.c M src/soc/amd/picasso/acpi/aoac.asl M src/soc/amd/stoneyridge/smbus_spd.c 6 files changed, 16 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/42894/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 5084672..8acd27f 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -5,12 +5,9 @@ #include <amdblocks/acpimmio_map.h> #include <amdblocks/acpimmio.h> -#define ACPI_BANK_PTR(bank) \ - (void *)(uintptr_t)(AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK) - #if CONSTANT_ACPIMMIO_BASE_ADDRESS #define DECLARE_ACPIMMIO(ptr, bank) \ - uint8_t *const ptr = ACPI_BANK_PTR(bank) + uint8_t *const ptr = (void *)(uintptr_t)ACPIMMIO_BASE(bank) #else #define DECLARE_ACPIMMIO(ptr, bank) uint8_t *ptr #endif diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 758a5562..e5caefc 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -95,13 +95,10 @@ #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 #ifdef __ACPI__ - -/* ASL fails on additions. */ +/* ASL MemoryFixed32() fails if these are additions. */ #define ACPIMMIO_MISC_BASE 0xfed80e00 #define ACPIMMIO_GPIO0_BASE 0xfed81500 -#define ACPIMMIO_AOAC_BASE 0xfed81e00 - -#else +#endif #define ACPIMMIO_SM_PCI_BANK 0x0000 #define ACPIMMIO_GPIO_100_BANK 0x0100 @@ -126,10 +123,6 @@ #define ACPIMMIO_ACDCTMR_BANK 0x1d00 #define ACPIMMIO_AOAC_BANK 0x1e00 -/* FIXME: Passing host base for SMBUS is not long-term solution. */ -#define ACPIMMIO_ASF_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ASF_BANK) -#define ACPIMMIO_SMBUS_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_SMBUS_BANK) - -#endif +#define ACPIMMIO_BASE(bank) (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK) #endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */ diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index c5c1ed8..f540e97 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -27,9 +27,9 @@ pbus = get_pbus_smbus(dev); res = find_resource(pbus->dev, 0x90); if (res->base == SMB_BASE_ADDR) - return ACPIMMIO_SMBUS_BASE; + return ACPIMMIO_BASE(SMBUS); - return ACPIMMIO_ASF_BASE; + return ACPIMMIO_BASE(ASF); } static int lsmbus_recv_byte(struct device *dev) diff --git a/src/soc/amd/common/block/smbus/smbus.c b/src/soc/amd/common/block/smbus/smbus.c index e304483..fe1862f 100644 --- a/src/soc/amd/common/block/smbus/smbus.c +++ b/src/soc/amd/common/block/smbus/smbus.c @@ -13,12 +13,15 @@ */ #define SMBUS_TIMEOUT (100 * 1000 * 10) +/* FIXME: Passing host base for SMBUS is not long-term solution. + It is possible to have multiple buses behind same host. */ + static u8 controller_read8(uintptr_t base, u8 reg) { switch (base) { - case ACPIMMIO_SMBUS_BASE: + case ACPIMMIO_BASE(SMBUS): return smbus_read8(reg); - case ACPIMMIO_ASF_BASE: + case ACPIMMIO_BASE(ASF): return asf_read8(reg); default: printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n", @@ -30,10 +33,10 @@ static void controller_write8(uintptr_t base, u8 reg, u8 val) { switch (base) { - case ACPIMMIO_SMBUS_BASE: + case ACPIMMIO_BASE(SMBUS): smbus_write8(reg, val); break; - case ACPIMMIO_ASF_BASE: + case ACPIMMIO_BASE(ASF): asf_write8(reg, val); break; default: diff --git a/src/soc/amd/picasso/acpi/aoac.asl b/src/soc/amd/picasso/acpi/aoac.asl index f26f85f..1b9e255 100644 --- a/src/soc/amd/picasso/acpi/aoac.asl +++ b/src/soc/amd/picasso/acpi/aoac.asl @@ -4,7 +4,7 @@ #define AOAC_DEVICE(DEV_NAME, DEV_ID, SX) \ PowerResource(DEV_NAME, SX, 0) { \ - OperationRegion (AOAC, SystemMemory, ACPIMMIO_AOAC_BASE + 0x40 + (DEV_ID << 1), 2) \ + OperationRegion (AOAC, SystemMemory, ACPIMMIO_BASE(AOAC) + 0x40 + (DEV_ID << 1), 2) \ Field (AOAC, ByteAcc, NoLock, Preserve) { \ /* \ * Target Device State \ diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index 7c54d8d..38aac76 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -34,7 +34,7 @@ dev_addr = (SmbusSlaveAddress >> 1); /* Read the first SPD byte */ - error = do_smbus_read_byte(ACPIMMIO_SMBUS_BASE, dev_addr, 0); + error = do_smbus_read_byte(ACPIMMIO_BASE(SMBUS), dev_addr, 0); if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; @@ -44,7 +44,7 @@ /* Read the remaining SPD bytes using do_smbus_recv_byte for speed */ for (index = 1 ; index < count ; index++) { - error = do_smbus_recv_byte(ACPIMMIO_SMBUS_BASE, dev_addr); + error = do_smbus_recv_byte(ACPIMMIO_BASE(SMBUS), dev_addr); if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; -- To view, visit https://review.coreboot.org/c/coreboot/+/42894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f2d04d9fc8bdd9e270fb3cb48d71f215999a50 Gerrit-Change-Number: 42894 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: [WIP] soc/amd/common: Avoid MMIO aliasing on SMBus
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42074 ) Change subject: [WIP] soc/amd/common: Avoid MMIO aliasing on SMBus ...................................................................... [WIP] soc/amd/common: Avoid MMIO aliasing on SMBus Change-Id: I5e0ebd7609c5c83d0e443ffba74dae68017d3ebc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/smbus/smbus.c M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 20 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/42074/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index b95a347..ac48538 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -250,46 +250,6 @@ write32(acpimmio_acpi + reg, value); } -static inline uint8_t asf_read8(uint8_t reg) -{ - return read8(acpimmio_asf + reg); -} - -static inline uint16_t asf_read16(uint8_t reg) -{ - return read16(acpimmio_asf + reg); -} - -static inline void asf_write8(uint8_t reg, uint8_t value) -{ - write8(acpimmio_asf + reg, value); -} - -static inline void asf_write16(uint8_t reg, uint16_t value) -{ - write16(acpimmio_asf + reg, value); -} - -static inline uint8_t smbus_read8(uint8_t reg) -{ - return read8(acpimmio_smbus + reg); -} - -static inline uint16_t smbus_read16(uint8_t reg) -{ - return read16(acpimmio_smbus + reg); -} - -static inline void smbus_write8(uint8_t reg, uint8_t value) -{ - write8(acpimmio_smbus + reg, value); -} - -static inline void smbus_write16(uint8_t reg, uint16_t value) -{ - write16(acpimmio_smbus + reg, value); -} - static inline uint8_t iomux_read8(uint8_t reg) { return read8(acpimmio_iomux + reg); diff --git a/src/soc/amd/common/block/smbus/smbus.c b/src/soc/amd/common/block/smbus/smbus.c index b5db56b..f8bab62 100644 --- a/src/soc/amd/common/block/smbus/smbus.c +++ b/src/soc/amd/common/block/smbus/smbus.c @@ -3,7 +3,7 @@ #include <stdint.h> #include <console/console.h> #include <device/smbus_host.h> -#include <amdblocks/acpimmio.h> +#include <amdblocks/acpimmio_map.h> #include <soc/southbridge.h> /* @@ -12,37 +12,31 @@ */ #define SMBUS_TIMEOUT (100 * 1000 * 10) -static u8 controller_read8(uintptr_t base, u8 reg) +union reg_bank { + uint8_t reg8[0x100]; + uint16_t reg16[0x100 / sizeof(uint16_t)]; +}; + +static __always_inline u8 controller_read8(const u32 base, const u8 reg) { - switch (base) { - case ACPIMMIO_SMBUS_BASE: - return smbus_read8(reg); - case ACPIMMIO_ASF_BASE: - return asf_read8(reg); - default: - printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n", - base); - } - return 0xff; + volatile union reg_bank *controller = (void *)(uintptr_t)base; + return controller->reg8[reg]; } -static void controller_write8(uintptr_t base, u8 reg, u8 val) +static __always_inline void controller_write8(const u32 base, const u8 reg, const u8 val) { - switch (base) { - case ACPIMMIO_SMBUS_BASE: - smbus_write8(reg, val); - break; - case ACPIMMIO_ASF_BASE: - asf_write8(reg, val); - break; - default: - printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%lx\n", - base); - } + volatile union reg_bank *controller = (void *)(uintptr_t)base; + controller->reg8[reg] = val; } static int smbus_wait_until_ready(uintptr_t mmio) { + if ((mmio != (uintptr_t)acpimmio_smbus) && + (mmio != (uintptr_t)acpimmio_asf)) { + printk(BIOS_ERR, "Invalid SMBus or ASF base %#zx\n", mmio); + return -1; + } + u32 loops; loops = SMBUS_TIMEOUT; do { diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index e90fe1b..7bdc4a4 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -366,6 +366,7 @@ static void fch_smbus_init(void) { +#if 0 /* 400 kHz smbus speed. */ const uint8_t smbus_speed = (66000000 / (400000 * 4)); @@ -376,6 +377,7 @@ smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); +#endif } /* Before console init */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e0ebd7609c5c83d0e443ffba74dae68017d3ebc Gerrit-Change-Number: 42074 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 26

Change in coreboot[master]: soc/intel/xeon_sp: Fix final MTRR usage
by Arthur Heymans (Code Review) 15 Dec '20

15 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47868 ) Change subject: soc/intel/xeon_sp: Fix final MTRR usage ...................................................................... soc/intel/xeon_sp: Fix final MTRR usage The region top_of_ram -> cbmem_top is used by FSP, but is also just regular DRAM. Marking it as such improves the final MTRR solution a lot and fixes MTRR starvation depending on the setup. Change-Id: I19ff7cf2d699b4cc34caccd91cafd6a284d699d3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/uncore.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/47868/1 diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 15a9f0f..94aabab 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -182,6 +182,11 @@ LOG_MEM_RESOURCE("low_ram", dev, index, base_kb, size_kb); ram_resource(dev, index++, base_kb, size_kb); + /* fsp_mem_base -> cbmem_top */ + base_kb = top_of_ram / KiB; + size_kb = ((uintptr_t)cbmem_top() - top_of_ram) / KiB; + reserved_ram_resource(dev, index++, base_kb, size_kb); + /* * FSP meomoy, CBMem regions are already added as reserved * Add TSEG and MESEG Regions as reserved memory -- To view, visit https://review.coreboot.org/c/coreboot/+/47868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19ff7cf2d699b4cc34caccd91cafd6a284d699d3 Gerrit-Change-Number: 47868 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: soc/amd/common/bloc: Code to digest FSP PerformanceLib timestamps
by Matt Papageorge (Code Review) 15 Dec '20

15 Dec '20

Matt Papageorge has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48256 ) Change subject: soc/amd/common/bloc: Code to digest FSP PerformanceLib timestamps ...................................................................... soc/amd/common/bloc: Code to digest FSP PerformanceLib timestamps The PEI PerformanceLib is capable of collecting timestamps from anywhere during FSP execution and store that data within GUID HOBs. This change adds code that can understand the HOBs. Long term plan is to add this data to cbmem as well as add more measurement checkpoints within FSP. Currently just the EDK defaults are generated. Note that you need a corresponding FSP change to trigger these HOBs to be generated. BUG=todo TEST=Verify output matches what can be dumped within FSP Change-Id: Ic064b9cb205154662280a3b2a5bc02d33a779fc7 Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com> --- M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/include/fsp/util.h A src/soc/amd/common/block/fsp_stats/Kconfig A src/soc/amd/common/block/fsp_stats/Makefile.inc A src/soc/amd/common/block/fsp_stats/fsp_stats.c 5 files changed, 248 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/48256/1 diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 60ab7cb..ece3037 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -183,15 +183,16 @@ die("9.1: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); } -const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size) +const void *fsp_find_extension_hob_inst_by_guid(const uint8_t *guid, size_t *size, const uint8_t instance_num) { const uint8_t *hob_guid; const struct hob_header *hob = fsp_get_hob_list(); + uint8_t hob_num; if (!hob) return NULL; - for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; + for (hob_num = 0; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) { if (hob->type != HOB_TYPE_GUID_EXTENSION) @@ -199,14 +200,24 @@ hob_guid = hob_header_to_struct(hob); if (fsp_guid_compare(hob_guid, guid)) { - *size = hob->length - (HOB_HEADER_LEN + 16); - return hob_header_to_extension_hob(hob); + if (hob_num == instance_num) { + *size = hob->length - (HOB_HEADER_LEN + 16); + return hob_header_to_extension_hob(hob); + } + hob_num++; } } return NULL; } +const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size) +{ + return fsp_find_extension_hob_inst_by_guid (guid, size, 0); +} + + + static void display_fsp_version_info_hob(const void *hob) { #if CONFIG(DISPLAY_FSP_VERSION_INFO) diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index f154a34..ac1374c 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -77,6 +77,7 @@ const void *fsp_get_hob_list(void); void *fsp_get_hob_list_ptr(void); const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size); +const void *fsp_find_extension_hob_inst_by_guid(const uint8_t *guid, size_t *size, const uint8_t instance_num); const void *fsp_find_nv_storage_data(size_t *size); enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); int fsp_find_range_hob(struct range_entry *re, const uint8_t guid[16]); diff --git a/src/soc/amd/common/block/fsp_stats/Kconfig b/src/soc/amd/common/block/fsp_stats/Kconfig new file mode 100644 index 0000000..5001cd9 --- /dev/null +++ b/src/soc/amd/common/block/fsp_stats/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_FSP_STATS + bool + default y + help + Parse FSP PerfromanceLib statistics diff --git a/src/soc/amd/common/block/fsp_stats/Makefile.inc b/src/soc/amd/common/block/fsp_stats/Makefile.inc new file mode 100644 index 0000000..c6ada9b --- /dev/null +++ b/src/soc/amd/common/block/fsp_stats/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_FSP_STATS) += fsp_stats.c diff --git a/src/soc/amd/common/block/fsp_stats/fsp_stats.c b/src/soc/amd/common/block/fsp_stats/fsp_stats.c new file mode 100644 index 0000000..ec4df1f --- /dev/null +++ b/src/soc/amd/common/block/fsp_stats/fsp_stats.c @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <lib.h> +#include <stdio.h> +#include <stdlib.h> +#include <stddef.h> +#include <stdint.h> +#include <fsp/util.h> +#include <bootstate.h> +#include <console/console.h> +#include <cbmem.h> + +#define AMD_FSP_PERFORMANCELIB_HOB \ + { \ + 0x3b387bfd, 0x7abc, 0x4cf2, \ + { \ + 0xa0, 0xca, 0xb6, 0xa1, 0x6c, 0x1b, 0x1b, 0x25 \ + } \ + } + +// +// FPDT Record Types +// +#define FPDT_GUID_EVENT_TYPE 0x1010 +#define FPDT_DYNAMIC_STRING_EVENT_TYPE 0x1011 +#define FPDT_DUAL_GUID_STRING_EVENT_TYPE 0x1012 +#define FPDT_GUID_QWORD_EVENT_TYPE 0x1013 +#define FPDT_GUID_QWORD_STRING_EVENT_TYPE 0x1014 +// todo : AMD specific types + +typedef struct __packed { + uint32_t SizeOfAllEntries; + uint32_t LoadImageCount; + uint32_t HobIsFull; +} FPDT_PEI_EXT_PERF_HEADER; + +/// +/// FPDT Performance Record header +/// +typedef struct __packed { + uint16_t Type; + uint8_t Length; + uint8_t Revision; + /// + /// ProgressID < 0x10 are reserved for core performance entries. + /// Start measurement point shall have lowered one nibble set to zero and + /// corresponding end points shall have lowered one nibble set to non-zero value; + /// keeping other nibbles same as start point. + /// + uint16_t ProgressID; + /// + /// APIC ID for the processor in the system used as a timestamp clock source. + /// If only one timestamp clock source is used, this field is Reserved and populated as + /// 0. + /// + uint32_t ApicID; + /// + /// 64-bit value (nanosecond) describing elapsed time since the most recent deassertion + /// of processor reset. + /// + uint64_t Timestamp; + /// + /// If ProgressID < 0x10, GUID of the referenced module; otherwise, GUID of the module + /// logging the event. + /// + uint8_t Guid[16]; +} FPDT_PERF_RECORD_HEADER; + +// +// FPDT Boot Performance Guid Event Record Structure +// +typedef struct __packed { + FPDT_PERF_RECORD_HEADER Header; +} FPDT_GUID_EVENT_RECORD; + +// +// FPDT Boot Performance Dynamic String Event Record Structure +// +typedef struct __packed { + FPDT_PERF_RECORD_HEADER Header; + /// + /// ASCII string describing the module. Padding supplied at the end if necessary with + /// null characters (0x00). It may be module name, function name, or token name. + /// + char String[0]; +} FPDT_DYNAMIC_STRING_EVENT_RECORD; + +// +// FPDT Boot Performance Dual GUID String Event Record Structure +// +typedef struct __packed { + FPDT_PERF_RECORD_HEADER Header; + /// + /// Event or Ppi or Protocol GUID for Callback. + /// + uint8_t Guid2[16]; + /// + /// ASCII string describing the module. Padding supplied at the end if necessary with + /// null characters (0x00). It is the function name. + /// + char String[0]; +} FPDT_DUAL_GUID_STRING_EVENT_RECORD; + +// +// FPDT Boot Performance GUID Qword Event Record Structure +// +typedef struct __packed { + FPDT_PERF_RECORD_HEADER Header; + /// + /// Qword of misc data, meaning depends on the ProgressId + /// + uint64_t Qword; +} FPDT_GUID_QWORD_EVENT_RECORD; + +// +// FPDT Boot Performance GUID Qword String Event Record Structure +// +typedef struct __packed { + FPDT_PERF_RECORD_HEADER Header; + /// + /// Qword of misc data, meaning depends on the ProgressId + /// + uint64_t Qword; + /// + /// ASCII string describing the module. Padding supplied at the end if necessary with + /// null characters (0x00). + /// + char String[0]; +} FPDT_GUID_QWORD_STRING_EVENT_RECORD; + + +typedef union { + FPDT_PERF_RECORD_HEADER RecordHeader; + FPDT_GUID_EVENT_RECORD GuidEvent; + FPDT_DYNAMIC_STRING_EVENT_RECORD DynamicStringEvent; + FPDT_DUAL_GUID_STRING_EVENT_RECORD DualGuidStringEvent; + FPDT_GUID_QWORD_EVENT_RECORD GuidQwordEvent; + FPDT_GUID_QWORD_STRING_EVENT_RECORD GuidQwordStringEvent; +} FPDT_RECORD_PTR; + +static void print_entries(uintptr_t buffer, size_t size) +{ + FPDT_RECORD_PTR *CurrentRecord, *EndOfRecords; + FPDT_PEI_EXT_PERF_HEADER *PeiPerformanceLogHeader; + uint8_t records; + uint64_t new_timestamp, old_timestamp; + + records = 0; + new_timestamp = 0; + old_timestamp = 0; + printk(BIOS_DEBUG, "%s : Offset of ProgressID %ld ApicID %ld timestamp %ld guid %ld\n", + __func__, offsetof(FPDT_PERF_RECORD_HEADER, ProgressID), + offsetof(FPDT_PERF_RECORD_HEADER, ApicID), + offsetof(FPDT_PERF_RECORD_HEADER, Timestamp), + offsetof(FPDT_PERF_RECORD_HEADER, Guid)); + + // todo check signature header + PeiPerformanceLogHeader = (FPDT_PEI_EXT_PERF_HEADER *)buffer; + CurrentRecord = (FPDT_RECORD_PTR *)(buffer + sizeof(FPDT_PEI_EXT_PERF_HEADER)); + EndOfRecords = (FPDT_RECORD_PTR *)((uint32_t)PeiPerformanceLogHeader->SizeOfAllEntries + + (uint32_t)CurrentRecord); + + while (CurrentRecord < EndOfRecords) { + printk(BIOS_DEBUG, "%s : Record num %d found type 0x%x loc 0x%x\n", __func__, + records, CurrentRecord->RecordHeader.Type, (uint32_t)CurrentRecord); + printk(BIOS_DEBUG, "Progress ID 0x%x Timestamp 0x%llx\n", + CurrentRecord->RecordHeader.ProgressID, + CurrentRecord->RecordHeader.Timestamp); + fsp_print_guid((EFI_GUID *)CurrentRecord->RecordHeader.Guid); + new_timestamp = CurrentRecord->RecordHeader.Timestamp; + + switch (CurrentRecord->RecordHeader.Type) { + case FPDT_GUID_EVENT_TYPE: + break; + case FPDT_DYNAMIC_STRING_EVENT_TYPE: + printk(BIOS_DEBUG, "Output string %.50s\n", + CurrentRecord->DynamicStringEvent.String); + break; + case FPDT_DUAL_GUID_STRING_EVENT_TYPE: + break; + case FPDT_GUID_QWORD_EVENT_TYPE: + break; + case FPDT_GUID_QWORD_STRING_EVENT_TYPE: + break; + default: + break; + } + + printk(BIOS_DEBUG, "Times 0x%llx 0x%llx\n", old_timestamp, new_timestamp); + printk(BIOS_DEBUG, "Time Delta 0x%llx\n", new_timestamp - old_timestamp); + old_timestamp = new_timestamp; + records++; + CurrentRecord = (FPDT_RECORD_PTR *)((uint32_t)CurrentRecord + + CurrentRecord->RecordHeader.Length); + } +} + +static void locate_performance_hob(void *unused) +{ + uintptr_t buffer; + size_t amd_fsp_performancelib_hob_size; + const EFI_GUID amd_fsp_performancelib_hob_guid = AMD_FSP_PERFORMANCELIB_HOB; + uint8_t instance_num; + + instance_num = 0; + + while (true) { + buffer = (uintptr_t)fsp_find_extension_hob_inst_by_guid( + (const uint8_t *)&amd_fsp_performancelib_hob_guid, + &amd_fsp_performancelib_hob_size, instance_num); + + if (buffer == 0 || amd_fsp_performancelib_hob_size == 0) { + printk(BIOS_DEBUG, "PerformanceLib HOB %d not found! \n", instance_num); + return; + } + + printk(BIOS_DEBUG, "PerformanceLib HOB %d found at location 0x%lx \n", + instance_num, buffer); + print_entries(buffer, amd_fsp_performancelib_hob_size); + instance_num++; + } +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, locate_performance_hob, NULL); + -- To view, visit https://review.coreboot.org/c/coreboot/+/48256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic064b9cb205154662280a3b2a5bc02d33a779fc7 Gerrit-Change-Number: 48256 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: mainboard: add Dell Latitude E7240
by Iru Cai (vimacs) (Code Review) 15 Dec '20

15 Dec '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Pablo Stebler, Angel Pons, Iru Cai, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40300 to look at the new patch set (#6). Change subject: mainboard: add Dell Latitude E7240 ...................................................................... mainboard: add Dell Latitude E7240 Based on autoport output. It boots from USB and mSATA with SeaBIOS. Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/dell/latitude_e7240.md M Documentation/mainboard/index.md A src/mainboard/dell/latitude_e7240/Kconfig A src/mainboard/dell/latitude_e7240/Kconfig.name A src/mainboard/dell/latitude_e7240/Makefile.inc A src/mainboard/dell/latitude_e7240/acpi/ec.asl A src/mainboard/dell/latitude_e7240/acpi/platform.asl A src/mainboard/dell/latitude_e7240/acpi/superio.asl A src/mainboard/dell/latitude_e7240/acpi_tables.c A src/mainboard/dell/latitude_e7240/board_info.txt A src/mainboard/dell/latitude_e7240/bootblock.c A src/mainboard/dell/latitude_e7240/devicetree.cb A src/mainboard/dell/latitude_e7240/dsdt.asl A src/mainboard/dell/latitude_e7240/gma-mainboard.ads A src/mainboard/dell/latitude_e7240/gpio.c A src/mainboard/dell/latitude_e7240/hda_verb.c A src/mainboard/dell/latitude_e7240/mainboard.c A src/mainboard/dell/latitude_e7240/romstage.c 18 files changed, 505 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/40300/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/40300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6933bdbcc8d0bbb85d62657624740266284ac71c Gerrit-Change-Number: 40300 Gerrit-PatchSet: 6 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Pablo Stebler <pablo(a)stebler.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Michael Niewöhner (Code Review) 15 Dec '20

15 Dec '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Georgi, Martin Roth, Paul Menzel, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48583 to look at the new patch set (#11). Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... soc/intel: hook up new gpio device in the soc chips This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/chip.c M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/common/block/gpio/Makefile.inc M src/soc/intel/common/block/gpio/gpio.c A src/soc/intel/common/block/gpio/gpio_dev.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/elkhartlake/chip.c M src/soc/intel/icelake/chip.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/skx/chip.c 14 files changed, 71 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48583/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: WIP: coreboot: Add anx7625 panel driver
by yongqiang niu (Code Review) 15 Dec '20

15 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46575 ) Change subject: WIP: coreboot: Add anx7625 panel driver ...................................................................... WIP: coreboot: Add anx7625 panel driver Add panel anx7625 to support display Signed-off-by: Huijuan Xie <huijuan.xie(a)mediatek.corp-partner.google.com> Change-Id: I045d2042b5649e36470500f266f108564b7063fa --- M src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/panel.h A src/mainboard/google/asurada/panel_anx7625.c 3 files changed, 131 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/46575/1 diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index d3f8ce6..2e5d86f 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -20,3 +20,5 @@ ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c + +ramstage-$(CONFIG_DRIVER_ANALOGIX_ANX7625) += panel_anx7625.c \ No newline at end of file diff --git a/src/mainboard/google/asurada/panel.h b/src/mainboard/google/asurada/panel.h new file mode 100644 index 0000000..648440b --- /dev/null +++ b/src/mainboard/google/asurada/panel.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_KUKUI_PANEL_H__ +#define __MAINBOARD_GOOGLE_KUKUI_PANEL_H__ + +#include <edid.h> +#include <soc/dsi.h> + +/* + * The data that to be serialized and put into CBFS. + * Note some fields, for example edid.mode.name, were actually pointers and + * cannot be really serialized. + */ +struct panel_serializable_data { + struct edid edid; /* edid info of this panel */ + enum lb_fb_orientation orientation; /* Panel orientation */ + u8 init[]; /* A packed array of lcm_init_command */ +}; + +struct panel_description { + const char *name; /* Panel name for constructing CBFS file name */ + struct panel_serializable_data *s; + void (*power_on)(void); /* Callback to turn on panel */ +}; + +/* Returns the panel description from given ID. */ +struct panel_description *get_panel_description(int panel_id); + +/* Loads panel serializable data from CBFS. */ +struct panel_description *get_panel_from_cbfs(struct panel_description *desc); + +#define INIT_DCS_CMD(...) \ + LCM_DCS_CMD, \ + sizeof((u8[]){__VA_ARGS__}), \ + __VA_ARGS__ + +#define INIT_GENERIC_CMD(...) \ + LCM_GENERIC_CMD, \ + sizeof((u8[]){__VA_ARGS__}), \ + __VA_ARGS__ + +#define INIT_DELAY_CMD(delay) \ + LCM_DELAY_CMD, \ + delay + +#define INIT_END_CMD \ + LCM_END_CMD + +/* GPIO names */ +#define GPIO_MIPIBRDG_INT_ODL GPIO(EINT6) /* 6 */ +#define GPIO_MIPIBRDG_PWREN GPIO(DSI_TE) /* 41 */ +#define GPIO_MIPIBRDG_RST_L_1V8 GPIO(LCM_RST) /* 42 */ +#define GPIO_MIPIBRDG_PP3300_EN GPIO(PERIPHERAL_EN1) /* 127 */ +#define GPIO_MIPIBRDG_PP1800_EN GPIO(PERIPHERAL_EN2) /* 128 */ +#define GPIO_MIPIBRDG_PP1000_EN GPIO(PERIPHERAL_EN3) /* 129 */ +#define GPIO_PP3300_PANEL GPIO(CAM_CLK3) /* 136 */ + +#endif /* __MAINBOARD_GOOGLE_KUKUI_PANEL_H__ */ diff --git a/src/mainboard/google/asurada/panel_anx7625.c b/src/mainboard/google/asurada/panel_anx7625.c new file mode 100644 index 0000000..0145859 --- /dev/null +++ b/src/mainboard/google/asurada/panel_anx7625.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <drivers/analogix/anx7625/anx7625.h> +#include <edid.h> +#include <gpio.h> +#include <soc/i2c.h> + +#include "panel.h" + + +static void power_on_anx7625(void) +{ + /* Disable backlight before turning on bridge */ + gpio_output(GPIO(KPROW1), 0); + gpio_output(GPIO(DISP_PWM), 0); + gpio_output(GPIO_PP3300_PANEL, 1); + + /* Turn on bridge */ + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 0); + gpio_output(GPIO_MIPIBRDG_PP1000_EN, 1); + gpio_output(GPIO_MIPIBRDG_PP1800_EN, 1); + gpio_output(GPIO_MIPIBRDG_PP3300_EN, 1); + mdelay(2); + gpio_output(GPIO_MIPIBRDG_PWREN, 1); + mdelay(10); + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 1); +} + +static void dummy_power_on(void) +{ + /* The panel has been already powered on when getting panel information + * so we should do nothing here. + */ +} + +static struct panel_serializable_data anx7625_data = { + .orientation = LB_FB_ORIENTATION_NORMAL, + .init = { INIT_END_CMD }, +}; + +static struct panel_description anx7625_panel = { + .s = &anx7625_data, + .power_on = dummy_power_on, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + /* To read panel EDID, we have to first power on anx7625. */ + power_on_anx7625(); + + u8 i2c_bus = 3; + mtk_i2c_bus_init(i2c_bus); + + if (anx7625_init(i2c_bus)) { + printk(BIOS_ERR, "Can't init ANX7625 bridge.\n"); + return NULL; + } + struct edid *edid = &anx7625_data.edid; + if (anx7625_dp_get_edid(i2c_bus, edid)) { + printk(BIOS_ERR, "Can't get panel's edid.\n"); + return NULL; + } + if (anx7625_dp_start(i2c_bus, edid) < 0) { + printk(BIOS_ERR, "Can't start display via ANX7625.\n"); + return NULL; + } + + return &anx7625_panel; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I045d2042b5649e36470500f266f108564b7063fa Gerrit-Change-Number: 46575 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 33

Change in coreboot[master]: soc/amd/common: Drop ACPIMMIO GPIO bank separation
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42690 to look at the new patch set (#10). Change subject: soc/amd/common: Drop ACPIMMIO GPIO bank separation ...................................................................... soc/amd/common: Drop ACPIMMIO GPIO bank separation It's assumed in ASL already that the banks appear one after other in ACPIMMIO space. There is no need for the separation of accessor functions by name. Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h 2 files changed, 0 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/42690/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/42690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6 Gerrit-Change-Number: 42690 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: Revert "cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()"
by Mike Banon (Code Review) 15 Dec '20

15 Dec '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Julius Werner, Angel Pons, Aaron Durbin, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48324 to review the following change. Change subject: Revert "cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()" ...................................................................... Revert "cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()" This reverts commit 9d0cc2aea918eced42dc3825c1ac94d0d4fbc380. Reason for revert: This commit breaks ASUS AM1I-A board (AMD fam16h) - confirmed by commit dichotomy. Now, while booting, this board gets a "CBFS ERROR: CBFS mcache overflow!" - which happens regardless of CBFS_MCACHE_SIZE. Luckily it doesn't break Lenovo G505S or ASUS A88XM-E, which are AMD fam15h. Until we come up with a workaround, this commit should be reverted, as well as the others based on it if available. Change-Id: I0e092c966da60deae21d19eb4053628541595bbb --- M src/drivers/pc80/rtc/option.c M src/include/cbfs.h M src/lib/cbfs.c M src/northbridge/intel/haswell/raminit.c M src/soc/intel/broadwell/raminit.c M src/soc/intel/quark/romstage/romstage.c 6 files changed, 93 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/48324/1 diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index 409f0ef..bb9d29a 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -49,28 +49,36 @@ return CB_SUCCESS; } -static struct cmos_option_table *get_cmos_layout(void) +static enum cb_err locate_cmos_layout(struct region_device *rdev) { - static struct cmos_option_table *ct = NULL; + uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; + static struct cbfsf fh; /* * In case VBOOT is enabled and this function is called from SMM, * we have multiple CMOS layout files and to locate them we'd need to * include VBOOT into SMM... * - * Support only one CMOS layout in the RO CBFS for now. + * Support only one CMOS layout in the 'COREBOOT' region for now. */ - if (!ct) - ct = cbfs_ro_map("cmos_layout.bin", NULL); - if (!ct) - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " - "Options are disabled\n"); - return ct; + if (!region_device_sz(&(fh.data))) { + if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin", + &cbfs_type)) { + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " + "Options are disabled\n"); + return CB_CMOS_LAYOUT_NOT_FOUND; + } + } + + cbfs_file_data(rdev, &fh); + + return CB_SUCCESS; } enum cb_err cmos_get_option(void *dest, const char *name) { struct cmos_option_table *ct; + struct region_device rdev; struct cmos_entries *ce; size_t namelen; int found = 0; @@ -78,9 +86,16 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - ct = get_cmos_layout(); - if (!ct) + if (locate_cmos_layout(&rdev) != CB_SUCCESS) { return CB_CMOS_LAYOUT_NOT_FOUND; + } + ct = rdev_mmap_full(&rdev); + if (!ct) { + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " + "Options are disabled\n"); + + return CB_CMOS_LAYOUT_NOT_FOUND; + } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -93,15 +108,19 @@ } if (!found) { printk(BIOS_DEBUG, "No CMOS option '%s'.\n", name); + rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } - if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) + if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { + rdev_munmap(&rdev, ct); return CB_CMOS_CHECKSUM_INVALID; - - if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) + } + if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { + rdev_munmap(&rdev, ct); return CB_CMOS_ACCESS_ERROR; - + } + rdev_munmap(&rdev, ct); return CB_SUCCESS; } @@ -149,6 +168,7 @@ enum cb_err cmos_set_option(const char *name, void *value) { struct cmos_option_table *ct; + struct region_device rdev; struct cmos_entries *ce; unsigned long length; size_t namelen; @@ -157,9 +177,16 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - ct = get_cmos_layout(); - if (!ct) + if (locate_cmos_layout(&rdev) != CB_SUCCESS) { return CB_CMOS_LAYOUT_NOT_FOUND; + } + ct = rdev_mmap_full(&rdev); + if (!ct) { + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " + "Options are disabled\n"); + + return CB_CMOS_LAYOUT_NOT_FOUND; + } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -172,6 +199,7 @@ } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); + rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } @@ -180,13 +208,18 @@ length = MAX(strlen((const char *)value) * 8, ce->length - 8); /* make sure the string is null terminated */ if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) - != CB_SUCCESS) + != CB_SUCCESS) { + rdev_munmap(&rdev, ct); return CB_CMOS_ACCESS_ERROR; + } } - if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) + if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) { + rdev_munmap(&rdev, ct); return CB_CMOS_ACCESS_ERROR; + } + rdev_munmap(&rdev, ct); return CB_SUCCESS; } diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 8d4c220..992b658 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -23,12 +23,9 @@ NOTE: Since this may return a direct pointer to memory-mapped hardware, compressed files are NOT transparently decompressed (unlike cbfs_load()). */ void *cbfs_map(const char *name, size_t *size_out); -/* Like cbfs_map(), except that it will always read from the read-only CBFS - ("COREBOOT" FMAP region), even when CONFIG(VBOOT) is enabled. */ -void *cbfs_ro_map(const char *name, size_t *size_out); -/* Removes a previously allocated CBFS mapping. Should try to unmap mappings in - strict LIFO order where possible, since mapping backends often don't support - more complicated cases. */ +/* Removes a mapping previously allocated with cbfs_map(). Should try to unmap + mappings in strict LIFO order where possible, since mapping backends often + don't support more complicated cases. */ int cbfs_unmap(void *mapping); /* Locate file in a specific region of fmap. Return 0 on success. < 0 on error*/ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, @@ -37,9 +34,6 @@ success or 0 on error. File will get decompressed as necessary. Same decompression requirements as cbfs_load_and_decompress(). */ size_t cbfs_load(const char *name, void *buf, size_t buf_size); -/* Like cbfs_load(), except that it will always read from the read-only CBFS - ("COREBOOT" FMAP region), even when CONFIG(VBOOT) is enabled. */ -size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size); /* Load |in_size| bytes from |rdev| at |offset| to the |buffer_size| bytes * large |buffer|, decompressing it according to |compression| in the process. * Returns the decompressed file size, or 0 on error. diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index beab74e..8d868a6 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -70,12 +70,12 @@ return 0; } -static void *_cbfs_map(const char *name, size_t *size_out, bool force_ro) +void *cbfs_map(const char *name, size_t *size_out) { struct region_device rdev; union cbfs_mdata mdata; - if (cbfs_boot_lookup(name, force_ro, &mdata, &rdev)) + if (cbfs_boot_lookup(name, false, &mdata, &rdev)) return NULL; if (size_out != NULL) @@ -84,16 +84,6 @@ return rdev_mmap_full(&rdev); } -void *cbfs_map(const char *name, size_t *size_out) -{ - return _cbfs_map(name, size_out, false); -} - -void *cbfs_ro_map(const char *name, size_t *size_out) -{ - return _cbfs_map(name, size_out, true); -} - int cbfs_unmap(void *mapping) { /* This works because munmap() only works on the root rdev and never @@ -291,13 +281,12 @@ return cbfs_map(name, NULL); } -static size_t _cbfs_load(const char *name, void *buf, size_t buf_size, - bool force_ro) +size_t cbfs_load(const char *name, void *buf, size_t buf_size) { struct region_device rdev; union cbfs_mdata mdata; - if (cbfs_boot_lookup(name, force_ro, &mdata, &rdev)) + if (cbfs_boot_lookup(name, false, &mdata, &rdev)) return 0; uint32_t compression = CBFS_COMPRESS_NONE; @@ -313,16 +302,6 @@ buf, buf_size, compression); } -size_t cbfs_load(const char *name, void *buf, size_t buf_size) -{ - return _cbfs_load(name, buf, buf_size, false); -} - -size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size) -{ - return _cbfs_load(name, buf, buf_size, true); -} - int cbfs_prog_stage_load(struct prog *pstage) { struct cbfs_stage stage; diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 9617ffb..290e402 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -107,6 +107,9 @@ { int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1))); + uint32_t type = CBFS_TYPE_MRC; + struct cbfsf f; + printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); /* @@ -127,10 +130,13 @@ /* * Locate and call UEFI System Agent binary. The binary needs to be at a fixed offset - * in the flash and can therefore only reside in the COREBOOT fmap region. We don't care - * about leaking the mapping. + * in the flash and can therefore only reside in the COREBOOT fmap region. */ - entry = cbfs_ro_map("mrc.bin", NULL); + if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) + die("mrc.bin not found!"); + + /* We don't care about leaking the mapping */ + entry = rdev_mmap_full(&f.data); if (entry) { int rv = entry(pei_data); diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c index 44a8937..e51b4f7 100644 --- a/src/soc/intel/broadwell/raminit.c +++ b/src/soc/intel/broadwell/raminit.c @@ -80,6 +80,8 @@ struct memory_info *mem_info; pei_wrapper_entry_t entry; int ret; + struct cbfsf f; + uint32_t type = CBFS_TYPE_MRC; broadwell_fill_pei_data(pei_data); @@ -112,10 +114,15 @@ pei_data->saved_data_size = 0; } - /* We don't care about leaking the mapping */ - entry = cbfs_ro_map("mrc.bin", NULL); - if (entry == NULL) + /* Determine if mrc.bin is in the cbfs. */ + if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) die("mrc.bin not found!"); + /* We don't care about leaking the mapping */ + entry = (pei_wrapper_entry_t)rdev_mmap_full(&f.data); + if (entry == NULL) { + printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); + return; + } printk(BIOS_DEBUG, "Starting Memory Reference Code\n"); diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 23a551e..9800aa4 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -49,16 +49,29 @@ void *locate_rmu_file(size_t *rmu_file_len) { + struct cbfsf fh; size_t fsize; void *rmu_data; + uint32_t type; /* Locate the rmu.bin file in the read-only region of the flash */ - rmu_data = cbfs_ro_map("rmu.bin", &fsize); - if (!rmu_data) + type = CBFS_TYPE_RAW; + if (cbfs_locate_file_in_region(&fh, "COREBOOT", "rmu.bin", &type)) return NULL; + /* Get the file size */ + fsize = region_device_sz(&fh.data); if (rmu_file_len != NULL) *rmu_file_len = fsize; + /* Get the data address */ + rmu_data = rdev_mmap(&fh.data, 0, fsize); + + /* Since the SPI flash is directly mapped into memory, we do not need + * the mapping provided by the rdev service. Unmap the file to prevent + * a memory leak. Return/leak the SPI flash address for the rmu.bin + * file data which will be directly accessed by FSP MemoryInit. + */ + rdev_munmap(&fh.data, rmu_data); return rmu_data; } -- To view, visit https://review.coreboot.org/c/coreboot/+/48324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e092c966da60deae21d19eb4053628541595bbb Gerrit-Change-Number: 48324 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: [WIP] sb/amd/pi/hudson: Fixes for common GPIO API
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42733 to look at the new patch set (#10). Change subject: [WIP] sb/amd/pi/hudson: Fixes for common GPIO API ...................................................................... [WIP] sb/amd/pi/hudson: Fixes for common GPIO API Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Kconfig A src/southbridge/amd/pi/hudson/soc/gpio.h A src/southbridge/amd/pi/hudson/soc/smi.h M src/vendorcode/amd/pi/Makefile.inc 4 files changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/42733/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/42733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Gerrit-Change-Number: 42733 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2020