Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48281 )
Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48281/6/src/soc/intel/tigerlake/ro…
File src/soc/intel/tigerlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48281/6/src/soc/intel/tigerlake/ro…
PS6, Line 140: /* cse_fw_sync() must be called after DRAM initialization */
> Same comment as JSL.
Ack
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48280 )
Change subject: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48280/6/src/soc/intel/jasperlake/r…
File src/soc/intel/jasperlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48280/6/src/soc/intel/jasperlake/r…
PS6, Line 140: cse_fw_sync() must be called after DRAM initialization
> It would be helpful to also add the information that HMRFPO (which is used by cse_fw_sync()) is expe […]
Ack
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48279 )
Change subject: soc/intel/common: Move CSE Lite driver functionality into romstage
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48279/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/48279/2//COMMIT_MSG@13
PS2, Line 13: Verified on JSL and TGL platforms
> Can you please add that detail to the commit message?
Ack
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Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Tim Wawrzynczak, Paul Menzel, Rizwan Qureshi, Sugnan Prabhu S, Krishna P Bhat D, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48281
to look at the new patch set (#7).
Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
......................................................................
soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
This patch sets up cse_fw_sync() call in the romstage. The cse_fw_sync()
must be called after DRAM initialization.
BUG=b:174694480
Test=Verified on Tigerlake platform
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856
---
M src/soc/intel/tigerlake/romstage/romstage.c
1 file changed, 12 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/48281/7
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Gerrit-MessageType: newpatchset
Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Tim Wawrzynczak, Paul Menzel, Sugnan Prabhu S, Rizwan Qureshi, Krishna P Bhat D, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48280
to look at the new patch set (#7).
Change subject: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage
......................................................................
soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage
This patch sets up cse_fw_sync() call in the romstage.The cse_fw_sync()
must be called after DRAM initialization.
BUG=b:174694480
Test=Verified on Drawlet
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a
---
M src/soc/intel/jasperlake/romstage/romstage.c
1 file changed, 11 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/48280/7
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Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Jamie Ryu, Tim Wawrzynczak, Rizwan Qureshi, Sugnan Prabhu S, Krishna P Bhat D, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#7).
Change subject: soc/intel/common: Move CSE Lite driver functionality into romstage
......................................................................
soc/intel/common: Move CSE Lite driver functionality into romstage
The patch sets up the CSE Lite driver in the romstage instead of ramstage.
With this change, CSE Lite driver sets CSE's boot partition and triggers
CSE FW update in the romstage. The cse_fw_sync() must be called after DRAM
initialization as HMRFPO_ENABLE HECI command (which is used by
cse_fw_sync()) is expected to be executed after DRAM initialization. With
this change, it improves the cold boot time by ~154ms.
Test=Verified on JSL and TGL platforms
BUG=b:174694480
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73
---
M src/soc/intel/common/block/cse/Makefile.inc
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
3 files changed, 3 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/48279/7
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Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48494 )
Change subject: soc/inte/common: Replace #if macro with if C-language constuct
......................................................................
soc/inte/common: Replace #if macro with if C-language constuct
This patch modifies CSE Lite driver to use 'if' C-lanugage construct
instead of #if macro.
TEST=Built the code for drawcia
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: Iecd5cf56ecd280de920f479e174762fe6b4164b0
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/cse_lite.c
2 files changed, 6 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/48494/1
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index d3b7288..c562ea3 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -29,7 +29,6 @@
This config will enable CSE RW firmware update feature and also will be used ensure
all the required configs are provided by mainboard.
-if SOC_INTEL_CSE_RW_UPDATE
config SOC_INTEL_CSE_FMAP_NAME
string "Name of CSE Region in FMAP"
default "SI_ME"
@@ -75,4 +74,3 @@
This config contains the Intel CSE RW version of the blob that is provided by
SOC_INTEL_CSE_RW_FILE config and the version must be set in the format
major.minor.hotfix.build (ex: 14.0.40.1209).
-endif
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index d173b6a..c7dac38 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -429,7 +429,6 @@
return cse_boot_to_rw(cse_bp_info);
}
-#if CONFIG(SOC_INTEL_CSE_RW_UPDATE)
static const struct fw_version *cse_get_bp_entry_version(enum boot_partition_id bp,
const struct cse_bp_info *bp_info)
{
@@ -772,7 +771,6 @@
return 0;
}
-#endif
void cse_fw_sync(void *unused)
{
@@ -801,12 +799,12 @@
* If SOC_INTEL_CSE_RW_UPDATE is defined , then trigger CSE firmware update. The driver
* triggers recovery if CSE CBFS RW metadata or CSE CBFS RW blob is not available.
*/
-#if CONFIG(SOC_INTEL_CSE_RW_UPDATE)
- uint8_t rv;
- rv = cse_fw_update(&cse_bp_info.bp_info);
- if (rv)
- cse_trigger_recovery(rv);
-#endif
+ if (CONFIG(SOC_INTEL_CSE_RW_UPDATE)) {
+ uint8_t rv;
+ rv = cse_fw_update(&cse_bp_info.bp_info);
+ if (rv)
+ cse_trigger_recovery(rv);
+ }
if (!cse_boot_to_rw(&cse_bp_info.bp_info)) {
printk(BIOS_ERR, "cse_lite: Failed to switch to RW\n");
--
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