Hello Felix Singer, V Sowmya, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/48570
to review the following change.
Change subject: soc/intel/jasperlake: Drop unreferenced devicetree settings
......................................................................
soc/intel/jasperlake: Drop unreferenced devicetree settings
No mainboard uses these settings, nor does SoC code. Drop them.
Change-Id: I40eba4128f1c5bafc7023b28dbaf40c0aca3f490
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/jasperlake/chip.h
1 file changed, 0 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/48570/1
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 2fc32c9..9d4bc5c 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -129,22 +129,13 @@
/* Enable if SD Card Power Enable Signal is Active High */
uint8_t SdCardPowerEnableActiveHigh;
- /* Integrated Sensor */
- uint8_t PchIshEnable;
-
- /* Heci related */
- uint8_t Heci3Enabled;
-
/* VR Config Settings for IA Core */
uint16_t ImonSlope;
uint16_t ImonOffset;
/* Gfx related */
- uint8_t IgdDvmt50PreAlloc;
uint8_t SkipExtGfxScan;
- uint32_t GraphicsConfigPtr;
-
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I40eba4128f1c5bafc7023b28dbaf40c0aca3f490
Gerrit-Change-Number: 48570
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com>
Gerrit-MessageType: newchange
Hello Felix Singer, V Sowmya, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/48568
to review the following change.
Change subject: soc/intel/elkhartlake: Drop unreferenced devicetree settings
......................................................................
soc/intel/elkhartlake: Drop unreferenced devicetree settings
No mainboard uses these settings, nor does SoC code. Drop them.
Change-Id: Ia928c4bbddd1c160228a9af8faf5d4be787f73f8
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/elkhartlake/chip.h
1 file changed, 0 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/48568/1
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index 7cd29b4..37237bb 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -132,17 +132,9 @@
/* Enable if SD Card Power Enable Signal is Active High */
uint8_t SdCardPowerEnableActiveHigh;
- /* Integrated Sensor */
- uint8_t PchIshEnable;
-
- /* Heci related */
- uint8_t Heci3Enabled;
-
/* Gfx related */
- uint8_t IgdDvmt50PreAlloc;
uint8_t SkipExtGfxScan;
- uint32_t GraphicsConfigPtr;
uint8_t Device4Enable;
/* HeciEnabled decides the state of Heci1 at end of boot
--
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Gerrit-Branch: master
Gerrit-Change-Id: Ia928c4bbddd1c160228a9af8faf5d4be787f73f8
Gerrit-Change-Number: 48568
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com>
Gerrit-MessageType: newchange
Hello Felix Singer, V Sowmya, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Arthur Heymans, Michael Niewöhner, Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/48566
to review the following change.
Change subject: soc/intel/alderlake: Drop unreferenced devicetree settings
......................................................................
soc/intel/alderlake: Drop unreferenced devicetree settings
No mainboard uses these settings, nor does SoC code. Drop them.
Change-Id: Ib4cf88a482f840edf16e2ac42e6ab61eccfba0aa
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/alderlake/chip.h
1 file changed, 0 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/48566/1
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 428fd4d..38d9671 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -146,12 +146,6 @@
/* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
- /* Integrated Sensor */
- uint8_t PchIshEnable;
-
- /* Heci related */
- uint8_t Heci3Enabled;
-
/* Gfx related */
enum {
IGD_SM_0MB = 0x00,
@@ -178,8 +172,6 @@
uint8_t InternalGfx;
uint8_t SkipExtGfxScan;
- uint32_t GraphicsConfigPtr;
-
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;
--
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Gerrit-Change-Id: Ib4cf88a482f840edf16e2ac42e6ab61eccfba0aa
Gerrit-Change-Number: 48566
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com>
Gerrit-MessageType: newchange
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48604 )
Change subject: Doc/mb/lenovo: Explain simpler GM45 flash method first
......................................................................
Doc/mb/lenovo: Explain simpler GM45 flash method first
Do not mislead newcomers into thinking the GM45 series laptops are hard
to flash. Describe the simple coreboot flashing procedure first, then
explain how to remove the ME firmware and use a custom flash layout.
Also, reword a sentence on the simple flashing procedure for clarity.
Change-Id: Ie83ec3d20f00e9d9c869e483e24d601506857f07
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M Documentation/mainboard/lenovo/montevina_series.md
1 file changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/48604/1
diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md
index c886a21..b513c97 100644
--- a/Documentation/mainboard/lenovo/montevina_series.md
+++ b/Documentation/mainboard/lenovo/montevina_series.md
@@ -9,6 +9,15 @@
Note that this does not allow you to determine whether the chip is in a SOIC-8
or a SOIC-16 package.
+## Installing with ME firmware
+
+To install coreboot and keep ME working, you don't need to do anything special
+with the flash descriptor. Only flash the `bios` region externally and don't
+touch any other regions:
+```console
+# flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios
+```
+
## Installing without ME firmware
```eval_rst
@@ -127,15 +136,6 @@
Then build coreboot and flash whole `build/coreboot.rom` to the chip.
-## Installing with ME firmware
-
-To install coreboot and keep ME working, you don't need to do anything special
-with the flash descriptor. Just flash only `bios` externally and don't touch any
-other regions:
-```console
-# flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios
-```
-
## Flash layout
The flash layouts of the OEM firmware are as follows:
--
To view, visit https://review.coreboot.org/c/coreboot/+/48604
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Gerrit-Change-Id: Ie83ec3d20f00e9d9c869e483e24d601506857f07
Gerrit-Change-Number: 48604
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-MessageType: newchange