Change in coreboot[master]: intel/common/block/lpc: Add new device IDs for Emmitsburg PCH
Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48596 )
Change subject: intel/common/block/lpc: Add new device IDs for Emmitsburg PCH ......................................................................
intel/common/block/lpc: Add new device IDs for Emmitsburg PCH
Add LPC/eSPI device ID of Emmitsburg (EMB) for setting LPC resources.
Refer to Emmitsburg PCH EDS (606161).
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: Ie5a5d9ba7e4f664ada2dae2294d6e4d0280a2157 --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/48596/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 9e6ac64..8ac29c5 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2837,6 +2837,7 @@ #define PCI_DEVICE_ID_INTEL_LWB_C621A_SUPER 0xa24a #define PCI_DEVICE_ID_INTEL_LWB_C627A_SUPER 0xa24b #define PCI_DEVICE_ID_INTEL_LWB_C629A_SUPER 0xa24c +#define PCI_DEVICE_ID_INTEL_EMB_SUPER 0x1b81 #define PCI_DEVICE_ID_INTEL_KBP_H_H270 0xa2c4 #define PCI_DEVICE_ID_INTEL_KBP_H_Z270 0xa2c5 #define PCI_DEVICE_ID_INTEL_KBP_H_Q270 0xa2c6 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index fc24b0a..369b6b1 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -153,6 +153,7 @@ PCI_DEVICE_ID_INTEL_LWB_C621A_SUPER, PCI_DEVICE_ID_INTEL_LWB_C627A_SUPER, PCI_DEVICE_ID_INTEL_LWB_C629A_SUPER, + PCI_DEVICE_ID_INTEL_EMB_SUPER, PCI_DEVICE_ID_INTEL_KBP_H_Q270, PCI_DEVICE_ID_INTEL_KBP_H_H270, PCI_DEVICE_ID_INTEL_KBP_H_Z270,
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48596 )
Change subject: intel/common/block/lpc: Add new device IDs for Emmitsburg PCH ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48596 )
Change subject: intel/common/block/lpc: Add new device IDs for Emmitsburg PCH ......................................................................
Patch Set 1: Code-Review+2
AFAIK, Emmitsburg is the PCH for next generation Xeon D processors
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48596 )
Change subject: intel/common/block/lpc: Add new device IDs for Emmitsburg PCH ......................................................................
Patch Set 1:
Patch Set 1: Code-Review+2
AFAIK, Emmitsburg is the PCH for next generation Xeon D processors
Yes, it is also the PCH for next generation Xeon-SP processor (SPR-SP), which is used in EGS (EagleStream) platform, the server platform after Whitney.
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48596 )
Change subject: intel/common/block/lpc: Add new device IDs for Emmitsburg PCH ......................................................................
intel/common/block/lpc: Add new device IDs for Emmitsburg PCH
Add LPC/eSPI device ID of Emmitsburg (EMB) for setting LPC resources.
Refer to Emmitsburg PCH EDS (606161).
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: Ie5a5d9ba7e4f664ada2dae2294d6e4d0280a2157 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48596 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c 2 files changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 9e6ac64..8ac29c5 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2837,6 +2837,7 @@ #define PCI_DEVICE_ID_INTEL_LWB_C621A_SUPER 0xa24a #define PCI_DEVICE_ID_INTEL_LWB_C627A_SUPER 0xa24b #define PCI_DEVICE_ID_INTEL_LWB_C629A_SUPER 0xa24c +#define PCI_DEVICE_ID_INTEL_EMB_SUPER 0x1b81 #define PCI_DEVICE_ID_INTEL_KBP_H_H270 0xa2c4 #define PCI_DEVICE_ID_INTEL_KBP_H_Z270 0xa2c5 #define PCI_DEVICE_ID_INTEL_KBP_H_Q270 0xa2c6 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index fc24b0a..369b6b1 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -153,6 +153,7 @@ PCI_DEVICE_ID_INTEL_LWB_C621A_SUPER, PCI_DEVICE_ID_INTEL_LWB_C627A_SUPER, PCI_DEVICE_ID_INTEL_LWB_C629A_SUPER, + PCI_DEVICE_ID_INTEL_EMB_SUPER, PCI_DEVICE_ID_INTEL_KBP_H_Q270, PCI_DEVICE_ID_INTEL_KBP_H_H270, PCI_DEVICE_ID_INTEL_KBP_H_Z270,
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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Hung-Te Lin (Code Review)
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Jonathan Zhang (Code Review)