coreboot-gerrit December 2020

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Change in coreboot[master]: [WIP] sb/amd/pi/hudson: Fixes for common GPIO API
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42733 ) Change subject: [WIP] sb/amd/pi/hudson: Fixes for common GPIO API ...................................................................... Patch Set 9: (3 comments) https://review.coreboot.org/c/coreboot/+/42733/8/src/southbridge/amd/pi/hud… File src/southbridge/amd/pi/hudson/soc/smi.h: PS8: > for everything apart from the defines soc/amd/common/block/include/amdblocks/smi. […] I think it was the same question as with <soc/gpio.h>, how should the #includes look like when the tree is organized as discrete cpu/ nb/ sb/ directories. https://review.coreboot.org/c/coreboot/+/42733/8/src/southbridge/amd/pi/hud… PS8, Line 4: #define __SOC_SMI_H__ Drop __ https://review.coreboot.org/c/coreboot/+/42733/8/src/southbridge/amd/pi/hud… PS8, Line 7: /* FIXME: Copies from stoneyridge now. */ Resolve before merge -- To view, visit https://review.coreboot.org/c/coreboot/+/42733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Gerrit-Change-Number: 42733 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 15 Dec 2020 04:58:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] sb/amd/pi/hudson: Fixes for common GPIO API
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42733 to look at the new patch set (#9). Change subject: [WIP] sb/amd/pi/hudson: Fixes for common GPIO API ...................................................................... [WIP] sb/amd/pi/hudson: Fixes for common GPIO API Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Kconfig A src/southbridge/amd/pi/hudson/soc/gpio.h A src/southbridge/amd/pi/hudson/soc/smi.h M src/vendorcode/amd/pi/Makefile.inc 4 files changed, 52 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/42733/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/42733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Gerrit-Change-Number: 42733 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8183/sspm.c: Use mtlib_init_mcu API
by Yidi Lin (Code Review) 15 Dec '20

15 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48441 ) Change subject: soc/mediatek/mt8183/sspm.c: Use mtlib_init_mcu API ...................................................................... soc/mediatek/mt8183/sspm.c: Use mtlib_init_mcu API Use mtlib_init_mcu API to load and run sspm firmware. TEST=emerge-kukui coreboot Change-Id: I63c4b99342bdebb2a94cbf0c6380b0a6817853e7 Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I785a6e6e09bd47252ce8497f289b2d1769d969cd --- M src/soc/mediatek/mt8183/Kconfig M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/sspm.c 3 files changed, 23 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/48441/1 diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index 82827d1..73271fa 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -45,4 +45,11 @@ bool default y +config SSPM_FIRMWARE + string "The file name of the MediaTek SSPM firmware" + default "sspm.bin" + help + The file name of the MediaTek SSPM firmware. + + endif diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 43893c3..d2d0390 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -52,6 +52,7 @@ ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c +ramstage-y += ../common/mtlib.c ramstage-y += ../common/pmic_wrap.c ramstage-y += ../common/rtc.c rtc.c ramstage-y += soc.c diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c index 1a4ba9e..0f0c9ca 100644 --- a/src/soc/mediatek/mt8183/sspm.c +++ b/src/soc/mediatek/mt8183/sspm.c @@ -1,26 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/barrier.h> -#include <cbfs.h> -#include <console/console.h> #include <device/mmio.h> +#include <soc/mtlib_common.h> #include <soc/sspm.h> -#include <string.h> +#include <soc/symbols.h> -#define BUF_SIZE (64 * KiB) -static uint8_t sspm_bin[BUF_SIZE] __aligned(8); +static void reset_sspm(struct mtlib_mcu *mcu) +{ + write32(&mt8183_sspm->sw_rstn, 0x1); +} + +static struct mtlib_mcu sspm = { + .firmware_name = CONFIG_SSPM_FIRMWARE, + .run_address = (void *)SSPM_SRAM_BASE, + .reset = reset_sspm, +}; void sspm_init(void) { - const char *file_name = "sspm.bin"; - size_t fw_size = cbfs_load(file_name, sspm_bin, sizeof(sspm_bin)); + sspm.load_buffer = _dram_dma; + sspm.buffer_size = REGION_SIZE(dram_dma); - if (fw_size == 0) - die("SSPM file :sspm.bin not found."); - - memcpy((void *)SSPM_SRAM_BASE, sspm_bin, fw_size); - /* Memory barrier to ensure that all fw code is loaded - before we release the reset pin. */ - mb(); - write32(&mt8183_sspm->sw_rstn, 0x1); + mtlib_init_mcu(&sspm); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I785a6e6e09bd47252ce8497f289b2d1769d969cd Gerrit-Change-Number: 48441 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: DO-NOT-SUBMIT: Asurada ToT - display
by Yidi Lin (Code Review) 15 Dec '20

15 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48489 ) Change subject: DO-NOT-SUBMIT: Asurada ToT - display ...................................................................... DO-NOT-SUBMIT: Asurada ToT - display Change-Id: Ib5bfb3826230950426c578ad576ba54023794c74 Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M 3rdparty/qc_blobs 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/48489/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index d0a9215..539d31a 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit d0a92151d387b5296b6c5fbff4e4d66839c5c2dd +Subproject commit 539d31ab9ea89084fa5edf7cc9ac3122786d5454 diff --git a/3rdparty/blobs b/3rdparty/blobs index a59fb6e..40b730a 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit a59fb6e3892f0629d43769a07ee7f1048a0ae1f8 +Subproject commit 40b730aed381bf39c9f523b0852167c8be3558b6 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 0e4288f..ee319ae 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 0e4288f81f806620c65f70ee2bcf94b69d574096 +Subproject commit ee319ae7bc59e88b60142f40a9ec1b46656de4db diff --git a/3rdparty/qc_blobs b/3rdparty/qc_blobs index 6b7fe49..11b212c 160000 --- a/3rdparty/qc_blobs +++ b/3rdparty/qc_blobs @@ -1 +1 @@ -Subproject commit 6b7fe498eb782b8f9758f28dd53bb0697be0d0b0 +Subproject commit 11b212c273b930885d1bee0b00a223a73628c852 -- To view, visit https://review.coreboot.org/c/coreboot/+/48489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5bfb3826230950426c578ad576ba54023794c74 Gerrit-Change-Number: 48489 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_mini: Adjust PL1/2 levels
by Matt DeVillier (Code Review) 15 Dec '20

15 Dec '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48586 ) Change subject: mb/purism/librem_mini: Adjust PL1/2 levels ...................................................................... mb/purism/librem_mini: Adjust PL1/2 levels While the Librem Mini (v1/v2) are more than capable of higher PL1/2, they currently ship with a 40W power supply, so set PL1/2 accordingly to avoid power spikes above the PSU rating (which can result in unexpected showdowns/reboots) Change-Id: Ia7f89e885f1af29cbbb67d6fb844257ba2b87417 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/48586/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 6b326f0..8fb84ce 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -7,8 +7,8 @@ # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ - .tdp_pl1_override = 25, - .tdp_pl2_override = 51, + .tdp_pl1_override = 15, + .tdp_pl2_override = 28, }" # Enable Enhanced Intel SpeedStep -- To view, visit https://review.coreboot.org/c/coreboot/+/48586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7f89e885f1af29cbbb67d6fb844257ba2b87417 Gerrit-Change-Number: 48586 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: coreboot: Add display code
by yongqiang niu (Code Review) 15 Dec '20

15 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46578 ) Change subject: WIP: coreboot: Add display code ...................................................................... WIP: coreboot: Add display code Add display init code to support display Signed-off-by: Huijuan Xie <huijuan.xie(a)mediatek.corp-partner.google.com> Change-Id: If730c42451f7b392285df686abc4ca252d8d42cf --- M src/mainboard/google/asurada/mainboard.c 1 file changed, 103 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46578/1 diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 677e917..30e98e8 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -1,16 +1,27 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <bl31.h> +#include <boardid.h> +#include <bootmode.h> #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <device/mmio.h> +#include <edid.h> +#include <gpio.h> #include <lib.h> +#include <soc/ddp.h> +#include <soc/dsi.h> #include <soc/dpm.h> +#include <soc/gpio.h> #include <soc/gpio_common.h> +#include <soc/mtcmos.h> #include <soc/spm.h> #include <soc/usb.h> #include "gpio.h" +#include "panel.h" #include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h> @@ -34,10 +45,102 @@ register_bl31_aux_param(&param_reset.h); } +/* Default implementation for boards without panels defined yet. */ +struct panel_description __weak *get_panel_description(int panel_id) +{ + printk(BIOS_ERR, "%s: ERROR: No panels defined for board: %s.\n", + __func__, CONFIG_MAINBOARD_PART_NUMBER); + return NULL; +} + +/* Set up backlight control pins as output pin and power-off by default */ +static void configure_panel_backlight(void) +{ + gpio_output(GPIO(KPROW1), 0); + gpio_output(GPIO(DISP_PWM), 0); +} + +static void power_on_panel(struct panel_description *panel) +{ + if (panel->power_on) { + panel->power_on(); + return; + } + + /* Default power sequence for most panels. */ + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 0); + mdelay(6); + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 1); + mdelay(6); +} + +static struct panel_description *get_active_panel(void) +{ + /* TODO(hungte) Create a dedicated panel_id() in board_id.c */ + int panel_id = sku_id() >> 4; + + struct panel_description *panel = get_panel_description(panel_id); + if (!panel) { + printk(BIOS_ERR, "%s: Panel %d is not supported.\n", + __func__, panel_id); + return NULL; + } + assert(panel->s); + + const struct edid *edid = &panel->s->edid; + const char *name = edid->ascii_string; + if (name[0] == '\0') + name = "unknown name"; + printk(BIOS_INFO, "%s: Found ID %d: '%s %s' %dx%d@%dHz\n", __func__, + panel_id, edid->manufacturer_name, name, edid->mode.ha, + edid->mode.va, edid->mode.refresh); + return panel; +} + +static bool configure_display(void) +{ + struct panel_description *panel = get_active_panel(); + if (!panel) + return false; + + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + configure_panel_backlight(); + power_on_panel(panel); + + struct edid *edid = &panel->s->edid; + edid_set_framebuffer_bits_per_pixel(edid, 32, 0); + mtk_ddp_init(); + u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM); + if (CONFIG(DRIVER_ANALOGIX_ANX7625)) + mipi_dsi_flags |= MIPI_DSI_MODE_EOT_PACKET; + if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, edid, + panel->s->init) < 0) { + printk(BIOS_ERR, "%s: Failed in DSI init.\n", __func__); + return false; + } + mtk_ddp_mode_set(edid); + set_vbe_mode_info_valid(edid, 0); + set_vbe_framebuffer_orientation(panel->s->orientation); + return true; +} + static void mainboard_init(struct device *dev) { int i; + if (display_init_required()) { + printk(BIOS_INFO, "%s: Starting display init.\n", __func__); + if (!configure_display()) + printk(BIOS_ERR, "%s: Failed to init display.\n", + __func__); + } else { + printk(BIOS_INFO, "%s: Skipped display init.\n", __func__); + } + + /* HACK, set pinctrl for SD card */ for (i = 51; i <= 56; i++) gpio_set_mode((gpio_t){.id = i}, 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/46578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If730c42451f7b392285df686abc4ca252d8d42cf Gerrit-Change-Number: 46578 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kukui: help payload to identify correct speaker amp type
by Hung-Te Lin (Code Review) 15 Dec '20

15 Dec '20

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48558 ) Change subject: mb/google/kukui: help payload to identify correct speaker amp type ...................................................................... mb/google/kukui: help payload to identify correct speaker amp type Kukui based devices may use different speaker amplifiers, for example MAX98357A, RT1015, or RT1015Q/automode. To help payloads identifying which component was installed on board, we want to pass the speaker GPIO in different name. This can be set in Kconfig as CONFIG_SPEAKER_GPIO_NAME. BUG=b:174534548 TEST=emerge-kukui coreboot depthcharge chromeos-bootimage BRANCH=kukui Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Change-Id: I4b44b026bee4d3b58646eee207aea0120071dd46 --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/chromeos.c 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/48558/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index cff94da..b36ce87 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -83,4 +83,12 @@ default 0x1 if BOARD_GOOGLE_BURNET || BOARD_GOOGLE_ESCHE default 0x0 +config SPEAKER_GPIO_NAME + string + default "speaker enable" if BOARD_GOOGLE_JACUZZI || BOARD_GOOGLE_JUNIPER + default "speaker enable" if BOARD_GOOGLE_KAPPA || BOARD_GOOGLE_DAMU + default "rt1015p sdb" if BOARD_GOOGLE_KAKADU + default "rt1015p sdb" if BOARD_GOOGLE_JACUZZI_COMMON + default "speaker enable" + endif diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index c5810d1..3f15a3f 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -23,7 +23,7 @@ {EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, {EC_IRQ.id, ACTIVE_LOW, -1, "EC interrupt"}, {CR50_IRQ.id, ACTIVE_HIGH, -1, "TPM interrupt"}, - {GPIO_EN_SPK_AMP.id, ACTIVE_HIGH, -1, "speaker enable"}, + {GPIO_EN_SPK_AMP.id, ACTIVE_HIGH, -1, CONFIG_SPEAKER_GPIO_NAME}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b44b026bee4d3b58646eee207aea0120071dd46 Gerrit-Change-Number: 48558 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in em100[master]: Support 4-byte address mode in SPI traces
by Stefan Reinauer (Code Review) 15 Dec '20

15 Dec '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/48553 ) Change subject: Support 4-byte address mode in SPI traces ...................................................................... Support 4-byte address mode in SPI traces - Track address mode globally, so we can access the user presets when reading SPI traces. - Enable address mode switching based on the SPI opcodes 0xB7 / 0xE9 - Read additional address byte when appropriate and skip it in the data stream - Skip trace packets without valid data Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: Iec9f36356eb7e612a909855cda85dc0ce1b5adc0 --- M em100.c M em100.h M trace.c 3 files changed, 23 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/53/48553/1 diff --git a/em100.c b/em100.c index c4b6c01..ca6e683 100644 --- a/em100.c +++ b/em100.c @@ -29,6 +29,7 @@ TFILE *configs; char *database_version; int debug = 0; +int address_mode = 3; volatile sig_atomic_t exit_requested = 0; static struct em100 em100_state; @@ -835,7 +836,6 @@ int compatibility = 0; int bus = 0, device = 0; int firmware_is_dpfw = 0; - int address_mode = 0; unsigned int serial_number = 0; unsigned long address_offset = 0; unsigned int spi_start_address = 0; diff --git a/em100.h b/em100.h index d49339b..ecb74d2 100644 --- a/em100.h +++ b/em100.h @@ -197,6 +197,7 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) char *get_em100_file(const char *name); extern int debug; +extern int address_mode; extern volatile sig_atomic_t exit_requested; /* Chips */ diff --git a/trace.c b/trace.c index 0c6cdfd..108691b 100644 --- a/trace.c +++ b/trace.c @@ -128,6 +128,7 @@ {"exit 4-byte address mode", 0xe9, 0, 0}, {"enter quad i/o mode", 0x35, 0, 0}, {"exit quad i/o mode", 0xf5, 0, 0}, + {"read SFDP Table", 0x5a, 1, 0}, {"unknown command", 0xff, 0, 0} }; @@ -178,6 +179,11 @@ unsigned int j = additional_pad_bytes; additional_pad_bytes = 0; unsigned char cmd = data[2 + i*8]; + + if (cmd == 0x00) { + /* packet without valid data */ + continue; + } if (cmd == 0xff) { /* timestamp */ timestamp = data[2 + i*8 + 2]; @@ -201,16 +207,27 @@ if (counter == 0) start_timestamp = timestamp; + /* Special commands */ + switch (spi_command) { + case 0xb7: + address_mode = 4; + break; + case 0xe9: + address_mode = 3; + break; + } + /* set up address if used by this command*/ if (!spi_cmd_vals->uses_address) { j = 1; /* skip command byte */ } else { - address = (data[i * 8 + 5] << 16) + - (data[i * 8 + 6] << 8) + - data[i * 8 + 7]; + if (address_mode == 3) + address = (data[i * 8 + 5] << 16) + (data[i * 8 + 6] << 8) + data[i * 8 + 7]; + else + address = (data[i * 8 + 5] << 24) + (data[i * 8 + 6] << 16) + (data[i * 8 + 7] << 8) + data[i * 8 + 8]; /* skip command, address bytes, and padding */ - j = 4 + spi_cmd_vals->pad_bytes; + j = 1 + address_mode + spi_cmd_vals->pad_bytes; if (j > MAX_TRACE_BLOCKLENGTH) { additional_pad_bytes = j - MAX_TRACE_BLOCKLENGTH; -- To view, visit https://review.coreboot.org/c/em100/+/48553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Iec9f36356eb7e612a909855cda85dc0ce1b5adc0 Gerrit-Change-Number: 48553 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Furquan Shaikh (Code Review) 15 Dec '20

15 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48583 ) Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… File src/soc/intel/alderlake/chip.c: https://review.coreboot.org/c/coreboot/+/48583/7/src/soc/intel/alderlake/ch… PS7, Line 202: else if (dev->path.type == DEVICE_PATH_GPIO) : dev->ops = &soc_gpio_ops; > > > > It also relieves each SoC from duplicating the same code to set up GPIO device ops. […] I still think that it would be beneficial to have a separate chip for the GPIO device. Anyways, we can start with this and see how the use cases develop. -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 15 Dec 2020 00:57:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: hook up new gpio device in the soc chips
by Michael Niewöhner (Code Review) 15 Dec '20

15 Dec '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48583 to look at the new patch set (#10). Change subject: soc/intel: hook up new gpio device in the soc chips ...................................................................... soc/intel: hook up new gpio device in the soc chips This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/chip.c M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/chip.c M src/soc/intel/common/block/gpio/Makefile.inc M src/soc/intel/common/block/gpio/gpio.c A src/soc/intel/common/block/gpio/gpio_dev.c M src/soc/intel/common/block/include/intelblocks/gpio.h M src/soc/intel/elkhartlake/chip.c M src/soc/intel/icelake/chip.c M src/soc/intel/jasperlake/chip.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/chip.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/skx/chip.c 14 files changed, 71 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48583/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/48583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Gerrit-Change-Number: 48583 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit December 2020