coreboot-gerrit December 2020

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Change in coreboot[master]: mb/google/octopus/variants/casta: Add support zinitix touchpad
by shkim (Code Review) 15 Dec '20

15 Dec '20

Hello SH Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48634 to review the following change. Change subject: mb/google/octopus/variants/casta: Add support zinitix touchpad ...................................................................... mb/google/octopus/variants/casta: Add support zinitix touchpad This change adds support zinitix touchpad for casta/bluebird. BRANCH=firmware-octopus-11297.B BUG=b:175618033 TEST=built and verified touchpad worked on casta Change-Id: I1a8f562de19d1a8160d52c65400553f0c68393e0 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/casta/overridetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/48634/1 diff --git a/src/mainboard/google/octopus/variants/casta/overridetree.cb b/src/mainboard/google/octopus/variants/casta/overridetree.cb index 3f2a884..be322f5 100644 --- a/src/mainboard/google/octopus/variants/casta/overridetree.cb +++ b/src/mainboard/google/octopus/variants/casta/overridetree.cb @@ -137,6 +137,16 @@ register "probed" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""ZNT0000"" + register "generic.cid" = ""PNP0C50"" + register "generic.desc" = ""Zinitix Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0xE" + device i2c 40 on end + end end # - I2C 6 end -- To view, visit https://review.coreboot.org/c/coreboot/+/48634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8f562de19d1a8160d52c65400553f0c68393e0 Gerrit-Change-Number: 48634 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: dcm: mt8192: Enable DCM
by Yidi Lin (Code Review) 15 Dec '20

15 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46407 ) Change subject: WIP: dcm: mt8192: Enable DCM ...................................................................... WIP: dcm: mt8192: Enable DCM Enable DCM settings. /* INFRACFG_AO */ dcm_infracfg_ao_aximem_bus_dcm(on); dcm_infracfg_ao_infra_bus_dcm(on); dcm_infracfg_ao_infra_conn_bus_dcm(on); dcm_infracfg_ao_infra_rx_p2p_dcm(on); dcm_infracfg_ao_peri_bus_dcm(on); dcm_infracfg_ao_peri_module_dcm(on); /* INFRA_AO_BCRM */ dcm_infra_ao_bcrm_infra_bus_dcm(on); dcm_infra_ao_bcrm_peri_bus_dcm(on); /* INFRACFG_AO_MEM */ /* move to preloader */ /* dcm_infracfg_ao_mem_dcm_emi_group(on); */ Change-Id: I5528d176b6bb1f9a5960de981766235510e6ebf1 --- M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 2 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/46407/1 diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 09c4c471..35e8ff2 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -306,4 +306,59 @@ DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) +enum { + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = ((0x1f << 12) | \ + (0x1 << 17) | \ + (0x1 << 18)), + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = ((0x10 << 12) | \ + (0x1 << 17) | \ + (0x0 << 18)), + INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x1 << 3) | \ + (0x1 << 4) | \ + (0x1f << 5) | \ + (0x1f << 10) | \ + (0x1 << 20) | \ + (0x1 << 23) | \ + (0x1 << 30)), + INFRACFG_AO_INFRA_BUS_DCM_REG0_ON = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x0 << 3) | \ + (0x0 << 4) | \ + (0x10 << 5) | \ + (0x1 << 10) | \ + (0x1 << 20) | \ + (0x1 << 23) | \ + (0x1 << 30)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK = ((0x1 << 8)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON = ((0x1 << 8)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK = ((0x1 << 8)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON = ((0x0 << 8)), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK = ((0xf << 0)), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON = ((0x0 << 0)), + INFRACFG_AO_PERI_BUS_DCM_REG0_MASK = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x1 << 3) | \ + (0x1 << 4) | \ + (0x1f << 5) | \ + (0x1f << 10) | \ + (0x1f << 15) | \ + (0x1 << 20) | \ + (0x1 << 21)), + INFRACFG_AO_PERI_BUS_DCM_REG0_ON = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x0 << 3) | \ + (0x0 << 4) | \ + (0x1f << 5) | \ + (0x0 << 10) | \ + (0x1f << 15) | \ + (0x1 << 20) | \ + (0x1 << 21)), + INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK = ((0x1 << 29) | \ + (0x1 << 31)), + INFRACFG_AO_PERI_MODULE_DCM_REG0_ON = ((0x1 << 29) | \ + (0x1 << 31)), +}; + #endif /* SOC_MEDIATEK_MT8192_PLL_H */ diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 24cfafd..0366cd6 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -427,6 +427,27 @@ /* enable infrasys DCM */ setbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + // dcm_infracfg_ao_aximem_bus_dcm + clrsetbits_le32(&mt8192_infracfg->infra_aximem_idle_bit_en_0, + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK, INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON); + // dcm_infracfg_ao_infra_bus_dcm + clrsetbits_le32(&mt8192_infracfg->infra_bus_dcm_ctrl, + INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK, INFRACFG_AO_INFRA_BUS_DCM_REG0_ON); + // dcm_infracfg_ao_infra_conn_bus_dcm + clrsetbits_le32(&mt8192_infracfg->module_sw_cg_2_set, + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON); + clrsetbits_le32(&mt8192_infracfg->module_sw_cg_2_clr, + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON); + // dcm_infracfg_ao_infra_rx_p2p_dcm + clrsetbits_le32(&mt8192_infracfg->p2p_rx_clk_on, + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK, INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON); + // dcm_infracfg_ao_peri_bus_dcm + clrsetbits_le32(&mt8192_infracfg->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_BUS_DCM_REG0_MASK, INFRACFG_AO_PERI_BUS_DCM_REG0_ON); + // dcm_infracfg_ao_peri_module_dcm + clrsetbits_le32(&mt8192_infracfg->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK, INFRACFG_AO_PERI_MODULE_DCM_REG0_ON); + /* initialize SPM request */ setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff); clrsetbits32(&mtk_topckgen->clk_scp_cfg_1, 0x100c, 0x3); -- To view, visit https://review.coreboot.org/c/coreboot/+/46407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5528d176b6bb1f9a5960de981766235510e6ebf1 Gerrit-Change-Number: 46407 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: ufs: disable refer clk
by Yidi Lin (Code Review) 15 Dec '20

15 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46408 ) Change subject: soc/mediatek/mt8192: ufs: disable refer clk ...................................................................... soc/mediatek/mt8192: ufs: disable refer clk ufs refer clk is enabled by default, which will cause the UFSHCI hold the SPM signal and lead to suspend fail. Since ufs kernel driver is not built-in, so disable refer clk in coreboot stage. Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Signed-off-by: Chaotian Jing <chaotian.jing(a)mediatek.com> Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 33 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 4ce5e6a..7b098e8 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -48,6 +48,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c ramstage-y += devapc.c +ramstage-y += ufs.c ramstage-y += mcupm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 19728a3..85eac5b 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -47,6 +47,7 @@ SPI7_BASE = IO_PHYS + 0x0101E000, SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, SFLASH_REG_BASE = IO_PHYS + 0x01234000, + UFSHCI_BASE = IO_PHYS + 0x01270000, EFUSEC_BASE = IO_PHYS + 0x01C10000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, IOCFG_BM_BASE = IO_PHYS + 0x01D10000, diff --git a/src/soc/mediatek/mt8192/include/soc/ufs.h b/src/soc/mediatek/mt8192/include/soc/ufs.h new file mode 100644 index 0000000..259aaf4 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/ufs.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_UFS_H +#define SOC_MEDIATEK_MT8192_UFS_H + +#include <device/mmio.h> +#include <soc/addressmap.h> + +void ufs_disable_refclk(void); + +enum ufshci_offset { + REG_UFS_REFCLK_CTRL = 0x144, +}; + +#define UFS_REFCLK_CTRL (ufshci_base + (unsigned long)REG_UFS_REFCLK_CTRL) + +#endif /* SOC_MEDIATEK_MT8192_UFS_H */ diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index ba153f2..c865e6f 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -6,6 +6,7 @@ #include <symbols.h> #include <soc/devapc.h> #include <soc/mcupm.h> +#include <soc/ufs.h> static void soc_read_resources(struct device *dev) { @@ -16,7 +17,8 @@ { mtk_mmu_disable_l2c_sram(); dapc_init(); - mcupm_init(); + mcupm_init(); + ufs_disable_refclk(); } static struct device_operations soc_ops = { diff --git a/src/soc/mediatek/mt8192/ufs.c b/src/soc/mediatek/mt8192/ufs.c new file mode 100644 index 0000000..854ef4c --- /dev/null +++ b/src/soc/mediatek/mt8192/ufs.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ufs.h> + +static unsigned long ufshci_base = (unsigned long)UFSHCI_BASE; + +void ufs_disable_refclk(void) +{ + /* disable ref clock to let UFSHCI release SPM signal */ + write32((void*)UFS_REFCLK_CTRL, 0); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 Gerrit-Change-Number: 46408 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 31

Change in coreboot[master]: soc/mediatek/mt8192: Initialize audio pll tuner frequency
by Yidi Lin (Code Review) 15 Dec '20

15 Dec '20

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46400 to review the following change. Change subject: soc/mediatek/mt8192: Initialize audio pll tuner frequency ...................................................................... soc/mediatek/mt8192: Initialize audio pll tuner frequency Add AUDPLL TUNER init code. TEST=Boots correctly on MT8192EVB. Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: I1f1b5b55a0a16d42311b16b89b15b31e1aa04670 --- M src/soc/mediatek/mt8192/pll.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46400/1 diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 11750d2..24cfafd 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -392,6 +392,10 @@ for (i = 0; i < ARRAY_SIZE(rates); i++) pll_set_rate(&plls[rates[i].id], rates[i].rate); + /* AUDPLL Tuner Frequency Set */ + write32(&mtk_apmixed->apll1_tuner_con0, read32(&mtk_apmixed->apll1_con2) + 1); + write32(&mtk_apmixed->apll2_tuner_con0, read32(&mtk_apmixed->apll2_con2) + 1); + /* xPLL Frequency Enable */ for (i = 0; i < APMIXED_PLL_MAX; i++) { if (i == APMIXED_USBPLL) -- To view, visit https://review.coreboot.org/c/coreboot/+/46400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f1b5b55a0a16d42311b16b89b15b31e1aa04670 Gerrit-Change-Number: 46400 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/intel/xeon_sp: Lock down DMIC
by Arthur Heymans (Code Review) 15 Dec '20

15 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47449 ) Change subject: soc/intel/xeon_sp: Lock down DMIC ...................................................................... soc/intel/xeon_sp: Lock down DMIC This is required for CBnT. Change-Id: I290742c163f5f067c8d529ddca8e2d8572ab6e6a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/pch.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/47449/1 diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c index 5427952..2b35223 100644 --- a/src/soc/intel/xeon_sp/pch.c +++ b/src/soc/intel/xeon_sp/pch.c @@ -39,6 +39,9 @@ reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1; pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); + + reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK); } void bootblock_pch_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/47449 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I290742c163f5f067c8d529ddca8e2d8572ab6e6a Gerrit-Change-Number: 47449 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in em100[master]: em100: Add trace console command
by Stefan Reinauer (Code Review) 15 Dec '20

15 Dec '20

Hello Duncan Laurie, I'd like you to do a code review. Please visit https://review.coreboot.org/c/em100/+/48599 to review the following change. Change subject: em100: Add trace console command ...................................................................... em100: Add trace console command Add a command which allows a realtime console output from em100 when using the CONFIG_SPI_FLASH_CONSOLE option in coreboot. Provide the offset and lenght of the region defined in the FMAP and it will watch for the host to write to that area, and when it sees a write it will print it to stdout. Change-Id: I78162585bcd73a3bb3a8aa590f43a96092946109 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M em100.c M em100.h M trace.c 3 files changed, 135 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/99/48599/1 diff --git a/em100.c b/em100.c index 4b0a121..f808ed6 100644 --- a/em100.c +++ b/em100.c @@ -787,6 +787,8 @@ {"list-devices", 0, 0, 'l'}, {"update-files", 0, 0, 'U'}, {"terminal", 0, 0, 'T'}, + {"traceconsole", 0, 0, 'R'}, + {"length", 1, 0, 'L'}, {"compatible", 0, 0, 'C'}, {NULL, 0, 0, 0} }; @@ -807,6 +809,8 @@ " -t|--trace: trace mode\n" " -O|--offset HEX_VAL: address offset for trace mode\n" " -T|--terminal: terminal mode\n" + " -R|--traceconsole: trace console mode\n" + " -L|--length HEX_VAL: length of buffer for traceconsole mode\n" " -F|--firmware-update FILE|auto: update EM100pro firmware (dangerous)\n" " -f|--firmware-dump FILE: export raw EM100pro firmware to file\n" " -g|--firmware-write FILE: export EM100pro firmware to DPFW file\n" @@ -832,18 +836,18 @@ const char *firmware_in = NULL, *firmware_out = NULL; const char *holdpin = NULL; int do_start = 0, do_stop = 0; - int verify = 0, trace = 0, terminal=0; + int verify = 0, trace = 0, terminal=0, traceconsole=0; int compatibility = 0; int bus = 0, device = 0; int firmware_is_dpfw = 0; unsigned int serial_number = 0; - unsigned long address_offset = 0; + unsigned long address_offset = 0, address_length = 0; unsigned int spi_start_address = 0; const char *voltage = NULL; struct sigaction signal_action; struct em100 *em100 = &em100_state; - while ((opt = getopt_long(argc, argv, "c:d:a:m:u:rsvtO:F:f:g:S:V:p:DCx:lUhT", + while ((opt = getopt_long(argc, argv, "c:d:a:m:u:rsvtO:F:f:g:S:V:p:DCx:lUhTRL:", longopts, &idx)) != -1) { switch (opt) { case 'c': @@ -919,6 +923,12 @@ case 'U': update_all_files(); return 0; + case 'R': + traceconsole = 1; + break; + case 'L': + sscanf(optarg, "%lx", &address_length); + break; case 'C': compatibility = 1; break; @@ -1206,7 +1216,7 @@ set_state(em100, 1); } - if (trace || terminal) { + if (trace || terminal || traceconsole) { int usb_errors = 0; if ((holdpin == NULL) && (!set_hold_pin_state(em100, 3))) { @@ -1220,7 +1230,7 @@ printf ("Starting "); - if (trace) { + if (trace || traceconsole) { reset_spi_trace(em100); printf("trace%s", terminal ? " & " : ""); } @@ -1234,13 +1244,18 @@ while (!exit_requested && usb_errors < MAX_USB_ERRORS) { int ret; - if (trace) { + + if (traceconsole) + ret = read_spi_trace_console(em100, address_offset, address_length); + else if (trace) ret = read_spi_trace(em100, terminal, address_offset); - } else { + else if (terminal) ret = read_spi_terminal(em100, 0); - } + if (ret == 0) usb_errors++; + if (ret < 0) + break; } if (usb_errors >= MAX_USB_ERRORS) printf("Error: Bailed out with too many USB errors.\n"); diff --git a/em100.h b/em100.h index ecb74d2..bf1bb87 100644 --- a/em100.h +++ b/em100.h @@ -172,6 +172,8 @@ unsigned long addr_offset); int read_spi_terminal(struct em100 *em100, int print_counter); int init_spi_terminal(struct em100 *em100); +int read_spi_trace_console(struct em100 *em100, unsigned long addr_offset, + unsigned long addr_len); /* Archive handling */ typedef struct { diff --git a/trace.c b/trace.c index 88265b5..7fe6ab8 100644 --- a/trace.c +++ b/trace.c @@ -305,6 +305,116 @@ return 1; } +int read_spi_trace_console(struct em100 *em100, unsigned long addr_offset, + unsigned long addr_len) +{ + unsigned char reportdata[REPORT_BUFFER_COUNT][REPORT_BUFFER_LENGTH] = + {{0}}; + unsigned char *data; + unsigned int count, i, report; + static int additional_pad_bytes = 0; + static unsigned int address = 0; + static int do_write = 0; + static struct spi_cmd_values *spi_cmd_vals = &spi_command_list[3]; + int addr_bytes = 4; + + if (addr_offset == 0) { + printf("Address offset for console buffer required\n"); + return -1; + } + if (addr_len == 0) { + printf("Console buffer length required\n"); + return -1; + } + + if (!read_report_buffer(em100, reportdata)) + return -1; + + for (report = 0; report < REPORT_BUFFER_COUNT; report++) { + data = &reportdata[report][0]; + count = (data[0] << 8) | data[1]; + if (!count) + continue; + if (count > 1023) { + printf("Warning: EM100pro sends too much data: %d.\n", count); + count = 1023; + } + for (i = 0; i < count; i++) { + unsigned int j = additional_pad_bytes; + unsigned int address_bytes = 0; + additional_pad_bytes = 0; + unsigned char cmd = data[2 + i*8]; + + /* from here, it must be data */ + if (cmd != cmdid) { + unsigned char spi_command = data[i * 8 + 4]; + spi_cmd_vals = get_command_vals(spi_command); + + /* new command */ + cmdid = cmd; + + /* set up address if used by this command */ + if (!spi_cmd_vals->uses_address) { + j = 1; /* skip command byte */ + } else { + /* If address_mode > 1 -> always decode 4 bytes */ + address_bytes = + (spi_cmd_vals->uses_address == 1) ? address_mode : 4; + + if (address_mode == 3) + address = (data[i * 8 + 5] << 16) + (data[i * 8 + 6] << 8) + data[i * 8 + 7]; + else + address = (data[i * 8 + 5] << 24) + (data[i * 8 + 6] << 16) + (data[i * 8 + 7] << 8) + data[i * 8 + 8]; + + /* skip command, address bytes, and padding */ + j = address_bytes + 1 + spi_cmd_vals->pad_bytes; + if (j > MAX_TRACE_BLOCKLENGTH) { + additional_pad_bytes = j - + MAX_TRACE_BLOCKLENGTH; + j = MAX_TRACE_BLOCKLENGTH; + } + } + +#if 0 + if (spi_cmd_vals->uses_address) + printf("0x%02x @ 0x%08x (%s)\n", + spi_command, address, spi_cmd_vals->cmd_name); + else + printf("0x%02x (%s)\n", + spi_command, spi_cmd_vals->cmd_name); +#endif + + curpos = 0; + if (spi_command == 0x02) + do_write = 1; + else + do_write = 0; + } + + if (do_write == 0 || + (spi_cmd_vals->uses_address == 0 || + address < addr_offset || + address > (addr_offset + addr_len))) { + curpos = data[2 + i*8 + 1] + 0x10; + continue; + } + + /* this exploits 8bit wrap around in curpos */ + unsigned char blocklen = (data[2 + i*8 + 1] - curpos); + blocklen /= 8; + + for (; j < blocklen; j++) { + printf("%c", data[i * 8 + addr_bytes + j]); + } + + /* this is because the em100 counts funny */ + curpos = data[2 + i*8 + 1] + 0x10; + fflush(stdout); + } + } + return 1; +} + #define UFIFO_SIZE 512 #define UFIFO_TIMEOUT 0x00 -- To view, visit https://review.coreboot.org/c/em100/+/48599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I78162585bcd73a3bb3a8aa590f43a96092946109 Gerrit-Change-Number: 48599 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration
by Felix Singer (Code Review) 15 Dec '20

15 Dec '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48325 ) Change subject: soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/48325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5 Gerrit-Change-Number: 48325 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Dec 2020 01:39:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration
by Benjamin Doron (Code Review) 15 Dec '20

15 Dec '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48325 ) Change subject: soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/48325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5 Gerrit-Change-Number: 48325 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Dec 2020 00:04:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [WIP] soc/amd/picasso/smi: add missing bits to GEVENT_MASK
by Felix Held (Code Review) 15 Dec '20

15 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48483 ) Change subject: [WIP] soc/amd/picasso/smi: add missing bits to GEVENT_MASK ...................................................................... [WIP] soc/amd/picasso/smi: add missing bits to GEVENT_MASK GEVENT_MASK should cover all GEVENT pins, but was missing SMITYPE_G_AGPIO9 and SMITYPE_G_AGPIO8. TODO: Find out if this is intentional or a bug. Change-Id: Ia676476e2d2cf468d82d6d90e9fc11d34f56f153 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/include/soc/smi.h 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/48483/1 diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index ad7edbc..e86809e 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -64,7 +64,9 @@ | (1 << SMITYPE_G_FANIN0) \ | (1 << SMITYPE_G_SYSRESET_L) \ | (1 << SMITYPE_G_AGPIO40) \ - | (1 << SMITYPE_G_PWR_BTN_L)) + | (1 << SMITYPE_G_PWR_BTN_L) \ + | (1 << SMITYPE_G_AGPIO9) \ + | (1 << SMITYPE_G_AGPIO8)) #define SMITYPE_MP2_WAKE 24 #define SMITYPE_MP2_GPIO0 25 #define SMITYPE_ESPI_SYS 26 -- To view, visit https://review.coreboot.org/c/coreboot/+/48483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia676476e2d2cf468d82d6d90e9fc11d34f56f153 Gerrit-Change-Number: 48483 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: [WIP] soc/amd/common/block/acpimmio: Redo acpimmio for psp_verstage a...
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42523 ) Change subject: [WIP] soc/amd/common/block/acpimmio: Redo acpimmio for psp_verstage again ...................................................................... [WIP] soc/amd/common/block/acpimmio: Redo acpimmio for psp_verstage again Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/Makefile.inc M src/soc/amd/common/block/acpimmio/mmio_util.c D src/soc/amd/common/block/acpimmio/mmio_util_psp.c A src/soc/amd/common/block/acpimmio/psp_verstage_stub.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h D src/soc/amd/common/block/include/amdblocks/acpimmio_psp.h 7 files changed, 67 insertions(+), 245 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/42523/1 diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc index 13864e4..28d78d5 100644 --- a/src/soc/amd/common/block/acpimmio/Makefile.inc +++ b/src/soc/amd/common/block/acpimmio/Makefile.inc @@ -13,5 +13,5 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO),y) verstage-$(CONFIG_ARCH_VERSTAGE_X86_32) += biosram.c verstage-$(CONFIG_ARCH_VERSTAGE_X86_32) += mmio_util.c -verstage-$(CONFIG_ARCH_VERSTAGE_ARM) += mmio_util_psp.c +verstage-$(CONFIG_ARCH_VERSTAGE_ARM) += mmio_util.c endif diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index c5f82f9..2bfa878 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -2,9 +2,12 @@ #include <types.h> #include <arch/io.h> -#include <amdblocks/acpimmio_map.h> #include <amdblocks/acpimmio.h> +#if CONSTANT_ACPIMMIO_BASE_ADDRESS +#include <amdblocks/acpimmio_map.h> +#endif + DECLARE_ACPIMMIO(acpimmio_sm_pci, SM_PCI); DECLARE_ACPIMMIO(acpimmio_gpio_100, GPIO_100); DECLARE_ACPIMMIO(acpimmio_smi, SMI); diff --git a/src/soc/amd/common/block/acpimmio/mmio_util_psp.c b/src/soc/amd/common/block/acpimmio/mmio_util_psp.c deleted file mode 100644 index 75f71e4..0000000 --- a/src/soc/amd/common/block/acpimmio/mmio_util_psp.c +++ /dev/null @@ -1,163 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <arch/io.h> -#include <device/mmio.h> -#include <amdblocks/acpimmio.h> - -static uintptr_t iomux_bar; - -void iomux_set_bar(void *bar) -{ - iomux_bar = (uintptr_t)bar; -} - -u8 iomux_read8(u8 reg) -{ - return read8((void *)(iomux_bar + reg)); -} - -u16 iomux_read16(u8 reg) -{ - return read16((void *)(iomux_bar + reg)); -} - -u32 iomux_read32(u8 reg) -{ - return read32((void *)(iomux_bar + reg)); -} - -void iomux_write8(u8 reg, u8 value) -{ - write8((void *)(iomux_bar + reg), value); -} - -void iomux_write16(u8 reg, u16 value) -{ - write16((void *)(iomux_bar + reg), value); -} - -void iomux_write32(u8 reg, u32 value) -{ - write32((void *)(iomux_bar + reg), value); -} - -static uintptr_t misc_bar; - -void misc_set_bar(void *bar) -{ - misc_bar = (uintptr_t)bar; -} - -u8 misc_read8(u8 reg) -{ - return read8((void *)(misc_bar + reg)); -} - -u16 misc_read16(u8 reg) -{ - return read16((void *)(misc_bar + reg)); -} - -u32 misc_read32(u8 reg) -{ - return read32((void *)(misc_bar + reg)); -} - -void misc_write8(u8 reg, u8 value) -{ - write8((void *)(misc_bar + reg), value); -} - -void misc_write16(u8 reg, u16 value) -{ - write16((void *)(misc_bar + reg), value); -} - -void misc_write32(u8 reg, u32 value) -{ - write32((void *)(misc_bar + reg), value); -} - -static uintptr_t gpio_bar; - -void gpio_set_bar(void *bar) -{ - gpio_bar = (uintptr_t)bar; -} - -void *gpio_get_bar(void) -{ - return (void *)gpio_bar; -} - -static uintptr_t aoac_bar; - -void aoac_set_bar(void *bar) -{ - aoac_bar = (uintptr_t)bar; -} - -u8 aoac_read8(u8 reg) -{ - return read8((void *)(aoac_bar + reg)); -} - -void aoac_write8(u8 reg, u8 value) -{ - write8((void *)(aoac_bar + reg), value); -} - -static uintptr_t io_bar; - -void io_set_bar(void *bar) -{ - io_bar = (uintptr_t)bar; -} - -u8 io_read8(u16 reg) -{ - return read8((void *)(io_bar + reg)); -} - -void io_write8(u16 reg, u8 value) -{ - write8((void *)(io_bar + reg), value); -} - -/* PM registers are accessed a byte at a time via CD6/CD7 */ -uint8_t pm_io_read8(uint8_t reg) -{ - outb(reg, PM_INDEX); - return inb(PM_DATA); -} - -uint16_t pm_io_read16(uint8_t reg) -{ - return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg); -} - -uint32_t pm_io_read32(uint8_t reg) -{ - return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg); -} - -void pm_io_write8(uint8_t reg, uint8_t value) -{ - outb(reg, PM_INDEX); - outb(value, PM_DATA); -} - -void pm_io_write16(uint8_t reg, uint16_t value) -{ - pm_io_write8(reg, value & 0xff); - value >>= 8; - pm_io_write8(reg + sizeof(uint8_t), value & 0xff); -} - -void pm_io_write32(uint8_t reg, uint32_t value) -{ - pm_io_write16(reg, value & 0xffff); - value >>= 16; - pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); -} diff --git a/src/soc/amd/common/block/acpimmio/psp_verstage_stub.c b/src/soc/amd/common/block/acpimmio/psp_verstage_stub.c new file mode 100644 index 0000000..9c74f8f --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/psp_verstage_stub.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpimmio.h> + +static void iomux_set_bar(void *bar) +{ + acpimmio_iomux_bar = bar; +} + +static void misc_set_bar(void *bar) +{ + acpimmio_misc_bar = bar; +} + +static void gpio_set_bar(void *bar) +{ + acpimmio_gpio0_bar = bar; +} + +static void aoac_set_bar(void *bar) +{ + acpimmio_aoac_bar = bar; +} + +static void io_set_bar(void *bar) +{ + acpimmio_io_bar = bar; +} diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 3caed11..3f00ae2 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -6,6 +6,40 @@ #include <device/mmio.h> #include <types.h> +/* For x86 base is constant, while PSP does mapping runtime. */ +#define CONSTANT_ACPIMMIO_BASE_ADDRESS ENV_X86 + +#if CONSTANT_ACPIMMIO_BASE_ADDRESS +#define MAYBE_CONST const +#define DECLARE_ACPIMMIO(ptr, bank) \ + uint8_t *const ptr = (void *)(AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK) +#else +#define MAYBE_CONST +#define DECLARE_ACPIMMIO(ptr, bank) uint8_t *ptr +#endif + +extern uint8_t *MAYBE_CONST acpimmio_gpio_100; +extern uint8_t *MAYBE_CONST acpimmio_sm_pci; +extern uint8_t *MAYBE_CONST acpimmio_smi; +extern uint8_t *MAYBE_CONST acpimmio_pmio; +extern uint8_t *MAYBE_CONST acpimmio_pmio2; +extern uint8_t *MAYBE_CONST acpimmio_biosram; +extern uint8_t *MAYBE_CONST acpimmio_cmosram; +extern uint8_t *MAYBE_CONST acpimmio_cmos; +extern uint8_t *MAYBE_CONST acpimmio_acpi; +extern uint8_t *MAYBE_CONST acpimmio_asf; +extern uint8_t *MAYBE_CONST acpimmio_smbus; +extern uint8_t *MAYBE_CONST acpimmio_wdt; +extern uint8_t *MAYBE_CONST acpimmio_hpet; +extern uint8_t *MAYBE_CONST acpimmio_iomux; +extern uint8_t *MAYBE_CONST acpimmio_misc; +extern uint8_t *MAYBE_CONST acpimmio_dpvga; +extern uint8_t *MAYBE_CONST acpimmio_gpio0; +extern uint8_t *MAYBE_CONST acpimmio_xhci_pm; +extern uint8_t *MAYBE_CONST acpimmio_acdc_tmr; +extern uint8_t *MAYBE_CONST acpimmio_aoac; + +#undef MAYBE_CONST /* Enable the AcpiMmio range at 0xfed80000 */ @@ -23,13 +57,6 @@ void pm_io_write16(uint8_t reg, uint16_t value); void pm_io_write32(uint8_t reg, uint32_t value); -#if !ENV_X86 - -#include <amdblocks/acpimmio_psp.h> - -#else - -#include <amdblocks/acpimmio_map.h> static inline uint8_t sm_pci_read8(uint8_t reg) { @@ -384,6 +411,4 @@ write8(acpimmio_aoac + reg, value); } -#endif /* ENV_X86 */ - #endif /* __AMDBLOCKS_ACPIMMIO_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 912e891..5d71287 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -112,20 +112,8 @@ * across family/model products. */ -/* For x86 base is constant, while PSP does mapping runtime. */ -#define CONSTANT_ACPIMMIO_BASE_ADDRESS ENV_X86 - #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 -#if CONSTANT_ACPIMMIO_BASE_ADDRESS -#define MAYBE_CONST const -#define DECLARE_ACPIMMIO(ptr, bank) \ - uint8_t *const ptr = (void *)(AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK) -#else -#define MAYBE_CONST -#define DECLARE_ACPIMMIO(ptr, bank) uint8_t *ptr -#endif - #ifdef __ACPI__ /* ASL fails on additions. */ @@ -161,29 +149,6 @@ #define ACPIMMIO_ASF_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ASF_BANK) #define ACPIMMIO_SMBUS_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_SMBUS_BANK) -extern uint8_t *MAYBE_CONST acpimmio_gpio_100; -extern uint8_t *MAYBE_CONST acpimmio_sm_pci; -extern uint8_t *MAYBE_CONST acpimmio_smi; -extern uint8_t *MAYBE_CONST acpimmio_pmio; -extern uint8_t *MAYBE_CONST acpimmio_pmio2; -extern uint8_t *MAYBE_CONST acpimmio_biosram; -extern uint8_t *MAYBE_CONST acpimmio_cmosram; -extern uint8_t *MAYBE_CONST acpimmio_cmos; -extern uint8_t *MAYBE_CONST acpimmio_acpi; -extern uint8_t *MAYBE_CONST acpimmio_asf; -extern uint8_t *MAYBE_CONST acpimmio_smbus; -extern uint8_t *MAYBE_CONST acpimmio_wdt; -extern uint8_t *MAYBE_CONST acpimmio_hpet; -extern uint8_t *MAYBE_CONST acpimmio_iomux; -extern uint8_t *MAYBE_CONST acpimmio_misc; -extern uint8_t *MAYBE_CONST acpimmio_dpvga; -extern uint8_t *MAYBE_CONST acpimmio_gpio0; -extern uint8_t *MAYBE_CONST acpimmio_xhci_pm; -extern uint8_t *MAYBE_CONST acpimmio_acdc_tmr; -extern uint8_t *MAYBE_CONST acpimmio_aoac; - -#undef MAYBE_CONST - #endif #endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_psp.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_psp.h deleted file mode 100644 index b8ca7b5..0000000 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_psp.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef __AMDBLOCKS_ACPIMMIO_PSP_H__ -#define __AMDBLOCKS_ACPIMMIO_PSP_H__ - -#include <device/mmio.h> -#include <types.h> - -void iomux_set_bar(void *bar); -void *iomux_get_bar(void); -void misc_set_bar(void *bar); -void *misc_get_bar(void); -void gpio_set_bar(void *bar); -void *gpio_get_bar(void); -void aoac_set_bar(void *bar); -void *aoac_get_bar(void); -void io_set_bar(void *bar); -u8 io_read8(u16 reg); -void io_write8(u16 reg, u8 value); - -u8 iomux_read8(u8 reg); -u16 iomux_read16(u8 reg); -u32 iomux_read32(u8 reg); -void iomux_write8(u8 reg, u8 value); -void iomux_write16(u8 reg, u16 value); -void iomux_write32(u8 reg, u32 value); -u8 misc_read8(u8 reg); -u16 misc_read16(u8 reg); -u32 misc_read32(u8 reg); -void misc_write8(u8 reg, u8 value); -void misc_write16(u8 reg, u16 value); -void misc_write32(u8 reg, u32 value); -u8 aoac_read8(u8 reg); -void aoac_write8(u8 reg, u8 value); - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60 Gerrit-Change-Number: 42523 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2020