coreboot-gerrit December 2020

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Change in coreboot[master]: soc/amd/common/gpio_banks: Drop underscore in __gpio
by Kyösti Mälkki (Code Review) 16 Dec '20

16 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48635 ) Change subject: soc/amd/common/gpio_banks: Drop underscore in __gpio ...................................................................... soc/amd/common/gpio_banks: Drop underscore in __gpio The local function names were chose such that they don't collide with <gpio.h> so the prefix is unnecessary. Change-Id: I4799a6d6b87e8081324d88b0773e61cbda0d4cfb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/48635/1 diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index a5f0eaf..8e340a3 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -94,7 +94,7 @@ return (uintptr_t)gpio_ctrl_ptr(gpio_num); } -static void __gpio_update32(gpio_t gpio_num, uint32_t mask, uint32_t or) +static void gpio_update32(gpio_t gpio_num, uint32_t mask, uint32_t or) { uint32_t reg; @@ -105,31 +105,31 @@ } /* Set specified bits of a register to match those of ctrl. */ -static void __gpio_setbits32(gpio_t gpio_num, uint32_t mask, uint32_t ctrl) +static void gpio_setbits32(gpio_t gpio_num, uint32_t mask, uint32_t ctrl) { - __gpio_update32(gpio_num, ~mask, ctrl & mask); + gpio_update32(gpio_num, ~mask, ctrl & mask); } -static void __gpio_and32(gpio_t gpio_num, uint32_t mask) +static void gpio_and32(gpio_t gpio_num, uint32_t mask) { - __gpio_update32(gpio_num, mask, 0); + gpio_update32(gpio_num, mask, 0); } -static void __gpio_or32(gpio_t gpio_num, uint32_t or) +static void gpio_or32(gpio_t gpio_num, uint32_t or) { - __gpio_update32(gpio_num, -1UL, or); + gpio_update32(gpio_num, -1UL, or); } static void master_switch_clr(uint32_t mask) { const uint8_t master_reg = GPIO_MASTER_SWITCH / sizeof(uint32_t); - __gpio_and32(master_reg, ~mask); + gpio_and32(master_reg, ~mask); } static void master_switch_set(uint32_t or) { const uint8_t master_reg = GPIO_MASTER_SWITCH / sizeof(uint32_t); - __gpio_or32(master_reg, or); + gpio_or32(master_reg, or); } int gpio_get(gpio_t gpio_num) @@ -142,27 +142,27 @@ void gpio_set(gpio_t gpio_num, int value) { - __gpio_setbits32(gpio_num, GPIO_OUTPUT_VALUE, value ? GPIO_OUTPUT_VALUE : 0); + gpio_setbits32(gpio_num, GPIO_OUTPUT_VALUE, value ? GPIO_OUTPUT_VALUE : 0); } void gpio_input_pulldown(gpio_t gpio_num) { - __gpio_setbits32(gpio_num, GPIO_PULL_MASK, GPIO_PULLDOWN_ENABLE); + gpio_setbits32(gpio_num, GPIO_PULL_MASK, GPIO_PULLDOWN_ENABLE); } void gpio_input_pullup(gpio_t gpio_num) { - __gpio_setbits32(gpio_num, GPIO_PULL_MASK, GPIO_PULLUP_ENABLE); + gpio_setbits32(gpio_num, GPIO_PULL_MASK, GPIO_PULLUP_ENABLE); } void gpio_input(gpio_t gpio_num) { - __gpio_and32(gpio_num, ~GPIO_OUTPUT_ENABLE); + gpio_and32(gpio_num, ~GPIO_OUTPUT_ENABLE); } void gpio_output(gpio_t gpio_num, int value) { - __gpio_or32(gpio_num, GPIO_OUTPUT_ENABLE); + gpio_or32(gpio_num, GPIO_OUTPUT_ENABLE); gpio_set(gpio_num, value); } @@ -217,9 +217,9 @@ soc_gpio_hook(gpio, mux); - __gpio_setbits32(gpio, PAD_CFG_MASK, control); + gpio_setbits32(gpio, PAD_CFG_MASK, control); /* Clear interrupt and wake status (write 1-to-clear bits) */ - __gpio_or32(gpio, GPIO_INT_STATUS | GPIO_WAKE_STATUS); + gpio_or32(gpio, GPIO_INT_STATUS | GPIO_WAKE_STATUS); if (control_flags == 0) continue; -- To view, visit https://review.coreboot.org/c/coreboot/+/48635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4799a6d6b87e8081324d88b0773e61cbda0d4cfb Gerrit-Change-Number: 48635 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Update SPD table for drobit
by Zhuohao Lee (Code Review) 16 Dec '20

16 Dec '20

Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48496 ) Change subject: mb/google/volteer: Update SPD table for drobit ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd9439f8449856d4ec6798a4e4310dd139bce05f Gerrit-Change-Number: 48496 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 16 Dec 2020 13:34:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Add GPIO to drobit support
by Zhuohao Lee (Code Review) 16 Dec '20

16 Dec '20

Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48497 ) Change subject: mb/google/volteer: Add GPIO to drobit support ...................................................................... Patch Set 3: (3 comments) https://review.coreboot.org/c/coreboot/+/48497/3/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/drobit/gpio.c: https://review.coreboot.org/c/coreboot/+/48497/3/src/mainboard/google/volte… PS3, Line 85: /* F11 : THC1_SPI2_CLK ==> FPMCU_BOOT1 */ : PAD_CFG_GPO(GPP_F11, 0, DEEP), This pin is EN_PP3300_WWAN https://review.coreboot.org/c/coreboot/+/48497/3/src/mainboard/google/volte… PS3, Line 118: /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ : PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), : /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ : PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), : /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ : PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), : /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ : PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), Do you use soundwire? It looks like those pins weren't be used from the schematics. https://review.coreboot.org/c/coreboot/+/48497/3/src/mainboard/google/volte… PS3, Line 136: early_gpio_table Please add "PAD_CFG_GPO(GPP_A13, 0, DEEP)," to early_gpio_table, please refer to https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… -- To view, visit https://review.coreboot.org/c/coreboot/+/48497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54ba182c6da3db282961b3c72a4d2d11d1001e95 Gerrit-Change-Number: 48497 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Wed, 16 Dec 2020 13:33:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Update galtic device tree
by Frank Chu (Code Review) 16 Dec '20

16 Dec '20

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48656 to look at the new patch set (#4). Change subject: mb/google/dedede: Update galtic device tree ...................................................................... mb/google/dedede: Update galtic device tree Update galtic device tree override to match schematics. BUG=b:170913840 BRANCH=none TEST=emerge-dedede coreboot Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I270cd2a9783030ad3a080b9cfda8a133e801c5ce --- M src/mainboard/google/dedede/variants/galtic/overridetree.cb 1 file changed, 106 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/48656/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/48656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I270cd2a9783030ad3a080b9cfda8a133e801c5ce Gerrit-Change-Number: 48656 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede: Update galtic device tree
by Frank Chu (Code Review) 16 Dec '20

16 Dec '20

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48656 to look at the new patch set (#3). Change subject: mb/google/dedede: Update galtic device tree ...................................................................... mb/google/dedede: Update galtic device tree Update galtic device tree override to match schematics. BUG=b:170913840 BRANCH=none TEST=emerge-dedede coreboot Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I270cd2a9783030ad3a080b9cfda8a133e801c5ce --- M src/mainboard/google/dedede/variants/galtic/overridetree.cb 1 file changed, 106 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/48656/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/48656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I270cd2a9783030ad3a080b9cfda8a133e801c5ce Gerrit-Change-Number: 48656 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede: Update SPD table for galtic
by Frank Chu (Code Review) 16 Dec '20

16 Dec '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48655 to look at the new patch set (#2). Change subject: mb/google/dedede: Update SPD table for galtic ...................................................................... mb/google/dedede: Update SPD table for galtic galtic memory table as follow: value Vendor Part number 0x00 MICRON MT53E512M32D2NP-046 WT:E 0x00 HYNIX H9HCNNNBKMMLXR-NEE 0x01 MICRON MT53E1G32D2NP-046 WT:A 0x02 HYNIX H9HCNNNCPMMLXR-NEE BUG=b:170913840 BRANCH=none TEST=emerge-dedede coreboot Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I30b8fe3f14e1af7bb5760530477f9311c6a4ee62 --- M src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc M src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt 3 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/48655/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30b8fe3f14e1af7bb5760530477f9311c6a4ee62 Gerrit-Change-Number: 48655 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede: Update galtic device tree
by Frank Chu (Code Review) 16 Dec '20

16 Dec '20

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48656 to look at the new patch set (#2). Change subject: mb/google/dedede: Update galtic device tree ...................................................................... mb/google/dedede: Update galtic device tree Update galtic device tree override to match schematics. BUG=b:170913840 BRANCH=none TEST=emerge-dedede coreboot Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I270cd2a9783030ad3a080b9cfda8a133e801c5ce --- M src/mainboard/google/dedede/variants/galtic/overridetree.cb 1 file changed, 97 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/48656/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I270cd2a9783030ad3a080b9cfda8a133e801c5ce Gerrit-Change-Number: 48656 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer: Update drobit device tree
by Frank Chu (Code Review) 16 Dec '20

16 Dec '20

Hello build bot (Jenkins), Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48495 to look at the new patch set (#3). Change subject: mb/google/volteer: Update drobit device tree ...................................................................... mb/google/volteer: Update drobit device tree Update drobit device tree override to match schematics. BUG=b:175351914 BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I48a3024df4270b111b90c4fb56847aad6e65bfa1 --- M src/mainboard/google/volteer/variants/drobit/overridetree.cb 1 file changed, 233 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/48495/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/48495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48a3024df4270b111b90c4fb56847aad6e65bfa1 Gerrit-Change-Number: 48495 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8192: Do the dramc pinmux selection
by CK HU (Code Review) 16 Dec '20

16 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44701 to review the following change. Change subject: soc/mediatek/mt8192: Do the dramc pinmux selection ...................................................................... soc/mediatek/mt8192: Do the dramc pinmux selection Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I7bc1971646a65db8eef5eb5223c919645c6e8ed9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c 1 file changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/44701/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 9b1216c..08f3ea4 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -6,8 +6,108 @@ #include <string.h> #include <timer.h> +const u8 mrr_o1_pinmux_mapping[PINMUX_MAX][CHANNEL_MAX][DQ_DATA_WIDTH] = { + [PINMUX_DSC] = { + [CHANNEL_A] = {0, 1, 7, 6, 4, 5, 2, 3, 9, 8, 11, 10, 14, 15, 13, 12}, + [CHANNEL_B] = {1, 0, 5, 6, 3, 2, 7, 4, 8, 9, 11, 10, 12, 14, 13, 15}, + }, + [PINMUX_LPBK] = { + }, + [PINMUX_EMCP] = { + [CHANNEL_A] = {1, 0, 3, 2, 4, 7, 6, 5,8, 9, 10, 14, 11, 15, 13, 12}, + [CHANNEL_B] = {0, 1, 4, 7, 3, 5, 6, 2,9, 8, 10, 12, 11, 14, 13, 15} + }, +}; + +static void set_rank_info_to_conf(const struct ddr_cali *cali) +{ + u8 value = ((cali->emi_config->cona_val >> 17) & 0x1) ? 0 : 1; + + SET32_BITFIELDS(&ch[0].ao.sa_reserve, + SA_RESERVE_MODE_RK0, cali->cbt_mode[RANK_0], + SA_RESERVE_MODE_RK1, cali->cbt_mode[RANK_1], + SA_RESERVE_SINGLE_RANK, value); +} + +static void get_dram_pinmux_sel(struct ddr_cali *cali) +{ + u32 value = (read32(&mtk_gpio->dram_pinmux_trapping) >> 19) & 0x1; + + if (value) + cali->pinmux_type = PINMUX_DSC; + else + cali->pinmux_type = PINMUX_EMCP; +} + +static void set_MRR_pinmux_mapping(const struct ddr_cali *cali) +{ + const u8 *map; + u32 bc_bak = dramc_get_broadcast(); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + map = mrr_o1_pinmux_mapping[get_pinmux_type(cali)][chn]; + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux1, + MRR_BIT_MUX1_MRR_BIT0_SEL, map[0], + MRR_BIT_MUX1_MRR_BIT1_SEL, map[1], + MRR_BIT_MUX1_MRR_BIT2_SEL, map[2], + MRR_BIT_MUX1_MRR_BIT3_SEL, map[3]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux2, + MRR_BIT_MUX2_MRR_BIT4_SEL, map[4], + MRR_BIT_MUX2_MRR_BIT5_SEL, map[5], + MRR_BIT_MUX2_MRR_BIT6_SEL, map[6], + MRR_BIT_MUX2_MRR_BIT7_SEL, map[7]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux3, + MRR_BIT_MUX3_MRR_BIT8_SEL, map[8], + MRR_BIT_MUX3_MRR_BIT9_SEL, map[9], + MRR_BIT_MUX3_MRR_BIT10_SEL, map[10], + MRR_BIT_MUX3_MRR_BIT11_SEL, map[11]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux4, + MRR_BIT_MUX4_MRR_BIT12_SEL, map[12], + MRR_BIT_MUX4_MRR_BIT13_SEL, map[13], + MRR_BIT_MUX4_MRR_BIT14_SEL, map[14], + MRR_BIT_MUX4_MRR_BIT15_SEL, map[15]); + } + dramc_set_broadcast(bc_bak); +} + +static void set_dqO1_pinmux_mapping(const struct ddr_cali *cali) +{ + const u8 *map; + u32 bc_bak = dramc_get_broadcast(); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + map = mrr_o1_pinmux_mapping[get_pinmux_type(cali)][chn]; + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dq_se_pinmux_ctrl0, + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0, map[0], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1, map[1], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2, map[2], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3, map[3], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4, map[4], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5, map[5], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6, map[6], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7, map[7]); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dq_se_pinmux_ctrl1, + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8, map[8], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9, map[9], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10, map[10], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11, map[11], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12, map[12], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13, map[13], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14, map[14], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15, map[15]); + } + + dramc_set_broadcast(bc_bak); +} + void global_option_init(struct ddr_cali *cali) { + set_rank_info_to_conf(cali); + get_dram_pinmux_sel(cali); + set_MRR_pinmux_mapping(cali); + set_dqO1_pinmux_mapping(cali); } void dfs_init_for_calibration(const struct ddr_cali *cali) -- To view, visit https://review.coreboot.org/c/coreboot/+/44701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bc1971646a65db8eef5eb5223c919645c6e8ed9 Gerrit-Change-Number: 44701 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Link gdt_init.S into bootblock
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47965 ) Change subject: arch/x86: Link gdt_init.S into bootblock ...................................................................... arch/x86: Link gdt_init.S into bootblock Followup work forces gdtptr and gdt towards the top of bootblock. They need to be realmode-addressable, i.e. within top 64 KiB or same segment with .reset. Change-Id: Ib6f23b2808d0a7e0d277d00a9b0f30c49fdefdd5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Makefile.inc M src/arch/x86/c_start.S M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/32bit/entry32.inc 4 files changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/47965/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 5157564..00917f0 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -98,6 +98,7 @@ bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c +bootblock-y += gdt_init.S bootblock-y += id.S bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c @@ -160,8 +161,6 @@ romstage-y += boot.c romstage-y += post.c -# gdt_init.S is included by entry32.inc when romstage is the first C -# environment. romstage-y += gdt_init.S romstage-y += cpu_common.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index a7af64f..8bebf87 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -142,10 +142,10 @@ /* This is the gdt for GCC part of coreboot. * It is different from the gdt in ASM part of coreboot - * which is defined in entry32.inc + * which is defined in gdt_init.S * * When the machine is initially started, we use a very simple - * gdt from ROM (that in entry32.inc) which only contains those + * gdt from ROM (that in gdt_init.S) which only contains those * entries we need for protected mode. * * When we're executing code from RAM, we want to do more complex diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 2665cc6..5e90da1 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -124,7 +124,7 @@ ljmpl $ROM_CODE_SEG, $__protected_start /** - * The gdt is defined in entry32.inc, it has a 4 Gb code segment + * The gdt is defined in gdt_init.S, it has a 4 Gb code segment * at 0x08, and a 4 GB data segment at 0x10; */ __gdtptr: diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 8509448..873a809 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -4,7 +4,6 @@ #include <arch/rom_segs.h> #include <cpu/x86/post_code.h> -#include <arch/x86/gdt_init.S> .code32 /* -- To view, visit https://review.coreboot.org/c/coreboot/+/47965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6f23b2808d0a7e0d277d00a9b0f30c49fdefdd5 Gerrit-Change-Number: 47965 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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