coreboot-gerrit December 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/common: Drop ACPIMMIO GPIO bank separation
by Angel Pons (Code Review) 16 Dec '20

16 Dec '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42690 ) Change subject: soc/amd/common: Drop ACPIMMIO GPIO bank separation ...................................................................... Patch Set 10: > Patch Set 10: Code-Review+2 > > this patch doesn't need the two patches before it in the same patch train to be merged before it lands, right? i don't think that this will cause issues, but I'll better verify before submitting patches out of the order in the patch train, so please confirm apu2 needs to be adapted first, so don't merge this one yet (will break building) -- To view, visit https://review.coreboot.org/c/coreboot/+/42690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6 Gerrit-Change-Number: 42690 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 16 Dec 2020 17:04:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Drop ACPIMMIO GPIO bank separation
by Felix Held (Code Review) 16 Dec '20

16 Dec '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42690 ) Change subject: soc/amd/common: Drop ACPIMMIO GPIO bank separation ...................................................................... Patch Set 10: Code-Review+2 this patch doesn't need the two patches before it in the same patch train to be merged before it lands, right? i don't think that this will cause issues, but I'll better verify before submitting patches out of the order in the patch train, so please confirm -- To view, visit https://review.coreboot.org/c/coreboot/+/42690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6 Gerrit-Change-Number: 42690 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 16 Dec 2020 17:00:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Drop ACPIMMIO GPIO bank separation
by Raul Rangel (Code Review) 16 Dec '20

16 Dec '20

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42690 ) Change subject: soc/amd/common: Drop ACPIMMIO GPIO bank separation ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6 Gerrit-Change-Number: 42690 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 16 Dec 2020 16:33:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/tiagopass/devicetree.cb: Add P2SB device
by Arthur Heymans (Code Review) 16 Dec '20

16 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48654 ) Change subject: mb/ocp/tiagopass/devicetree.cb: Add P2SB device ...................................................................... mb/ocp/tiagopass/devicetree.cb: Add P2SB device This fixes ocp/tiagopass not booting as after FSP-S the P2SB is accessed to read out or reconfigure the HPET and PCH IOAPIC DBF. Change-Id: Ia37bd0f14627980345cd07f20e935a10d4760b69 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/ocp/tiogapass/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/48654/1 diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 008633b..488f677 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -77,6 +77,7 @@ register "bmc_boot_timeout" = "90" end end # Intel Corporation C621 Series Chipset LPC/eSPI Controller + device pci 1f.1 hidden end # p2sb device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller -- To view, visit https://review.coreboot.org/c/coreboot/+/48654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia37bd0f14627980345cd07f20e935a10d4760b69 Gerrit-Change-Number: 48654 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: Drop ACPIMMIO GPIO bank separation
by Kyösti Mälkki (Code Review) 16 Dec '20

16 Dec '20

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42690 ) Change subject: soc/amd/common: Drop ACPIMMIO GPIO bank separation ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/42690/4/src/soc/amd/common/block/g… File src/soc/amd/common/block/gpio_banks/gpio.c: https://review.coreboot.org/c/coreboot/+/42690/4/src/soc/amd/common/block/g… PS4, Line 83: return acpimmio_gpio0 + gpio_num * sizeof(uint32_t); > Done? Split to CB:48639, should it be desireable to further hide gpio_read/write32() from being globally available. -- To view, visit https://review.coreboot.org/c/coreboot/+/42690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6 Gerrit-Change-Number: 42690 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 16 Dec 2020 16:13:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Drop ACPIMMIO GPIO bank separation
by Angel Pons (Code Review) 16 Dec '20

16 Dec '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42690 ) Change subject: soc/amd/common: Drop ACPIMMIO GPIO bank separation ...................................................................... Patch Set 10: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/42690/4/src/soc/amd/common/block/g… File src/soc/amd/common/block/gpio_banks/gpio.c: https://review.coreboot.org/c/coreboot/+/42690/4/src/soc/amd/common/block/g… PS4, Line 83: return acpimmio_gpio0 + gpio_num * sizeof(uint32_t); > The inlined varinat moves away from <acpimmio.h> here. Intent is for this gpio. […] Done? -- To view, visit https://review.coreboot.org/c/coreboot/+/42690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6 Gerrit-Change-Number: 42690 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 16 Dec 2020 15:30:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Move DMICTL lock
by Arthur Heymans (Code Review) 16 Dec '20

16 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48657 ) Change subject: soc/intel/xeon_sp: Move DMICTL lock ...................................................................... soc/intel/xeon_sp: Move DMICTL lock On SKX FPM-M does not return if this is set too early. Tested on OCP/Tiogapass, boots. Change-Id: Ib8ef7bab36bfd4b62988768753d10b4d7b7d567f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/include/soc/pch.h M src/soc/intel/xeon_sp/pch.c M src/soc/intel/xeon_sp/skx/chip.c 4 files changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/48657/1 diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 6beebdf..592a316 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -79,6 +79,7 @@ fsp_silicon_init(false); override_hpet_ioapic_bdf(); pch_enable_ioapic(); + pch_lock_dmictl(); setup_lapic(); p2sb_unhide(); } diff --git a/src/soc/intel/xeon_sp/include/soc/pch.h b/src/soc/intel/xeon_sp/include/soc/pch.h index 0be14ae..156a22a 100644 --- a/src/soc/intel/xeon_sp/include/soc/pch.h +++ b/src/soc/intel/xeon_sp/include/soc/pch.h @@ -10,5 +10,6 @@ #endif void override_hpet_ioapic_bdf(void); +void pch_lock_dmictl(void); #endif /* _SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c index 44824ca..d2496b1 100644 --- a/src/soc/intel/xeon_sp/pch.c +++ b/src/soc/intel/xeon_sp/pch.c @@ -40,9 +40,6 @@ reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1; pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); - - reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL); - pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK); } void bootblock_pch_init(void) @@ -69,3 +66,9 @@ p2sb_set_ioapic_bdf(ioapic_bdf); p2sb_set_hpet_bdf(hpet_bdf); } + +void pch_lock_dmictl(void) +{ + uint32_t reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL); + pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK); +} diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 0505ea7..f101973 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -45,6 +45,7 @@ printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(false); override_hpet_ioapic_bdf(); + pch_lock_dmictl(); } static void soc_final(void *data) -- To view, visit https://review.coreboot.org/c/coreboot/+/48657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8ef7bab36bfd4b62988768753d10b4d7b7d567f Gerrit-Change-Number: 48657 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Update drobit device tree
by Zhuohao Lee (Code Review) 16 Dec '20

16 Dec '20

Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48495 ) Change subject: mb/google/volteer: Update drobit device tree ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/48495/3/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/drobit/overridetree.cb: https://review.coreboot.org/c/coreboot/+/48495/3/src/mainboard/google/volte… PS3, Line 25: device pci 04.0 on : chip drivers/intel/dptf : ## Active Policy : register "policies.active" = "{ : [0] = {.target = DPTF_TEMP_SENSOR_3, : .thresholds = {TEMP_PCT(57, 90), : TEMP_PCT(47, 80), : TEMP_PCT(40, 70), : TEMP_PCT(36, 60), : TEMP_PCT(34, 50), : TEMP_PCT(30, 40),}}}" : : ## Passive Policy : register "policies.passive" = "{ : [0] = DPTF_PASSIVE(CPU, CPU, 95, 6000), : [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 6000), : [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 75, 6000), : [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 6000), : [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 6000)}" : : ## Critical Policy : register "policies.critical" = "{ : [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), : [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 80, SHUTDOWN), : [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN), : [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), : [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 80, SHUTDOWN)}" : : ## Power Limits Control : # 3-15W PL1 in 200mW increments, avg over 28-32s interval : # PL2 is 15-51W, avg over 28-32s interval : register "controls.power_limits" = "{ : .pl1 = {.min_power = 3000, : .max_power = 15000, : .time_window_min = 28 * MSECS_PER_SEC, : .time_window_max = 32 * MSECS_PER_SEC, : .granularity = 200,}, : .pl2 = {.min_power = 15000, : .max_power = 51000, : .time_window_min = 28 * MSECS_PER_SEC, : .time_window_max = 32 * MSECS_PER_SEC, : .granularity = 1000,}}" : : ## Fan Performance Control (Percent, Speed, Noise, Power) : register "controls.fan_perf" = "{ : [0] = { 90, 5200, 220, 2200, }, : [1] = { 80, 4900, 180, 1800, }, : [2] = { 70, 4600, 145, 1450, }, : [3] = { 60, 4200, 115, 1150, }, : [4] = { 50, 3800, 90, 900, }, : [5] = { 40, 3400, 55, 550, }, : [6] = { 30, 2900, 30, 300, }, : [7] = { 20, 2300, 15, 150, }, : [8] = { 10, 1600, 10, 100, }, : [9] = { 0, 0, 0, 50, }}" : : # Fan options : register "options.fan.fine_grained_control" = "1" : register "options.fan.step_size" = "2" : : device generic 0 on end : end : end # DPTF 0x9A03 Is this fine tuned for the Drobit? If not, i would suggest to submit it later. -- To view, visit https://review.coreboot.org/c/coreboot/+/48495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48a3024df4270b111b90c4fb56847aad6e65bfa1 Gerrit-Change-Number: 48495 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 16 Dec 2020 13:50:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/gpio_banks: Drop underscore in __gpio
by Kyösti Mälkki (Code Review) 16 Dec '20

16 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48635 ) Change subject: soc/amd/common/gpio_banks: Drop underscore in __gpio ...................................................................... soc/amd/common/gpio_banks: Drop underscore in __gpio The local function names were chose such that they don't collide with <gpio.h> so the prefix is unnecessary. Change-Id: I4799a6d6b87e8081324d88b0773e61cbda0d4cfb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/48635/1 diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index a5f0eaf..8e340a3 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -94,7 +94,7 @@ return (uintptr_t)gpio_ctrl_ptr(gpio_num); } -static void __gpio_update32(gpio_t gpio_num, uint32_t mask, uint32_t or) +static void gpio_update32(gpio_t gpio_num, uint32_t mask, uint32_t or) { uint32_t reg; @@ -105,31 +105,31 @@ } /* Set specified bits of a register to match those of ctrl. */ -static void __gpio_setbits32(gpio_t gpio_num, uint32_t mask, uint32_t ctrl) +static void gpio_setbits32(gpio_t gpio_num, uint32_t mask, uint32_t ctrl) { - __gpio_update32(gpio_num, ~mask, ctrl & mask); + gpio_update32(gpio_num, ~mask, ctrl & mask); } -static void __gpio_and32(gpio_t gpio_num, uint32_t mask) +static void gpio_and32(gpio_t gpio_num, uint32_t mask) { - __gpio_update32(gpio_num, mask, 0); + gpio_update32(gpio_num, mask, 0); } -static void __gpio_or32(gpio_t gpio_num, uint32_t or) +static void gpio_or32(gpio_t gpio_num, uint32_t or) { - __gpio_update32(gpio_num, -1UL, or); + gpio_update32(gpio_num, -1UL, or); } static void master_switch_clr(uint32_t mask) { const uint8_t master_reg = GPIO_MASTER_SWITCH / sizeof(uint32_t); - __gpio_and32(master_reg, ~mask); + gpio_and32(master_reg, ~mask); } static void master_switch_set(uint32_t or) { const uint8_t master_reg = GPIO_MASTER_SWITCH / sizeof(uint32_t); - __gpio_or32(master_reg, or); + gpio_or32(master_reg, or); } int gpio_get(gpio_t gpio_num) @@ -142,27 +142,27 @@ void gpio_set(gpio_t gpio_num, int value) { - __gpio_setbits32(gpio_num, GPIO_OUTPUT_VALUE, value ? GPIO_OUTPUT_VALUE : 0); + gpio_setbits32(gpio_num, GPIO_OUTPUT_VALUE, value ? GPIO_OUTPUT_VALUE : 0); } void gpio_input_pulldown(gpio_t gpio_num) { - __gpio_setbits32(gpio_num, GPIO_PULL_MASK, GPIO_PULLDOWN_ENABLE); + gpio_setbits32(gpio_num, GPIO_PULL_MASK, GPIO_PULLDOWN_ENABLE); } void gpio_input_pullup(gpio_t gpio_num) { - __gpio_setbits32(gpio_num, GPIO_PULL_MASK, GPIO_PULLUP_ENABLE); + gpio_setbits32(gpio_num, GPIO_PULL_MASK, GPIO_PULLUP_ENABLE); } void gpio_input(gpio_t gpio_num) { - __gpio_and32(gpio_num, ~GPIO_OUTPUT_ENABLE); + gpio_and32(gpio_num, ~GPIO_OUTPUT_ENABLE); } void gpio_output(gpio_t gpio_num, int value) { - __gpio_or32(gpio_num, GPIO_OUTPUT_ENABLE); + gpio_or32(gpio_num, GPIO_OUTPUT_ENABLE); gpio_set(gpio_num, value); } @@ -217,9 +217,9 @@ soc_gpio_hook(gpio, mux); - __gpio_setbits32(gpio, PAD_CFG_MASK, control); + gpio_setbits32(gpio, PAD_CFG_MASK, control); /* Clear interrupt and wake status (write 1-to-clear bits) */ - __gpio_or32(gpio, GPIO_INT_STATUS | GPIO_WAKE_STATUS); + gpio_or32(gpio, GPIO_INT_STATUS | GPIO_WAKE_STATUS); if (control_flags == 0) continue; -- To view, visit https://review.coreboot.org/c/coreboot/+/48635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4799a6d6b87e8081324d88b0773e61cbda0d4cfb Gerrit-Change-Number: 48635 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Update SPD table for drobit
by Zhuohao Lee (Code Review) 16 Dec '20

16 Dec '20

Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48496 ) Change subject: mb/google/volteer: Update SPD table for drobit ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd9439f8449856d4ec6798a4e4310dd139bce05f Gerrit-Change-Number: 48496 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 16 Dec 2020 13:34:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2020