coreboot-gerrit December 2020

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Change in coreboot[master]: mb/google/volteer: Add GPIO to drobit support
by Frank Chu (Code Review) 17 Dec '20

17 Dec '20

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48497 ) Change subject: mb/google/volteer: Add GPIO to drobit support ...................................................................... Patch Set 4: (3 comments) https://review.coreboot.org/c/coreboot/+/48497/3/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/drobit/gpio.c: https://review.coreboot.org/c/coreboot/+/48497/3/src/mainboard/google/volte… PS3, Line 85: /* F11 : THC1_SPI2_CLK ==> FPMCU_BOOT1 */ : PAD_CFG_GPO(GPP_F11, 0, DEEP), > This pin is EN_PP3300_WWAN Done https://review.coreboot.org/c/coreboot/+/48497/3/src/mainboard/google/volte… PS3, Line 118: /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ : PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), : /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ : PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), : /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ : PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), : /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ : PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), > Do you use soundwire? It looks like those pins weren't be used from the schematics. Done https://review.coreboot.org/c/coreboot/+/48497/3/src/mainboard/google/volte… PS3, Line 136: early_gpio_table > Please add "PAD_CFG_GPO(GPP_A13, 0, DEEP)," to early_gpio_table, […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/48497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54ba182c6da3db282961b3c72a4d2d11d1001e95 Gerrit-Change-Number: 48497 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Thu, 17 Dec 2020 09:11:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Add GPIO to drobit support
by build bot (Jenkins) (Code Review) 17 Dec '20

17 Dec '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48497 ) Change subject: mb/google/volteer: Add GPIO to drobit support ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/48497/4/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/drobit/gpio.c: https://review.coreboot.org/c/coreboot/+/48497/4/src/mainboard/google/volte… PS4, Line 144: /* assert reset on reboot */ code indent should use tabs where possible -- To view, visit https://review.coreboot.org/c/coreboot/+/48497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54ba182c6da3db282961b3c72a4d2d11d1001e95 Gerrit-Change-Number: 48497 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Thu, 17 Dec 2020 09:11:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Add GPIO to drobit support
by Frank Chu (Code Review) 17 Dec '20

17 Dec '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Caveh Jalali, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48497 to look at the new patch set (#4). Change subject: mb/google/volteer: Add GPIO to drobit support ...................................................................... mb/google/volteer: Add GPIO to drobit support Add support for gpio driver for drobit BUG=b:175351914 BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I54ba182c6da3db282961b3c72a4d2d11d1001e95 --- M src/mainboard/google/volteer/variants/drobit/Makefile.inc A src/mainboard/google/volteer/variants/drobit/gpio.c 2 files changed, 185 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/48497/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/48497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54ba182c6da3db282961b3c72a4d2d11d1001e95 Gerrit-Change-Number: 48497 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8192: Set BL31 platform mt8192
by Yidi Lin (Code Review) 16 Dec '20

16 Dec '20

Hello CK HU, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46383 to review the following change. Change subject: soc/mediatek/mt8192: Set BL31 platform mt8192 ...................................................................... soc/mediatek/mt8192: Set BL31 platform mt8192 Change-Id: I80d4a339b4a75647f55a699af447dcd362aab7b5 Signed-off-by: CK Hu <ck.hu(a)mediatek.com> --- M src/soc/mediatek/mt8192/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46383/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 20acd24..8bc7b74 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -49,6 +49,8 @@ cbfs-files-y += $(DRAM_CBFS) endif +BL31_MAKEARGS += PLAT=mt8192 + CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include -- To view, visit https://review.coreboot.org/c/coreboot/+/46383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80d4a339b4a75647f55a699af447dcd362aab7b5 Gerrit-Change-Number: 46383 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: [WIP] arch/x86: Use intermediate .id section
by Kyösti Mälkki (Code Review) 16 Dec '20

16 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47602 ) Change subject: [WIP] arch/x86: Use intermediate .id section ...................................................................... [WIP] arch/x86: Use intermediate .id section The strings in id.S are the same as those defined in lib/version.c. Eliminating the calculation of reverse offsets allows the references across linker sections and dropping the duplicate strings in id.S. TBD: util/cbfstool needs to post-process and invert the offsets in .id section. Change-Id: I35d3312336e9c66d657d2ca619cf30fd79e18fd4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/id.S 1 file changed, 4 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/47602/1 diff --git a/src/arch/x86/id.S b/src/arch/x86/id.S index 4ff397d..545232a 100644 --- a/src/arch/x86/id.S +++ b/src/arch/x86/id.S @@ -4,23 +4,9 @@ .section ".id", "a", @progbits -ver: - .asciz COREBOOT_VERSION -vendor: - .asciz CONFIG_MAINBOARD_VENDOR -part: - .asciz CONFIG_MAINBOARD_PART_NUMBER - -#if ENV_X86_64 -.long 0xffffffff - ver + 1 /* Reverse offset to the version */ -.long 0xffffffff - vendor + 1 /* Reverse offset to the vendor id */ -.long 0xffffffff - part + 1 /* Reverse offset to the part number */ -#else -.long - ver /* Reverse offset to the version */ -.long - vendor /* Reverse offset to the vendor id */ -.long - part /* Reverse offset to the part number */ -#endif - -.long CONFIG_ROM_SIZE /* Size of this romimage */ +.long coreboot_version /* Reverse offset to the version */ +.long mainboard_vendor /* Reverse offset to the vendor id */ +.long mainboard_part_number /* Reverse offset to the part number */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ .previous -- To view, visit https://review.coreboot.org/c/coreboot/+/47602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35d3312336e9c66d657d2ca619cf30fd79e18fd4 Gerrit-Change-Number: 47602 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 19

Change in coreboot[master]: arch/ppc64: Remove .id section in bootblock
by Kyösti Mälkki (Code Review) 16 Dec '20

16 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47966 ) Change subject: arch/ppc64: Remove .id section in bootblock ...................................................................... arch/ppc64: Remove .id section in bootblock The strings in .id are expected to match the build for the purpose of identifying the binary image. There is no identified use for the offsets. The files id.ld and prologue.inc were unused. Change-Id: Ida332671e0ace3f6afd11020474ffda04614bad5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/ppc64/Kconfig M src/arch/ppc64/bootblock.S D src/arch/ppc64/id.ld D src/arch/ppc64/prologue.inc 4 files changed, 0 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/47966/1 diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index 546dbc8..44dbb1d 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -17,7 +17,3 @@ config ARCH_RAMSTAGE_PPC64 bool select ARCH_PPC64 - -config ID_SECTION_OFFSET - hex - default 0x80 diff --git a/src/arch/ppc64/bootblock.S b/src/arch/ppc64/bootblock.S index 8b66fcd..b443f05 100644 --- a/src/arch/ppc64/bootblock.S +++ b/src/arch/ppc64/bootblock.S @@ -8,26 +8,3 @@ .org 0x100, 0xff _start: b _start - .section ".id", "a", %progbits - - .section ".id", "a", @progbits - - .globl __id_start -__id_start: -ver: - .asciz "4" //COREBOOT_VERSION -vendor: - .asciz "qemu" //CONFIG_MAINBOARD_VENDOR -part: - .asciz "1" //CONFIG_MAINBOARD_PART_NUMBER - /* Reverse offset to the vendor id */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - ver - /* Reverse offset to the vendor id */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor - /* Reverse offset to the part number */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - part - /* of this romimage */ -.long CONFIG_ROM_SIZE - .globl __id_end - -__id_end: diff --git a/src/arch/ppc64/id.ld b/src/arch/ppc64/id.ld deleted file mode 100644 index 7449740..0000000 --- a/src/arch/ppc64/id.ld +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -SECTIONS { - . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; - .id (.): { - *(.id) - } -} diff --git a/src/arch/ppc64/prologue.inc b/src/arch/ppc64/prologue.inc deleted file mode 100644 index 21f7d49..0000000 --- a/src/arch/ppc64/prologue.inc +++ /dev/null @@ -1,4 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -.section ".rom.data", "a", @progbits -.section ".rom.text", "ax", @progbits -- To view, visit https://review.coreboot.org/c/coreboot/+/47966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida332671e0ace3f6afd11020474ffda04614bad5 Gerrit-Change-Number: 47966 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: arch/x86: Remove ID_SECTION_OFFSET
by Kyösti Mälkki (Code Review) 16 Dec '20

16 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47598 ) Change subject: arch/x86: Remove ID_SECTION_OFFSET ...................................................................... arch/x86: Remove ID_SECTION_OFFSET The location is hardcoded inside flashrom at least and currently there is no platform that needs to locate it elsewhere. Change-Id: I8348f2ac0cab969ab78ecb50a55de486eee0cf9b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/ppc64/Kconfig M src/arch/x86/Kconfig M src/arch/x86/id.S M src/cpu/x86/16bit/reset16.ld 4 files changed, 12 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/47598/1 diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index 44dbb1d..546dbc8 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -17,3 +17,7 @@ config ARCH_RAMSTAGE_PPC64 bool select ARCH_PPC64 + +config ID_SECTION_OFFSET + hex + default 0x80 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index b5e52e6..f4ddd20 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -179,10 +179,6 @@ hex default 0xfed00000 if !HPET_ADDRESS_OVERRIDE -config ID_SECTION_OFFSET - hex - default 0x80 - # 64KiB default bootblock size config C_ENV_BOOTBLOCK_SIZE hex diff --git a/src/arch/x86/id.S b/src/arch/x86/id.S index 798b25d..f79952f 100644 --- a/src/arch/x86/id.S +++ b/src/arch/x86/id.S @@ -2,27 +2,18 @@ #include <build.h> - .section ".id", "a", @progbits +.section ".id", "a", @progbits - .globl __id_start -__id_start: ver: .asciz COREBOOT_VERSION vendor: .asciz CONFIG_MAINBOARD_VENDOR part: .asciz CONFIG_MAINBOARD_PART_NUMBER -.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the - *vendor id - */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the - * vendor id - */ -.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the - * part number - */ -.long CONFIG_ROM_SIZE /* Size of this romimage */ - .globl __id_end -__id_end: +.long - ver /* Reverse offset to the version */ +.long - vendor /* Reverse offset to the vendor id */ +.long - part /* Reverse offset to the part number */ +.long CONFIG_ROM_SIZE /* Size of this romimage */ + .previous diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index 1c7e40f..d356034 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -20,10 +20,11 @@ /* Trigger an error if I have an unuseable start address */ _bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report."); - . = (0xffffffff - CONFIG_ID_SECTION_OFFSET) - (__id_end - __id_start) + 1; + . = ID_SECTION; .id (.): { KEEP(*(.id)) } + ID_SECTION = 0xffffff80 - SIZEOF(.id); #if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) . = 0xffffffc0; -- To view, visit https://review.coreboot.org/c/coreboot/+/47598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8348f2ac0cab969ab78ecb50a55de486eee0cf9b Gerrit-Change-Number: 47598 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports
by V Sowmya (Code Review) 16 Dec '20

16 Dec '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48619 ) Change subject: mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports ...................................................................... mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports This change enables PCIEXP_HOTPLUG to support resource allocation for TCSS TBT/USB4 ports. Change-Id: I5f883dac0d7e5fa84ad2e1683f84c933a90cea51 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/intel/adlrvp/Kconfig 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/48619/1 diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index b6d3ff3..369ce21 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -15,6 +15,7 @@ select SOC_INTEL_ALDERLAKE select HAVE_SPD_IN_CBFS select DRIVERS_SOUNDWIRE_ALC711 + select PCIEXP_HOTPLUG config CHROMEOS bool @@ -77,6 +78,18 @@ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC endchoice +config PCIEXP_HOTPLUG_BUSES + int + default 42 + +config PCIEXP_HOTPLUG_MEM + hex + default 0xc200000 # 194 MiB + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex + default 0x1c000000 # 448 MiB + config VBOOT select VBOOT_LID_SWITCH select VBOOT_MOCK_SECDATA -- To view, visit https://review.coreboot.org/c/coreboot/+/48619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f883dac0d7e5fa84ad2e1683f84c933a90cea51 Gerrit-Change-Number: 48619 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: autoport: Add a license header to non-empty asl files
by Iru Cai (vimacs) (Code Review) 16 Dec '20

16 Dec '20

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45464 to review the following change. Change subject: autoport: Add a license header to non-empty asl files ...................................................................... autoport: Add a license header to non-empty asl files Change-Id: I8078d8babf24feabb22856ee820ab45b7d466f62 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/ec_fixme.go M util/autoport/ec_lenovo.go M util/autoport/ec_none.go M util/autoport/main.go 4 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/45464/1 diff --git a/util/autoport/ec_fixme.go b/util/autoport/ec_fixme.go index f5d039c..54f78ab 100644 --- a/util/autoport/ec_fixme.go +++ b/util/autoport/ec_fixme.go @@ -19,6 +19,7 @@ SouthBridge.EnableGPE(SouthBridge.DecodeGPE(sbGPE)) } + Add_gpl(ap) ap.WriteString( `Method(_WAK, 1) { @@ -64,6 +65,7 @@ defer si.Close() if hasKeyboard { + Add_gpl(si) si.WriteString("#include <drivers/pc80/pc/ps2_controller.asl>\n") MainboardInit += fmt.Sprintf("\tpc_keyboard_init(NO_AUX_DEVICE);\n") MainboardIncludes = append(MainboardIncludes, "pc80/keyboard.h") @@ -72,6 +74,7 @@ ec := Create(ctx, "acpi/ec.asl") defer ec.Close() + Add_gpl(ec) ec.WriteString(`Device(EC) { Name (_HID, EISAID("PNP0C09")) diff --git a/util/autoport/ec_lenovo.go b/util/autoport/ec_lenovo.go index 6851d6d..763ac26 100644 --- a/util/autoport/ec_lenovo.go +++ b/util/autoport/ec_lenovo.go @@ -39,6 +39,7 @@ Value: "1", }, GPEDefine) + Add_gpl(ap) ap.WriteString( `Method(_WAK, 1) { @@ -57,6 +58,7 @@ si := Create(ctx, "acpi/superio.asl") defer si.Close() + Add_gpl(si) si.WriteString("#include <drivers/pc80/pc/ps2_controller.asl>\n") /* FIXME:XX Move this to ec/lenovo. */ @@ -163,6 +165,7 @@ ec := Create(ctx, "acpi/ec.asl") defer ec.Close() + Add_gpl(ec) ec.WriteString("#include <ec/lenovo/h8/acpi/ec.asl>\n") KconfigBool["EC_LENOVO_PMH7"] = true diff --git a/util/autoport/ec_none.go b/util/autoport/ec_none.go index eb2b87c..bcb61bf 100644 --- a/util/autoport/ec_none.go +++ b/util/autoport/ec_none.go @@ -4,6 +4,7 @@ ap := Create(ctx, "acpi/platform.asl") defer ap.Close() + Add_gpl(ap) ap.WriteString( `Method(_WAK, 1) { diff --git a/util/autoport/main.go b/util/autoport/main.go index 1a9050a..e8436bd 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -825,9 +825,9 @@ dsdt.WriteString("#define " + define.Key + " " + define.Value + "\n") } + Add_gpl(dsdt) dsdt.WriteString( ` - #include <acpi/acpi.h> DefinitionBlock( -- To view, visit https://review.coreboot.org/c/coreboot/+/45464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8078d8babf24feabb22856ee820ab45b7d466f62 Gerrit-Change-Number: 45464 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/google/guybrush: Add new mainboard
by Mathew King (Code Review) 16 Dec '20

16 Dec '20

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48479 ) Change subject: mb/google/guybrush: Add new mainboard ...................................................................... mb/google/guybrush: Add new mainboard Guybrush is a new Google mainboard with an AMD SOC. This is a stripped down version of the Zork mainbord as a starting point. BUG=b:175143925 TEST=builds Change-Id: I1792f21ff7616f364ddc8b0c04481049b2a5fb04 --- A src/mainboard/google/guybrush/Kconfig A src/mainboard/google/guybrush/Kconfig.name A src/mainboard/google/guybrush/Makefile.inc A src/mainboard/google/guybrush/board_info.txt A src/mainboard/google/guybrush/bootblock.c A src/mainboard/google/guybrush/chromeos.c A src/mainboard/google/guybrush/chromeos.fmd A src/mainboard/google/guybrush/dsdt.asl A src/mainboard/google/guybrush/ec.c A src/mainboard/google/guybrush/mainboard.c A src/mainboard/google/guybrush/sku_id.c A src/mainboard/google/guybrush/smihandler.c A src/mainboard/google/guybrush/spd/Makefile.inc A src/mainboard/google/guybrush/spd/ddr4-spd-1.hex A src/mainboard/google/guybrush/spd/ddr4-spd-2.hex A src/mainboard/google/guybrush/spd/ddr4-spd-3.hex A src/mainboard/google/guybrush/spd/ddr4-spd-4.hex A src/mainboard/google/guybrush/spd/ddr4-spd-5.hex A src/mainboard/google/guybrush/spd/ddr4-spd-6.hex A src/mainboard/google/guybrush/spd/ddr4-spd-7.hex A src/mainboard/google/guybrush/spd/ddr4-spd-8.hex A src/mainboard/google/guybrush/spd/ddr4-spd-9.hex A src/mainboard/google/guybrush/spd/ddr4-spd-empty.hex A src/mainboard/google/guybrush/spd/ddr4_spd_manifest.generated.txt A src/mainboard/google/guybrush/variants/baseboard/Makefile.inc A src/mainboard/google/guybrush/variants/baseboard/devicetree.cb A src/mainboard/google/guybrush/variants/baseboard/fsps_baseboard.c A src/mainboard/google/guybrush/variants/baseboard/gpio_baseboard.c A src/mainboard/google/guybrush/variants/baseboard/gpio_baseboard_common.c A src/mainboard/google/guybrush/variants/baseboard/helpers.c A src/mainboard/google/guybrush/variants/baseboard/include/baseboard/acpi/thermal.asl A src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h A src/mainboard/google/guybrush/variants/baseboard/include/baseboard/gpio.h A src/mainboard/google/guybrush/variants/baseboard/include/baseboard/thermal.h A src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/guybrush/variants/baseboard/tpm_tis.c A src/mainboard/google/guybrush/variants/guybrush/Makefile.inc A src/mainboard/google/guybrush/variants/guybrush/gpio.c A src/mainboard/google/guybrush/variants/guybrush/include/variant/acpi/thermal.asl A src/mainboard/google/guybrush/variants/guybrush/include/variant/ec.h A src/mainboard/google/guybrush/variants/guybrush/include/variant/gpio.h A src/mainboard/google/guybrush/variants/guybrush/include/variant/thermal.h A src/mainboard/google/guybrush/variants/guybrush/overridetree.cb A src/mainboard/google/guybrush/variants/guybrush/spd/Makefile.inc A src/mainboard/google/guybrush/variants/guybrush/spd/dram_id.generated.txt A src/mainboard/google/guybrush/variants/guybrush/spd/mem_parts_used.txt A src/mainboard/google/guybrush/verstage.c 47 files changed, 2,686 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/48479/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig new file mode 100644 index 0000000..5ab52f9 --- /dev/null +++ b/src/mainboard/google/guybrush/Kconfig @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_GOOGLE_BASEBOARD_GUYBRUSH + def_bool n + +if BOARD_GOOGLE_BASEBOARD_GUYBRUSH + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_AMD_COMMON_BLOCK_USE_ESPI + select SOC_AMD_PICASSO + select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF + select VGA_BIOS + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_AMD_I2S_MACHINE_DEV + select DISABLE_SPI_FLASH_ROM_SHARING + select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_AUDIO_CODEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_I2C_TUNNEL + select EC_GOOGLE_CHROMEEC_SKUID + select ELOG + select ELOG_BOOT_COUNT + select ELOG_GSMI + select HAVE_ACPI_TABLES + select GFXUMA + select GOOGLE_SMBIOS_MAINBOARD_VERSION + select MAINBOARD_HAS_CHROMEOS + select PICASSO_CONSOLE_UART + select MAINBOARD_HAS_I2C_TPM_CR50 + select MAINBOARD_HAS_TPM2 + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE + select HAVE_EM100_SUPPORT + select SYSTEM_TYPE_LAPTOP + select DRIVERS_GENERIC_MAX98357A + select HAVE_ACPI_RESUME + select DRIVERS_USB_ACPI + select DRIVERS_UART_ACPI + +config ELOG_BOOT_COUNT_CMOS_OFFSET + int + default 144 + +# FMDFILE is set here so that coreboot build picks up this flash map layout +# even when CHROMEOS is not selected when building upstream. +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" + +config MAINBOARD_DIR + string + default "google/guybrush" + +config VARIANT_DIR + string + default "guybrush" if BOARD_GOOGLE_GUYBRUSH + +config MAINBOARD_PART_NUMBER + string + default "Guybrush" if BOARD_GOOGLE_GUYBRUSH + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config MAINBOARD_FAMILY + string + default "Google_Guybrush" + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_LID_SWITCH + select VBOOT_STARTS_BEFORE_BOOTBLOCK + +config VBOOT_VBNV_OFFSET + hex + default 0x2A + +config CHROMEOS + # Use default libpayload config + select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE + +config AMD_FWM_POSITION_INDEX + int + default 2 + +config DRIVER_TPM_I2C_BUS + hex + default 0x03 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + +config PICASSO_FW_A_POSITION + hex + default 0xFF012040 + depends on VBOOT_SLOTS_RW_AB + help + Location of the AMD firmware in the RW_A region. This is the + start of the RW-A region + 64 bytes for the cbfs header. + +config PICASSO_FW_B_POSITION + hex + default 0xFF312040 + depends on VBOOT_SLOTS_RW_AB + help + Location of the AMD firmware in the RW_B region. This is the + start of the RW-A region + 64 bytes for the cbfs header. + +config VARIANT_HAS_FPMCU + bool + default n + help + Select y if any SKU of the board has a fingerprint sensor + +config VARIANT_MAX_BOARD_ID_BROKEN_FMPCU_POWER + int + default 0 + help + Last board version that needs the extra delay for FPMCU init. + +config EFS_SPI_READ_MODE + int + default 0 if EM100 # Normal read mode + default 2 # Dual IO (1-1-2) + +config EFS_SPI_SPEED + int + default 3 if EM100 # 16.66 MHz + default 0 # 66.66 MHz + +config EFS_SPI_MICRON_FLAG + int + default 0 + +config CHROMEOS_WIFI_SAR + bool + default y if CHROMEOS + select DRIVERS_WIFI_GENERIC + select DSAR_ENABLE + select SAR_ENABLE + select USE_SAR + select GEO_SAR_ENABLE + select HAVE_REGULATORY_DOMAIN if BOARD_GOOGLE_VILBOZ + +endif # BOARD_GOOGLE_BASEBOARD_GUYBRUSH diff --git a/src/mainboard/google/guybrush/Kconfig.name b/src/mainboard/google/guybrush/Kconfig.name new file mode 100644 index 0000000..076516c --- /dev/null +++ b/src/mainboard/google/guybrush/Kconfig.name @@ -0,0 +1,5 @@ +comment "Guybrush" + +config BOARD_GOOGLE_GUYBRUSH + bool "-> Guybrush" + select BOARD_GOOGLE_BASEBOARD_GUYBRUSH diff --git a/src/mainboard/google/guybrush/Makefile.inc b/src/mainboard/google/guybrush/Makefile.inc new file mode 100644 index 0000000..96c97b6 --- /dev/null +++ b/src/mainboard/google/guybrush/Makefile.inc @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +romstage-y += chromeos.c +romstage-y += sku_id.c + +ramstage-y += chromeos.c +ramstage-y += ec.c +ramstage-y += sku_id.c + +verstage-y += verstage.c + +smm-y += smihandler.c + +subdirs-y += variants/baseboard +subdirs-y += spd + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include/baseboard/acpi + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/guybrush/board_info.txt b/src/mainboard/google/guybrush/board_info.txt new file mode 100644 index 0000000..0c81acb --- /dev/null +++ b/src/mainboard/google/guybrush/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Guybrush +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c new file mode 100644 index 0000000..87e0285 --- /dev/null +++ b/src/mainboard/google/guybrush/bootblock.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <baseboard/variants.h> +#include <acpi/acpi.h> + +void bootblock_mainboard_early_init(void) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + gpios = variant_bootblock_gpio_table(&num_gpios, acpi_get_sleep_type()); + program_gpios(gpios, num_gpios); + + variant_pcie_gpio_configure(); +} diff --git a/src/mainboard/google/guybrush/chromeos.c b/src/mainboard/google/guybrush/chromeos.c new file mode 100644 index 0000000..c790e11 --- /dev/null +++ b/src/mainboard/google/guybrush/chromeos.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <variant/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + /* Write protect is active low, so invert it here */ + return !gpio_get(CROS_WP_GPIO); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(CROS_WP_GPIO, GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/guybrush/chromeos.fmd b/src/mainboard/google/guybrush/chromeos.fmd new file mode 100644 index 0000000..7c2b95b --- /dev/null +++ b/src/mainboard/google/guybrush/chromeos.fmd @@ -0,0 +1,33 @@ +FLASH@0xFF000000 16M { + SI_BIOS { + RW_MRC_CACHE 64K + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + RW_SECTION_B 3M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 20K + SMMSTORE(PRESERVE) 4K + RW_LEGACY(CBFS) + WP_RO@8M 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 448K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/google/guybrush/dsdt.asl b/src/mainboard/google/guybrush/dsdt.asl new file mode 100644 index 0000000..a96d47c --- /dev/null +++ b/src/mainboard/google/guybrush/dsdt.asl @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <variant/ec.h> + +/* DefinitionBlock Statement */ +#include <acpi/acpi.h> + +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + + /* global NVS and variables */ + #include <globalnvs.asl> + + /* PCI IRQ mapping for the Southbridge */ + #include <pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <sleepstates.asl> + + /* Contains _SWS methods */ + #include <soc/amd/common/acpi/acpi_wake_source.asl> + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe the SOC */ + #include <soc.asl> + + } /* End \_SB scope */ + + /* Thermal handler */ + #include <variant/acpi/thermal.asl> + + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +} +/* End of ASL file */ diff --git a/src/mainboard/google/guybrush/ec.c b/src/mainboard/google/guybrush/ec.c new file mode 100644 index 0000000..f4f441c --- /dev/null +++ b/src/mainboard/google/guybrush/ec.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <variant/ec.h> + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s3_device_events = MAINBOARD_EC_S3_DEVICE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + }; + + printk(BIOS_DEBUG, "mainboard: EC init\n"); + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c new file mode 100644 index 0000000..7c422f1 --- /dev/null +++ b/src/mainboard/google/guybrush/mainboard.c @@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <string.h> +#include <console/console.h> +#include <cbfs.h> +#include <device/device.h> +#include <device/mmio.h> +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <acpi/acpi_gnvs.h> +#include <amdblocks/amd_pci_util.h> +#include <amdblocks/gpio_banks.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <smbios.h> +#include <soc/cpu.h> +#include <soc/gpio.h> +#include <soc/nvs.h> +#include <soc/pci_devs.h> +#include <soc/platform_descriptors.h> +#include <soc/southbridge.h> +#include <soc/smi.h> +#include <soc/soc_util.h> +#include <amdblocks/acpimmio.h> +#include <variant/ec.h> +#include <variant/thermal.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <commonlib/helpers.h> +#include <bootstate.h> + +#define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN" +#define METHOD_BACKLIGHT_DISABLE "\\_SB.BKDS" +#define METHOD_MAINBOARD_INI "\\_SB.MINI" +#define METHOD_MAINBOARD_WAK "\\_SB.MWAK" +#define METHOD_MAINBOARD_PTS "\\_SB.MPTS" + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + */ +static uint8_t fch_pic_routing[0x80]; +static uint8_t fch_apic_routing[0x80]; + +_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), + "PIC and APIC FCH interrupt tables must be the same size"); + +/* + * This table doesn't actually perform any routing. It only populates the + * PCI_INTERRUPT_LINE register on the PCI device with the PIC value specified + * in fch_apic_routing. The linux kernel only looks at this field as a backup + * if ACPI routing fails to describe the PCI routing correctly. The linux kernel + * also uses the APIC by default, so the value coded into the registers will be + * wrong. + * + * This table is also confusing because PCI Interrupt routing happens at the + * device/slot level, not the function level. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + { PCIE_GPP_0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_1_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 1 - Wifi + { PCIE_GPP_2_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 2 - SD + { PCIE_GPP_3_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_5_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_6_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, // Bridge 6 - NVME + { PCIE_GPP_A_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_B_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, +}; + +/* + * This controls the device -> IRQ routing. + * The PIC values are limited to 0,1, 3 - 12, 14, 15. + */ +static const struct fch_irq_routing { + uint8_t intr_index; + uint8_t pic_irq_num; + uint8_t apic_irq_num; +} fch_pirq[] = { + { PIRQ_A, 6, 16 }, + { PIRQ_B, 6, 17 }, + { PIRQ_C, 14, 18 }, + { PIRQ_D, 15, 19 }, + { PIRQ_SCI, 9, 9 }, + { PIRQ_EMMC, 5, 5 }, + { PIRQ_GPIO, 7, 7 }, + { PIRQ_I2C2, 10, 10 }, + { PIRQ_I2C3, 11, 11 }, + { PIRQ_UART0, 4, 4 }, + { PIRQ_UART1, 3, 3 }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0xf1, 0x00 }, + { PIRQ_MISC1, 0x00, 0x00 }, + { PIRQ_MISC2, 0x00, 0x00 }, +}; + +static void init_tables(void) +{ + const struct fch_irq_routing *entry; + int i; + + memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); + memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); + + for (i = 0; i < ARRAY_SIZE(fch_pirq); i++) { + entry = fch_pirq + i; + fch_pic_routing[entry->intr_index] = entry->pic_irq_num; + fch_apic_routing[entry->intr_index] = entry->apic_irq_num; + } +} + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + init_tables(); + + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); + intr_data_ptr = fch_apic_routing; + picr_data_ptr = fch_pic_routing; +} + +static void mainboard_configure_gpios(void) +{ + size_t base_num_gpios, override_num_gpios; + const struct soc_amd_gpio *base_gpios, *override_gpios; + + base_gpios = variant_base_gpio_table(&base_num_gpios); + override_gpios = variant_override_gpio_table(&override_num_gpios); + + gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios, + override_num_gpios); +} + +static void mainboard_devtree_update(void) +{ + variant_devtree_update(); +} + +static void mainboard_init(void *chip_info) +{ + const struct sci_source *gpes; + size_t num; + int boardid; + + mainboard_ec_init(); + boardid = board_id(); + printk(BIOS_INFO, "Board ID: %d\n", boardid); + + mainboard_configure_gpios(); + + /* Update DUT configuration */ + mainboard_devtree_update(); + + /* + * Some platforms use SCI not generated by a GPIO pin (event above 23). + * For these boards, gpe_configure_sci() is still needed, but all GPIO + * generated events (23-0) must be removed from gpe_table[]. + * For boards that only have GPIO generated events, table gpe_table[] + * must be removed, and get_gpe_table() should return NULL. + */ + gpes = variant_gpe_table(&num); + if (gpes != NULL) + gpe_configure_sci(gpes, num); +} + +void mainboard_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + variant_get_dxio_ddi_descriptors(dxio_descs, dxio_num, ddi_descs, ddi_num); +} + +static void mainboard_write_blken(void) +{ + acpigen_write_method(METHOD_BACKLIGHT_ENABLE, 0); + acpigen_soc_clear_tx_gpio(GPIO_85); + acpigen_pop_len(); +} + +static void mainboard_write_blkdis(void) +{ + acpigen_write_method(METHOD_BACKLIGHT_DISABLE, 0); + acpigen_soc_set_tx_gpio(GPIO_85); + acpigen_pop_len(); +} + +static void mainboard_write_mini(void) +{ + acpigen_write_method(METHOD_MAINBOARD_INI, 0); + acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE); + acpigen_pop_len(); +} + +static void mainboard_write_mwak(void) +{ + acpigen_write_method(METHOD_MAINBOARD_WAK, 0); + acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE); + acpigen_pop_len(); +} + +static void mainboard_write_mpts(void) +{ + acpigen_write_method(METHOD_MAINBOARD_PTS, 0); + acpigen_emit_namestring(METHOD_BACKLIGHT_DISABLE); + acpigen_pop_len(); +} + +static void mainboard_fill_ssdt(const struct device *dev) +{ + mainboard_write_blken(); + mainboard_write_blkdis(); + mainboard_write_mini(); + mainboard_write_mpts(); + mainboard_write_mwak(); +} + +/************************************************* + * Dedicated mainboard function + *************************************************/ +static void guybrush_enable(struct device *dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); + + dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; + dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; + +} + +static void mainboard_final(void *chip_info) +{ + struct global_nvs *gnvs; + + gnvs = acpi_get_gnvs(); + + if (gnvs) { + gnvs->tmps = CTL_TDP_SENSOR_ID; + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + } + + finalize_gpios(acpi_get_sleep_type()); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = guybrush_enable, + .final = mainboard_final, +}; + +void __weak variant_devtree_update(void) +{ +} + +__weak const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + /* Default weak implementation - No overrides. */ + *size = 0; + return NULL; +} diff --git a/src/mainboard/google/guybrush/sku_id.c b/src/mainboard/google/guybrush/sku_id.c new file mode 100644 index 0000000..82ee355 --- /dev/null +++ b/src/mainboard/google/guybrush/sku_id.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <boardid.h> +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> + +uint32_t sku_id(void) +{ + return google_chromeec_get_board_sku(); +} + +/* An unprovisioned SKU ID indicates we're in the factory booting prior to + proper SKU ID provisioning. */ +int boot_is_factory_unprovisioned(void) +{ + return sku_id() == CROS_SKU_UNPROVISIONED; +} diff --git a/src/mainboard/google/guybrush/smihandler.c b/src/mainboard/google/guybrush/smihandler.c new file mode 100644 index 0000000..1c26d45 --- /dev/null +++ b/src/mainboard/google/guybrush/smihandler.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <baseboard/variants.h> +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <gpio.h> +#include <soc/smi.h> +#include <variant/ec.h> +#include <variant/gpio.h> +#include <console/console.h> + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_process_events(); +} +void mainboard_smi_sleep(u8 slp_typ) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); + + gpios = variant_sleep_gpio_table(&num_gpios, slp_typ); + program_gpios(gpios, num_gpios); +} + +int mainboard_smi_apmc(u8 apmc) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + + return 0; +} diff --git a/src/mainboard/google/guybrush/spd/Makefile.inc b/src/mainboard/google/guybrush/spd/Makefile.inc new file mode 100644 index 0000000..d6ae475 --- /dev/null +++ b/src/mainboard/google/guybrush/spd/Makefile.inc @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# This directory +SPD_SOURCES_DIR := src/mainboard/$(MAINBOARDDIR)/spd + +APCB_SOURCES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/APCB_$(f).gen) + +# APCB binary with magic numbers to be replaced by apcb_edit tool +APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATION)/APCB_magic.bin + +$(obj)/APCB_%.gen: $(SPD_SOURCES_DIR)/%.hex \ + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) + $(APCB_EDIT_TOOL) \ + $(APCB_MAGIC_BLOB) \ + $@ \ + --hex \ + --strip_manufacturer_information \ + --spd_0_0 $< \ + $(if $(APCB_POPULATE_2ND_CHANNEL), --spd_1_0 $<, ) \ + --board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \ + --board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \ + --board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \ + --board_id_gpio3 $(APCB_BOARD_ID_GPIO3) diff --git a/src/mainboard/google/guybrush/spd/ddr4-spd-1.hex b/src/mainboard/google/guybrush/spd/ddr4-spd-1.hex new file mode 100644 index 0000000..32d141f --- /dev/null +++ b/src/mainboard/google/guybrush/spd/ddr4-spd-1.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 00 00 00 02 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/guybrush/spd/ddr4-spd-2.hex b/src/mainboard/google/guybrush/spd/ddr4-spd-2.hex new file mode 100644 index 0000000..85b2035 --- /dev/null +++ b/src/mainboard/google/guybrush/spd/ddr4-spd-2.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/guybrush/spd/ddr4-spd-3.hex b/src/mainboard/google/guybrush/spd/ddr4-spd-3.hex new file mode 100644 index 0000000..d2869ea --- /dev/null +++ b/src/mainboard/google/guybrush/spd/ddr4-spd-3.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 00 00 00 02 03 00 00 +00 00 06 07 F8 3F 00 00 73 73 73 11 00 73 F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/guybrush/spd/ddr4-spd-4.hex b/src/mainboard/google/guybrush/spd/ddr4-spd-4.hex new file mode 100644 index 0000000..b676992 --- /dev/null +++ b/src/mainboard/google/guybrush/spd/ddr4-spd-4.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00 +00 00 06 07 FC 3F 00 00 6D 6D 6D 11 00 6D F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 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a/src/mainboard/google/guybrush/spd/ddr4-spd-5.hex b/src/mainboard/google/guybrush/spd/ddr4-spd-5.hex new file mode 100644 index 0000000..d72bf1e --- /dev/null +++ b/src/mainboard/google/guybrush/spd/ddr4-spd-5.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 00 08 00 00 00 00 01 03 00 00 +00 00 06 07 F8 3F 00 00 73 73 73 11 00 73 F0 0A +20 08 00 05 00 A8 18 2B 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 B5 00 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 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b/src/mainboard/google/guybrush/spd/ddr4-spd-6.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 00 00 00 01 03 00 00 +00 00 06 07 F8 3F 00 00 73 73 73 11 00 73 F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 86 86 86 86 D6 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 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00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/guybrush/spd/ddr4-spd-empty.hex b/src/mainboard/google/guybrush/spd/ddr4-spd-empty.hex new file mode 100644 index 0000000..1a5be53 --- /dev/null +++ b/src/mainboard/google/guybrush/spd/ddr4-spd-empty.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/guybrush/spd/ddr4_spd_manifest.generated.txt b/src/mainboard/google/guybrush/spd/ddr4_spd_manifest.generated.txt new file mode 100644 index 0000000..21565c6 --- /dev/null +++ b/src/mainboard/google/guybrush/spd/ddr4_spd_manifest.generated.txt @@ -0,0 +1,16 @@ +H5AN8G6NDJR-XNC,ddr4-spd-1.hex +MT40A512M16TB-062E:J,ddr4-spd-1.hex +H5ANAG6NCMR-XNC,ddr4-spd-2.hex +HMA851S6CJR6N-VK,ddr4-spd-3.hex +K4A8G165WC-BCTD,ddr4-spd-3.hex +H5AN8G6NCJR-VKC,ddr4-spd-3.hex +MT40A1G16KNR-075:E,ddr4-spd-4.hex +K4AAG165WB-MCTD,ddr4-spd-5.hex +H5ANAG6NCMR-VKC,ddr4-spd-6.hex +K4A8G165WC-BCWE,ddr4-spd-1.hex +MT40A1G16KD-062E:E,ddr4-spd-7.hex +K4AAG165WA-BCWE,ddr4-spd-7.hex +H5AN8G6NCJR-XNC,ddr4-spd-1.hex +K4AAG165WA-BCTD,ddr4-spd-8.hex +H5ANAG6NDMR-XNC,ddr4-spd-2.hex +H5ANAG6NCJR-XNC,ddr4-spd-9.hex diff --git a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc new file mode 100644 index 0000000..a0a5a27 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += gpio_baseboard_common.c +bootblock-y += helpers.c +bootblock-y += gpio_baseboard.c + +verstage-y += gpio_baseboard_common.c +verstage-y += helpers.c +verstage-y += gpio_baseboard.c +verstage-y += tpm_tis.c + +romstage-y += gpio_baseboard_common.c +romstage-y += helpers.c +romstage-y += gpio_baseboard.c +romstage-y += tpm_tis.c + +ramstage-y += gpio_baseboard_common.c +ramstage-y += gpio_baseboard.c +ramstage-y += fsps_baseboard.c +ramstage-y += helpers.c +ramstage-y += tpm_tis.c + +smm-y += gpio_baseboard.c + +# Add OEM ID table +ifeq ($(CONFIG_USE_OEM_BIN),y) +cbfs-files-y += oem.bin +oem.bin-file := $(call strip_quotes,$(CONFIG_OEM_BIN_FILE)) +oem.bin-type := raw +endif #($(CONFIG_USE_OEM_BIN),y) + +# APCB Board ID GPIO configuration. +# These GPIOs determine which memory SPD will be used during boot. +# APCB_BOARD_ID_GPIO[0-3] = GPIO_NUMBER GPIO_IO_MUX GPIO_BANK_CTL +# GPIO_NUMBER: FCH GPIO number +# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO +# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO +# APCB_POPULATE_2ND_CHANNEL: Populates 2nd memory channel in APCB when true. +# Guybrush based boards select 1 or 2 channels based on AGPIO84 +APCB_BOARD_ID_GPIO0 = 121 1 0 +APCB_BOARD_ID_GPIO1 = 120 1 0 +APCB_BOARD_ID_GPIO2 = 131 3 0 +APCB_BOARD_ID_GPIO3 = 116 1 0 +APCB_POPULATE_2ND_CHANNEL = true diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb new file mode 100644 index 0000000..4181b4a --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -0,0 +1,413 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Set FADT Configuration + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + # See table 5-34 ACPI 6.3 spec + register "fadt_flags" = "ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_SEALED_CASE" + + register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" + register "acp_i2s_wake_enable" = "0" + register "acp_pme_enable" = "0" + + # Start : OPN Performance Configuration + # (Configuratin that is common for all variants) + # For the below fields, 0 indicates use SOC default + + # PROCHOT_L de-assertion Ramp Time + register "prochot_l_deassertion_ramp_time_ms" = "20" + + # Lower die temperature limit + register "thermctl_limit_degreeC" = "100" + + # FP5 Processor Voltage Supply PSI Currents + register "psi0_current_limit_mA" = "18000" + register "psi0_soc_current_limit_mA" = "12000" + register "vddcr_soc_voltage_margin_mV" = "0" + register "vddcr_vdd_voltage_margin_mV" = "0" + + # VRM Limits + register "vrm_maximum_current_limit_mA" = "0" + register "vrm_soc_maximum_current_limit_mA" = "0" + register "vrm_current_limit_mA" = "0" + register "vrm_soc_current_limit_mA" = "0" + + # Misc SMU settings + register "sb_tsi_alert_comparator_mode_en" = "0" + register "core_dldo_bypass" = "1" + register "min_soc_vid_offset" = "0" + register "aclk_dpm0_freq_400MHz" = "0" + + # End : OPN Performance Configuration + + register "emmc_config" = "{ + .timing = SD_EMMC_EMMC_HS400, + .sdr104_hs400_driver_strength = SD_EMMC_DRIVE_STRENGTH_A, + /* + * The reference design was missing a pull-up on the CMD line. + * This means we can't run at the full 400 kHz. By setting this + * to 1 we run at the slowest frequency possible by the + * controller (~97 kHz). + * + * Boards that have the pull-up should correctly set this. + */ + .init_khz_preset = 1, + }" + + register "has_usb2_phy_tune_params" = "1" + + # Controller0 Port0 Default + register "usb_2_port_tune_params[0]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port1 Default + register "usb_2_port_tune_params[1]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port2 Default + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller0 Port3 Default + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x6, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller1 Port0 Default + register "usb_2_port_tune_params[4]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # Controller1 Port1 Default + register "usb_2_port_tune_params[5]" = "{ + .com_pds_tune = 0x03, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x02, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .tx_vref_tune = 0x5, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + # SPI Configuration + register "common_config.spi_config" = "{ + .normal_speed = SPI_SPEED_33M, /* MHz */ + .fast_speed = SPI_SPEED_66M, /* MHz */ + .altio_speed = SPI_SPEED_66M, /* MHz */ + .tpm_speed = SPI_SPEED_66M, /* MHz */ + .read_mode = SPI_READ_MODE_DUAL122, + }" + + # USB OC pin mapping + register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0" # USB C0 + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0 + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_1" # USB A1 + register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_1" # USB C1 + register "usb_port_overcurrent_pin[4]" = "USB_OC_NONE" # Camera or internal hub + register "usb_port_overcurrent_pin[5]" = "USB_OC_NONE" # Bluetooth + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x62, + /* + * Only 0x62 and 0x66 are required. But, this is not supported by + * standard IO decodes and there are only 4 generic I/O windows + * available. Hence, open a window from 0x62-0x67. + */ + .size = 5, + }, + .generic_io_range[1] = { + .base = 0x800, /* EC_HOST_CMD_REGION0 */ + .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ + }, + .generic_io_range[2] = { + .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ + .size = 255, /* EC_MEMMAP_SIZE */ + }, + .generic_io_range[3] = { + .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ + .size = 8, /* 0x200 - 0x207 */ + }, + + .io_mode = ESPI_IO_MODE_QUAD, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .dedicated_alert_pin = 1, + .periph_ch_en = 1, + .vw_ch_en = 1, + .oob_ch_en = 0, + .flash_ch_en = 0, + + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), + }" + + register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL" + + # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader + register "gpp_clk_config[2]" = "GPP_CLK_OFF" + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_REQ" # NVME SSD + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + + device cpu_cluster 0 on + device lapic 0 on end + end + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge, must be enabled + device pci 1.1 off end # GPP Bridge 0 + device pci 1.2 on # GPP Bridge 1 - Wifi + chip drivers/wifi/generic + register "wake" = "GEVENT_8" + device pci 00.0 on end + end + end + device pci 1.3 on end # GPP Bridge 2 - SD + device pci 1.4 off end # GPP Bridge 3 + device pci 1.5 off end # GPP Bridge 4 + device pci 1.6 off end # GPP Bridge 5 + device pci 1.7 on end # GPP Bridge 6 - NVME + device pci 8.0 on end # Dummy Host Bridge, must be enabled + device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device pci 0.0 on end # Internal GPU + device pci 0.1 on end # Display HDA + device pci 0.2 on end # Crypto Coprocesor + device pci 0.3 on # USB 3.1 + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on end + end + + # The following devices are only enabled on Dali SKUs + chip drivers/usb/acpi + register "desc" = ""User-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_14)" + device usb 2.5 on end + end + end + end + end + device pci 0.4 on # USB 3.1 + chip drivers/usb/acpi + # The following devices are only enabled on Picasso SKUs + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""User-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_14)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""World-Facing Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.0 on end + end + end + end + end + device pci 0.5 on + chip drivers/amd/i2s_machine_dev + register "hid" = ""AMDI5682"" + # DMIC select GPIO for ACP machine device + # This GPIO is used to select DMIC0 or DMIC1 by the + # kernel driver. It does not really have a polarity + # since low and high control the selection of DMIC and + # hence does not have an active polarity. + # Kernel driver does not use the polarity field and + # instead treats the GPIO selection as follows: + # Set low (0) = Select DMIC0 + # Set high (1) = Select DMIC1 + register "dmic_select_gpio" = "ACPI_GPIO_OUTPUT(GPIO_67)" + device generic 0.0 on end + end + end # Audio + device pci 0.6 off end # HDA + device pci 0.7 on end # non-Sensor Fusion Hub device + end + device pci 8.2 off # Internal GPP Bridge 0 to Bus B + device pci 0.0 off end # AHCI + end + device pci 14.0 on end # SM + device pci 14.3 on # - D14F3 bridge + chip ec/google/chromeec + device pnp 0c09.0 on + chip ec/google/chromeec/i2c_tunnel + register "uid" = "1" + register "remote_bus" = "8" + device generic 0.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_29)" + register "property_count" = "2" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" + device i2c 1a on end + end + end + end + chip ec/google/chromeec/i2c_tunnel + register "name" = ""MSTH"" + register "uid" = "1" + register "remote_bus" = "9" + device generic 1.0 on end + end + chip ec/google/chromeec/audio_codec + register "uid" = "1" + device generic 0 on end + end + end + end + end + device pci 14.6 off end # Non-Functional SDHCI + device pci 18.0 on end # Data fabric [0-7] + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + end # domain + + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_91)" + register "sdmode_delay" = "5" + device generic 0.1 on end + end + + device mmio 0xfedc5000 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" + device i2c 50 on end + end + end + + device mmio 0xfedca000 off end # UART1 + device mmio 0xfedce000 off end # UART2 + device mmio 0xfedcf000 off end # UART3 + +end # chip soc/amd/picasso diff --git a/src/mainboard/google/guybrush/variants/baseboard/fsps_baseboard.c b/src/mainboard/google/guybrush/variants/baseboard/fsps_baseboard.c new file mode 100644 index 0000000..49d8ade --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/fsps_baseboard.c @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/bsd/compiler.h> +#include <soc/soc_util.h> + +void __weak variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num) +{ + *dxio_descs = baseboard_get_dxio_descriptors(dxio_num); + *ddi_descs = baseboard_get_ddi_descriptors(ddi_num); +} + +/* FP5 package can support Type 1 (Picasso) and Type 2 (Dali), however some + * Type 1 parts, while reporting as Picasso through cpuid, are fused like a Dali. + * Those parts need to be configured as Type 2. */ + +static const fsp_dxio_descriptor pco_dxio_descriptors[] = { + { + // NVME SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 0, + .end_logical_lane = 3, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ4, + }, + { + // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 4, + .end_logical_lane = 4, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0, + }, + { + // SD Reader + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 5, + .end_logical_lane = 5, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1, + } +}; + +static const fsp_dxio_descriptor dali_dxio_descriptors[] = { + { + // NVME SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 0, + .end_logical_lane = 1, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ4, + }, + { + // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 4, + .end_logical_lane = 4, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0, + }, + { + // SD Reader + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 5, + .end_logical_lane = 5, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1, + } +}; + +const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num) +{ + /* Type 2 or Type 1 fused like Type 2. */ + if (soc_is_reduced_io_sku()) { + *num = ARRAY_SIZE(dali_dxio_descriptors); + return dali_dxio_descriptors; + } else { + /* Type 1 */ + *num = ARRAY_SIZE(pco_dxio_descriptors); + return pco_dxio_descriptors; + } + +} + +static const fsp_ddi_descriptor pco_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT1 HDMI + .connector_type = HDMI, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DDI2, DP2, DB OPT1 USB-C1 + .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + }, + { + // DDI3, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +static const fsp_ddi_descriptor dali_ddi_descriptors[] = { + { + // DDI0, DP0, eDP + .connector_type = EDP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { + // DDI1, DP1, DB OPT2 USB-C1 / DB OPT3 MST hub + .connector_type = DP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { + // DDI2, DP3, USB-C0 + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +const fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num) +{ + /* Type 2 or Type 1 fused like Type 2. */ + if (soc_is_reduced_io_sku()) { + *num = ARRAY_SIZE(dali_ddi_descriptors); + return dali_ddi_descriptors; + } else { + /* Type 1 */ + *num = ARRAY_SIZE(pco_ddi_descriptors); + return pco_ddi_descriptors; + } +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio_baseboard.c b/src/mainboard/google/guybrush/variants/baseboard/gpio_baseboard.c new file mode 100644 index 0000000..90cd588 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio_baseboard.c @@ -0,0 +1,307 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <baseboard/variants.h> +#include <delay.h> +#include <ec/google/chromeec/ec.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <soc/smi.h> +#include <stdlib.h> +#include <boardid.h> +#include <variant/gpio.h> + +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* PWR_BTN_L */ + PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), + /* SYS_RESET_L */ + PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), + /* WIFI_PCIE_WAKE_ODL */ + PAD_SCI(GPIO_2, PULL_NONE, EDGE_LOW), + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* PEN_DETECT_ODL */ + PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3), + /* PEN_POWER_EN - Enabled*/ + PAD_GPO(GPIO_5, HIGH), + /* FPMCU_INT_L */ + PAD_SCI(GPIO_6, PULL_NONE, LEVEL_LOW), + /* I2S_SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S_LRCLK - Bit banged in depthcharge */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* TOUCHPAD_INT_ODL */ + PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), + /* S0iX SLP - (unused - goes to EC & FPMCU */ + PAD_NC(GPIO_10), + /* USI_INT_ODL */ + PAD_GPI(GPIO_12, PULL_NONE), + /* EN_PWR_TOUCHPAD_PS2 */ + PAD_GPO(GPIO_13, HIGH), + /* BT_DISABLE */ + PAD_GPO(GPIO_14, LOW), + /* GPIO_15: Not available */ + /* USB_OC0_L - USB C0 + USB A0 */ + PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), + /* USB_OC1_L - USB C1 + USB A1 */ + PAD_NF(GPIO_17, USB_OC1_L, PULL_NONE), + /* WIFI_DISABLE */ + PAD_GPO(GPIO_18, LOW), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* EMMC_CMD */ + PAD_NF(GPIO_21, EMMC_CMD, PULL_NONE), + /* EC_FCH_SCI_ODL */ + PAD_SCI(GPIO_22, PULL_NONE, EDGE_LOW), + /* AC_PRES */ + PAD_NF(GPIO_23, AC_PRES, PULL_UP), + /* EC_FCH_WAKE_L */ + PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW), + /* GPIO_25: Not available */ + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* PCIE_RST1_L (unused) */ + PAD_NC(GPIO_27), + /* GPIO_28: Not available */ + /* GPIO_29: HP_INT_ODL */ + PAD_GPI(GPIO_29, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* EC_AP_INT_ODL (Sensor Framesync) */ + PAD_GPI(GPIO_31, PULL_NONE), + /* GPIO_33 - GPIO_39: Not available */ + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, HIGH), + /* GPIO_41: Not available */ + /* GPIO_42: Handled in bootblock for wifi power/reset control. */ + /* GPIO_43 - GPIO_66: Not available */ + /* DMIC SEL */ + /* + * Make sure Ext ROM Sharing is disabled before using this GPIO. Otherwise SPI flash + * access will be very slow. + */ + PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic + /* EMMC_RESET_L */ + PAD_GPO(GPIO_68, HIGH), + /* FPMCU_BOOT0 */ + PAD_GPO(GPIO_69, LOW), + /* EMMC_CLK */ + PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), + /* GPIO_71 - GPIO_73: Not available */ + /* EMMC_DATA4 */ + PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE), + /* EMMC_DATA6 */ + PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, HIGH), + /* GPIO_77 - GPIO_83: Not available */ + /* RAM_ID_4 */ + PAD_GPI(GPIO_84, PULL_NONE), + /* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */ + PAD_GPO(GPIO_85, HIGH), + /* WIFI_AUX_RESET_L */ + PAD_GPO(GPIO_86, HIGH), + /* EMMC_DATA7 */ + PAD_NF(GPIO_87, EMMC_DATA7, PULL_NONE), + /* EMMC_DATA5 */ + PAD_NF(GPIO_88, EMMC_DATA5, PULL_NONE), + /* GPIO_89 - unused */ + PAD_NC(GPIO_89), + /* EN_PWR_TOUCHSCREEN */ + PAD_GPO(GPIO_90, LOW), + /* EN_SPKR */ + PAD_GPO(GPIO_91, LOW), + /* CLK_REQ0_L - WIFI */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* GPIO_93 - GPIO_103: Not available */ + /* EMMC_DATA0 */ + PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE), + /* EMMC_DATA1 */ + PAD_NF(GPIO_105, EMMC_DATA1, PULL_NONE), + /* EMMC_DATA2 */ + PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE), + /* EMMC_DATA3 */ + PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP), + /* EMMC_DS */ + PAD_NF(GPIO_109, EMMC_DS, PULL_NONE), + /* GPIO_110 - GPIO112: Not available */ + /* I2C2_SCL - USI/Touchpad */ + PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), + /* I2C2_SDA - USI/Touchpad */ + PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), + /* CLK_REQ1_L - SD Card */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* RAM_ID_3 */ + PAD_GPI(GPIO_116, PULL_NONE), + /* GPIO_117 - GPIO_119: Not available */ + /* RAM_ID_1 */ + PAD_GPI(GPIO_120, PULL_NONE), + /* RAM_ID_0 */ + PAD_GPI(GPIO_121, PULL_NONE), + /* GPIO_122 - GPIO_128: Not available */ + /* KBRST_L */ + PAD_NF(GPIO_129, KBRST_L, PULL_NONE), + /* EC_IN_RW_OD */ + PAD_GPI(GPIO_130, PULL_NONE), + /* RAM_ID_2 */ + PAD_GPI(GPIO_131, PULL_NONE), + /* CLK_REQ4_L - SSD */ + PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), + /* GPIO_133 - GPIO_134: Not available */ + /* DEV_BEEP_CODEC_IN (Dev beep Data out) */ + PAD_GPI(GPIO_135, PULL_NONE), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* BIOS_FLASH_WP_ODL */ + PAD_GPI(GPIO_137, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + /* DEV_BEEP_BCLK */ + PAD_GPI(GPIO_139, PULL_NONE), + /* USI_RESET_L */ + PAD_GPO(GPIO_140, LOW), + /* UART1_RXD - FPMCU */ + PAD_NF(GPIO_141, UART1_RXD, PULL_NONE), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_142, HIGH), + /* UART1_TXD - FPMCU */ + PAD_NF(GPIO_143, UART1_TXD, PULL_NONE), + /* USI_REPORT_EN */ + PAD_GPO(GPIO_144, LOW), +}; + +const __weak +struct soc_amd_gpio *variant_base_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} + +/* + * This function is still needed for boards that sets gevents above 23 + * that will generate SCI or SMI. Normally this function + * points to a table of gevents and what needs to be set. The code that + * calls it was modified so that when this function returns NULL then the + * caller does nothing. + */ +const __weak struct sci_source *variant_gpe_table(size_t *num) +{ + return NULL; +} + +static void wifi_power_reset_configure(void) +{ + /* + * Configure WiFi GPIOs such that: + * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device. + * - Enable power to WiFi using EN_PWR_WIFI_L. + * - Wait for >50ms after power to WiFi is enabled. (Time between bootblock & ramstage) + * - WIFI_AUX_RESET_L gets deasserted later in mainboard_configure_gpios in ramstage + */ + static const struct soc_amd_gpio v3_wifi_table[] = { + /* WIFI_AUX_RESET_L */ + PAD_GPO(GPIO_86, LOW), + /* EN_PWR_WIFI_L */ + PAD_GPO(GPIO_42, LOW), + }; + program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); +} + +__weak void variant_pcie_gpio_configure(void) +{ + static const struct soc_amd_gpio pcie_gpio_table[] = { + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, HIGH), + /* CLK_REQ0_L - WIFI */ + PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), + /* CLK_REQ1_L - SD Card */ + PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), + /* CLK_REQ4_L - SSD */ + PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), + /* SD_AUX_RESET_L */ + PAD_GPO(GPIO_142, HIGH), + }; + + program_gpios(pcie_gpio_table, ARRAY_SIZE(pcie_gpio_table)); + + wifi_power_reset_configure(); +} + +__weak void finalize_gpios(int slp_typ) +{ + if (variant_has_fingerprint() && slp_typ != ACPI_S3) { + + if (fpmcu_needs_delay()) + mdelay(550); + + /* + * Enable the FPMCU by enabling EN_PWR_FP, then bringing it out + * of reset by setting FPMCU_RST_L high 3ms later. + */ + gpio_set(GPIO_32, 1); + mdelay(3); + gpio_set(GPIO_11, 1); + } +} + +static const struct soc_amd_gpio gpio_fingerprint_bootblock_table[] = { + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), +}; + +static const struct soc_amd_gpio gpio_no_fingerprint_bootblock_table[] = { + /* FPMCU_RST_L */ + PAD_NC(GPIO_11), + /* EN_PWR_FP */ + PAD_NC(GPIO_32), +}; + +const __weak struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ) +{ + if (variant_has_fingerprint()) { + if (slp_typ == ACPI_S3) + return NULL; + + *size = ARRAY_SIZE(gpio_fingerprint_bootblock_table); + return gpio_fingerprint_bootblock_table; + } + + *size = ARRAY_SIZE(gpio_no_fingerprint_bootblock_table); + return gpio_no_fingerprint_bootblock_table; +} + +static const struct soc_amd_gpio gpio_sleep_table[] = { + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, LOW), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, LOW), +}; + +static const struct soc_amd_gpio gpio_fp_shutdown_table[] = { + /* NVME_AUX_RESET_L */ + PAD_GPO(GPIO_40, LOW), + /* EN_PWR_CAMERA */ + PAD_GPO(GPIO_76, LOW), + + /* FPMCU_RST_L */ + PAD_GPO(GPIO_11, LOW), + /* EN_PWR_FP */ + PAD_GPO(GPIO_32, LOW), +}; + +const __weak struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ) +{ + if (slp_typ == SLP_TYP_S5) { + *size = ARRAY_SIZE(gpio_fp_shutdown_table); + return gpio_fp_shutdown_table; + } + + *size = ARRAY_SIZE(gpio_sleep_table); + return gpio_sleep_table; +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio_baseboard_common.c b/src/mainboard/google/guybrush/variants/baseboard/gpio_baseboard_common.c new file mode 100644 index 0000000..0b658a4 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio_baseboard_common.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <soc/gpio.h> +#include <stdlib.h> +#include <boardid.h> +#include <variant/gpio.h> + +static const struct soc_amd_gpio early_gpio_table[] = { + /* H1_FCH_INT_ODL */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS), + /* I2C3_SCL - H1 */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA - H1 */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* PCIE_RST0_L - Fixed timings */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* FCH_ESPI_EC_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_NONE), + /* UART0_RXD - DEBUG */ + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + /* UART0_TXD - DEBUG */ + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), +}; + +const __weak struct soc_amd_gpio *variant_early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/helpers.c b/src/mainboard/google/guybrush/variants/baseboard/helpers.c new file mode 100644 index 0000000..e32ef12 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/helpers.c @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <inttypes.h> +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> + +/* Global definitions for FW_CONFIG values */ +enum { + /* Daughterboard index for attributes. */ + FW_CONFIG_MASK_DB_INDEX = 0xf, + FW_CONFIG_DB_INDEX_SHIFT = 0, + /* Mainboard USB index for attributes. */ + FW_CONFIG_MASK_MB_USB_INDEX = 0xf, + FW_CONFIG_MB_USB_INDEX_SHIFT = 4, + /* Lid accelerometer properties. */ + FW_CONFIG_MASK_LID_ACCEL = 0x7, + FW_CONFIG_LID_ACCEL_SHIFT = 8, + /* Base gyro sensor properties. */ + FW_CONFIG_MASK_BASE_GYRO = 0x7, + FW_CONFIG_BASE_GYRO_SHIFT = 11, + /* Keyboard backlight presence */ + FW_CONFIG_MASK_KEYB_BL = 0x1, + FW_CONFIG_KEYB_BL_SHIFT = 14, + /* Tablet mode supported through lid angle */ + FW_CONFIG_MASK_LID_ANGLE_TABLET_MODE = 0x1, + FW_CONFIG_LID_ANGLE_TABLET_MODE_SHIFT = 15, + /* Stylus presence */ + FW_CONFIG_MASK_STYLUS = 0x1, + FW_CONFIG_STYLUS_SHIFT = 16, + /* Fingerprint sensor presence */ + FW_CONFIG_MASK_FP = 0x1, + FW_CONFIG_SHIFT_FP = 17, + /* NVME presence */ + FW_CONFIG_MASK_NVME = 0x1, + FW_CONFIG_SHIFT_NVME = 18, + /* EMMC presence */ + FW_CONFIG_MASK_EMMC = 0x1, + FW_CONFIG_SHIFT_EMMC = 19, + /* SD controller type */ + FW_CONFIG_MASK_SD_CTRLR = 0x7, + FW_CONFIG_SHIFT_SD_CTRLR = 20, + /* SPI speed value */ + FW_CONFIG_MASK_SPI_SPEED = 0xf, + FW_CONFIG_SHIFT_SPI_SPEED = 23, + /* Fan information */ + FW_CONFIG_MASK_FAN = 0x3, + FW_CONFIG_SHIFT_FAN = 27, +}; + +static int get_fw_config(uint64_t *val) +{ + static uint64_t known_value; + + if (known_value) { + *val = known_value; + return 0; + } + + if (google_chromeec_cbi_get_fw_config(&known_value) != 0) { + printk(BIOS_ERR, "FW_CONFIG not set in CBI\n"); + return -1; + } + + *val = known_value; + + return 0; +} + +static unsigned int extract_field(uint64_t mask, int shift) +{ + uint64_t fw_config; + + /* On errors nothing is assumed to be set. */ + if (get_fw_config(&fw_config)) + return 0; + + return (fw_config >> shift) & mask; +} + +int variant_has_emmc(void) +{ + return !!extract_field(FW_CONFIG_MASK_EMMC, FW_CONFIG_SHIFT_EMMC); +} + +int variant_has_nvme(void) +{ + return !!extract_field(FW_CONFIG_MASK_NVME, FW_CONFIG_SHIFT_NVME); +} + +int variant_get_daughterboard_id(void) +{ + return extract_field(FW_CONFIG_MASK_DB_INDEX, FW_CONFIG_DB_INDEX_SHIFT); +} + +bool variant_has_fingerprint(void) +{ + if (CONFIG(VARIANT_HAS_FPMCU)) + return true; + + return false; +} + +bool fpmcu_needs_delay(void) +{ + /* + * Older board versions need an extra delay here to finish resetting + * the FPMCU. The resistor value in the glitch prevention circuit was + * sized so that the FPMCU doesn't turn of for ~1 second. On newer + * boards, that's been updated to ~30ms, which allows the FPMCU's + * reset to be completed in the time between bootblock and finalize. + */ + uint32_t board_version; + + if (google_chromeec_cbi_get_board_version(&board_version)) + board_version = 1; + + if (board_version <= CONFIG_VARIANT_MAX_BOARD_ID_BROKEN_FMPCU_POWER) + return true; + + return false; +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/acpi/thermal.asl b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/acpi/thermal.asl new file mode 100644 index 0000000..dec33ec --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/acpi/thermal.asl @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <variant/thermal.h> + +/* Thermal Zone */ + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + /* Thermal constants for passive cooling */ + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + /* Thermal zone polling frequency: 10 seconds */ + Name (_TZP, 100) + + /* Thermal sampling period for passive cooling: 2 seconds */ + Name (_TSP, 20) + + /* Convert from Degrees C to 1/10 Kelvin for ACPI */ + Method (CTOK, 1) { + /* 10th of Degrees C */ + Local0 = Arg0 * 10 + + /* Convert to Kelvin */ + Local0 += 2732 + + Return (Local0) + } + + /* Threshold for OS to shutdown */ + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + /* Threshold for passive cooling */ + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + /* Processors used for passive cooling */ + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (_TMP, 0, Serialized) + { + /* Get temperature from EC in deci-kelvin */ + Local0 = \_SB.PCI0.LPCB.EC0.TSRD (TMPS) + + /* Critical temperature in deci-kelvin */ + Local1 = CTOK (\TCRT) + + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 + + /* Wait 1 second for EC to re-poll */ + Sleep (1000) + + /* Re-read temperature from EC */ + Local0 = \_SB.PCI0.LPCB.EC0.TSRD (TMPS) + + Debug = "RE-READ TEMPERATURE" + Debug = Local0 + } + + Return (Local0) + } + + } +} diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000..dc06a78 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <variant/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* EC device events to enable and log in S3 */ +#define MAINBOARD_EC_S3_DEVICE_EVENTS 0 + +/* Enable LID switch */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN EC_WAKE_GPI + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* + * Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in + * variant/gpio.h + */ +#define EC_ENABLE_SYNC_IRQ_GPIO + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + +#endif diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000..b1dcd66 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#ifndef __ACPI__ +#include <soc/gpio.h> +#include <platform_descriptors.h> + +#define EC_IN_RW_OD GPIO_130 + +/* SPI Write protect */ +#define CROS_WP_GPIO GPIO_137 +#define GPIO_EC_IN_RW EC_IN_RW_OD + +#endif /* _ACPI__ */ + +/* These define the GPE, not the GPIO. */ +#define EC_SCI_GPI 3 /* eSPI system event -> GPE 3 */ +#define EC_WAKE_GPI 15 /* AGPIO 24 -> GPE 15 */ + +/* EC sync irq */ +#define EC_SYNC_IRQ 31 + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/thermal.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/thermal.h new file mode 100644 index 0000000..b3c951b --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/thermal.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef THERMAL_H +#define THERMAL_H + +/* + * Picasso Thermal Requirements + * TDP (W) 15 + * T die,max (°C) 105 + * T ctl,max 105 + * T die,lmt (default) 100 + * T ctl,lmt (default) 100 + */ + +/* Control TDP Settings */ +#define CTL_TDP_SENSOR_ID 2 /* EC TIN2 */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 104 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +#endif diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..898584b --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <stddef.h> +#include <boardid.h> +#include <ec/google/chromeec/ec.h> +#include <soc/platform_descriptors.h> +#include "chip.h" + +const struct sci_source *variant_gpe_table(size_t *num); +const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); +/* + * This function provides base GPIO configuration table. It is typically provided by + * baseboard using a weak implementation. If GPIO configuration for a variant differs + * significantly from the baseboard, then the variant can also provide a strong implementation + * of this function. + */ +const struct soc_amd_gpio *variant_base_gpio_table(size_t *size); +/* + * This function allows variant to override any GPIOs that are different than the base GPIO + * configuration provided by variant_base_gpio_table(). + */ +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size); + +/* This function provides GPIO init in bootblock. */ +const struct soc_amd_gpio *variant_bootblock_gpio_table(size_t *size, int slp_typ); + +/* + * This function provides GPIO table for the pads that need to be configured when entering + * sleep. + */ +const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ); + +/* Program any required GPIOs at the finalize phase */ +void finalize_gpios(int slp_typ); +/* Modify devictree settings during ramstage. */ +void variant_devtree_update(void); +/* Configure PCIe GPIOs as per variant sequencing requirements. */ +void variant_pcie_gpio_configure(void); + +/* Per variant FSP-S initialization, default implementation in baseboard and + * overrideable by the variant. */ +void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs, + size_t *dxio_num, + const fsp_ddi_descriptor **ddi_descs, + size_t *ddi_num); + +/* Provide the descriptors for the associated baseboard for the variant. These functions + * can be used for obtaining the baseboard's descriptors if the variant followed the + * baseboard. */ +const fsp_dxio_descriptor *baseboard_get_dxio_descriptors(size_t *num); +const fsp_ddi_descriptor *baseboard_get_ddi_descriptors(size_t *num); + +/* Retrieve attributes from FW_CONFIG in CBI. */ +/* Return 0 if non-existent, 1 if present. */ +int variant_has_emmc(void); +/* Return 0 if non-existent, 1 if present. */ +int variant_has_nvme(void); + +/* Determine if booting in factory by using CROS_SKU_UNPROVISIONED. */ +int boot_is_factory_unprovisioned(void); + +/* Return value of daughterboard ID */ +int variant_get_daughterboard_id(void); +/* Return true if the board has a fingerprint sensor. */ +bool variant_has_fingerprint(void); +/* Return true if the board needs an extra fpmcu delay. */ +bool fpmcu_needs_delay(void); + +#endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/guybrush/variants/baseboard/tpm_tis.c b/src/mainboard/google/guybrush/variants/baseboard/tpm_tis.c new file mode 100644 index 0000000..46952c3 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/tpm_tis.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <security/tpm/tis.h> +#include <soc/gpio.h> +#include <variant/gpio.h> + +int tis_plat_irq_status(void) +{ + return gpio_interrupt_status(GPIO_3); +} diff --git a/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc new file mode 100644 index 0000000..57e7136 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd + +ramstage-y += gpio.c diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c new file mode 100644 index 0000000..f2fc794 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <ec/google/chromeec/ec.h> + +static const struct soc_amd_gpio bid1_bid2_gpio_set_stage_ram[] = { + /* DMIC_SEL */ + PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic + /* USB_OC4_L - USB_A1 */ + PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE), + /* USB_OC2_L - USB A0 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), + /* EN_PWR_TOUCHPAD_PS2 */ + PAD_GPO(GPIO_67, HIGH), + /* DMIC_AD_EN */ + PAD_GPO(GPIO_84, HIGH), + /* MST_GPIO_2 (Fw Update HDMI hub) */ + PAD_GPI(GPIO_86, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* MST_GPIO_3 (Fw Update HDMI hub) */ + PAD_GPI(GPIO_90, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), +}; + +static const struct soc_amd_gpio bid3_gpio_set_stage_ram[] = { + /* DMIC_SEL */ + PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic + /* USB_OC4_L - USB_A1 */ + PAD_NF(GPIO_14, USB_OC4_L, PULL_NONE), + /* USB_OC2_L - USB A0 */ + PAD_NF(GPIO_18, USB_OC2_L, PULL_NONE), + /* EN_PWR_WIFI */ + PAD_GPO(GPIO_29, HIGH), + /* EN_PWR_TOUCHPAD_PS2 */ + PAD_GPO(GPIO_67, HIGH), + /* MST_GPIO_2 (Fw Update HDMI hub) */ + PAD_GPI(GPIO_86, PULL_NONE), + /* EN_DEV_BEEP_L */ + PAD_GPO(GPIO_89, HIGH), + /* MST_GPIO_3 (Fw Update HDMI hub) */ + PAD_GPI(GPIO_90, PULL_NONE), + /* USI_RESET */ + PAD_GPO(GPIO_140, HIGH), +}; + +const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) +{ + uint32_t board_version; + + /* + * If board version cannot be read, assume that this is an older revision of the board + * and so apply overrides. If board version is provided by the EC, then apply overrides + * if version < 2. + */ + if (google_chromeec_cbi_get_board_version(&board_version) != 0) + board_version = 1; + + if (board_version <= 2) { + *size = ARRAY_SIZE(bid1_bid2_gpio_set_stage_ram); + return bid1_bid2_gpio_set_stage_ram; + } else if (board_version <= 3) { + *size = ARRAY_SIZE(bid3_gpio_set_stage_ram); + return bid3_gpio_set_stage_ram; + } + + *size = 0; + return NULL; +} diff --git a/src/mainboard/google/guybrush/variants/guybrush/include/variant/acpi/thermal.asl b/src/mainboard/google/guybrush/variants/guybrush/include/variant/acpi/thermal.asl new file mode 100644 index 0000000..7a793d8 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/guybrush/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/guybrush/variants/guybrush/include/variant/ec.h b/src/mainboard/google/guybrush/variants/guybrush/include/variant/ec.h new file mode 100644 index 0000000..9e61a44 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/guybrush/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/ec.h> diff --git a/src/mainboard/google/guybrush/variants/guybrush/include/variant/gpio.h b/src/mainboard/google/guybrush/variants/guybrush/include/variant/gpio.h new file mode 100644 index 0000000..dfaeec3 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/guybrush/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/guybrush/variants/guybrush/include/variant/thermal.h b/src/mainboard/google/guybrush/variants/guybrush/include/variant/thermal.h new file mode 100644 index 0000000..2af6479 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/guybrush/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/thermal.h> diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb new file mode 100644 index 0000000..6bf0632 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #55593 Chapter 3.2 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "2" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "200" + register "sustained_power_limit_mW" = "15000" + + register "telemetry_vddcr_vdd_slope_mA" = "71222" + register "telemetry_vddcr_vdd_offset" = "0" + register "telemetry_vddcr_soc_slope_mA" = "28977" + register "telemetry_vddcr_soc_offset" = "0" + + # End : OPN Performance Configuration + + # USB OC pin mapping + register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_2" # USB A0 + register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_4" # USB A1 + + # Enable I2C2 for trackpad, touchscreen, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 21, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 76, /* 2.31 to 0 */ + }" + + # Enable I2C3 for H1 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 125, /* 0 to 1.26v (1.8 * .7) */ + .fall_time_ns = 37, /* 1.26v to 0 */ + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + end # domain + + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + register "wake" = "GEVENT_22" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" + register "generic.wake" = "GEVENT_22" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + # 32ms: Rise time of the reset line + # 20ms: Firmware ready time + register "reset_delay_ms" = "32 + 20" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_144)" + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" + register "reset_delay_ms" = "20" + register "has_power_resource" = "1" + device i2c 10 on end + end + end + + device mmio 0xfedca000 on + chip drivers/uart/acpi + register "name" = ""CRFP"" + register "desc" = ""Fingerprint Reader"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cros-ec-uart"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_6)" + register "wake" = "GEVENT_10" + register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" + device generic 0 on end + end + end + +end # chip soc/amd/picasso diff --git a/src/mainboard/google/guybrush/variants/guybrush/spd/Makefile.inc b/src/mainboard/google/guybrush/variants/guybrush/spd/Makefile.inc new file mode 100644 index 0000000..6508c26 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/guybrush/spd/Makefile.inc @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = H5AN8G6NCJR-VKC +SPD_SOURCES += ddr4-spd-6.hex # ID = 1(0b0001) Parts = H5ANAG6NCMR-VKC diff --git a/src/mainboard/google/guybrush/variants/guybrush/spd/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/guybrush/spd/dram_id.generated.txt new file mode 100644 index 0000000..20232a3 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/guybrush/spd/dram_id.generated.txt @@ -0,0 +1,3 @@ +DRAM Part Name ID to assign +H5AN8G6NCJR-VKC 0 (0000) +H5ANAG6NCMR-VKC 1 (0001) diff --git a/src/mainboard/google/guybrush/variants/guybrush/spd/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/guybrush/spd/mem_parts_used.txt new file mode 100644 index 0000000..7316ee0 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/guybrush/spd/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) +H5AN8G6NCJR-VKC, 0 +H5ANAG6NCMR-VKC, 1 diff --git a/src/mainboard/google/guybrush/verstage.c b/src/mainboard/google/guybrush/verstage.c new file mode 100644 index 0000000..bcbf396 --- /dev/null +++ b/src/mainboard/google/guybrush/verstage.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <amdblocks/gpio_banks.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <security/vboot/vboot_common.h> +#include <soc/southbridge.h> + +static void setup_gpio(void) +{ + const struct soc_amd_gpio *gpios; + size_t num_gpios; + + printk(BIOS_DEBUG, "Setting GPIOs\n"); + gpios = variant_early_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); + printk(BIOS_DEBUG, "GPIOs setup\n"); +} + +static void setup_i2c(void) +{ + printk(BIOS_DEBUG, "Setting up i2c\n"); + i2c_soc_early_init(); + printk(BIOS_DEBUG, "i2c setup\n"); +} + +void verstage_mainboard_early_init(void) +{ + setup_gpio(); +} + +void verstage_mainboard_init(void) +{ + enable_aoac_devices(); + setup_i2c(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1792f21ff7616f364ddc8b0c04481049b2a5fb04 Gerrit-Change-Number: 48479 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit December 2020