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Change in coreboot[master]: azalia: Make `find_verb` function non-static
by Angel Pons (Code Review) 17 Dec '20

17 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48348 ) Change subject: azalia: Make `find_verb` function non-static ...................................................................... azalia: Make `find_verb` function non-static Rename it to `azalia_find_verb` as the function is now globally visible. Change-Id: Ie66323b2c62139e86d3d7e003f6653a3def7b5f2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/azalia_device.c M src/include/device/azalia_device.h M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c M src/southbridge/intel/ibexpeak/azalia.c 7 files changed, 8 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/48348/1 diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index e12ffad..20e7d2b 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -85,7 +85,7 @@ return 0; } -static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) +u32 azalia_find_verb(struct device *dev, u32 viddid, const u32 **verb) { int idx = 0; @@ -179,7 +179,7 @@ /* 2 */ reg32 = read32(base + HDA_IR_REG); printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32); - verb_size = find_verb(dev, reg32, &verb); + verb_size = azalia_find_verb(dev, reg32, &verb); if (!verb_size) { printk(BIOS_DEBUG, "azalia_audio: No verb!\n"); diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 7bb8e10..7b5f5d6 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -19,6 +19,7 @@ #define HDA_ICII_VALID (1 << 1) int azalia_set_bits(void *port, u32 mask, u32 val); +u32 azalia_find_verb(struct device *dev, u32 viddid, const u32 **verb); void azalia_audio_init(struct device *dev); extern struct device_operations default_azalia_audio_ops; diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 5e810c4..1925a6f 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -41,24 +41,6 @@ return 0; } -static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) -{ - int idx = 0; - - while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 - if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header - continue; - } - *verb = &cim_verb_data[idx + 3]; - return verb_size; - } - - /* Not all codecs need to load another verb */ - return 0; -} - /* * Wait 50usec for the codec to indicate it is ready. * No response would imply that the codec is non-operative. @@ -131,7 +113,7 @@ /* 2 */ reg32 = read32(base + HDA_IR_REG); printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); - verb_size = find_verb(dev, reg32, &verb); + verb_size = azalia_find_verb(dev, reg32, &verb); if (!verb_size) { printk(BIOS_DEBUG, "Azalia: No verb!\n"); diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index a511468..fa3e9b4 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -39,24 +39,6 @@ return 0; } -static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) -{ - int idx = 0; - - while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 - if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header - continue; - } - *verb = &cim_verb_data[idx + 3]; - return verb_size; - } - - /* Not all codecs need to load another verb */ - return 0; -} - /* * Wait 50usec for the codec to indicate it is ready. * No response would imply that the codec is non-operative. @@ -129,7 +111,7 @@ /* 2 */ reg32 = read32(base + HDA_IR_REG); printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); - verb_size = find_verb(dev, reg32, &verb); + verb_size = azalia_find_verb(dev, reg32, &verb); if (!verb_size) { printk(BIOS_DEBUG, "Azalia: No verb!\n"); diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index 7078e67..9752285 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -39,24 +39,6 @@ return 0; } -static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) -{ - int idx = 0; - - while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 - if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header - continue; - } - *verb = &cim_verb_data[idx + 3]; - return verb_size; - } - - /* Not all codecs need to load another verb */ - return 0; -} - /* * Wait 50usec for the codec to indicate it is ready. * No response would imply that the codec is non-operative. @@ -129,7 +111,7 @@ /* 2 */ reg32 = read32(base + HDA_IR_REG); printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); - verb_size = find_verb(dev, reg32, &verb); + verb_size = azalia_find_verb(dev, reg32, &verb); if (!verb_size) { printk(BIOS_DEBUG, "Azalia: No verb!\n"); diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index 982efb7..81768bb 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -39,24 +39,6 @@ return 0; } -static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) -{ - int idx = 0; - - while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 - if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header - continue; - } - *verb = &cim_verb_data[idx + 3]; - return verb_size; - } - - /* Not all codecs need to load another verb */ - return 0; -} - /* * Wait 50usec for the codec to indicate it is ready. * No response would imply that the codec is non-operative. @@ -129,7 +111,7 @@ /* 2 */ reg32 = read32(base + HDA_IR_REG); printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); - verb_size = find_verb(dev, reg32, &verb); + verb_size = azalia_find_verb(dev, reg32, &verb); if (!verb_size) { printk(BIOS_DEBUG, "Azalia: No verb!\n"); diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 0c19598..af4f8ff 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -37,24 +37,6 @@ return 0; } -static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) -{ - int idx = 0; - - while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 - if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header - continue; - } - *verb = &cim_verb_data[idx + 3]; - return verb_size; - } - - /* Not all codecs need to load another verb */ - return 0; -} - /* * Wait 50usec for the codec to indicate it is ready. * No response would imply that the codec is non-operative. @@ -127,7 +109,7 @@ /* 2 */ reg32 = read32(base + HDA_IR_REG); printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); - verb_size = find_verb(dev, reg32, &verb); + verb_size = azalia_find_verb(dev, reg32, &verb); if (!verb_size) { printk(BIOS_DEBUG, "Azalia: No verb!\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/48348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie66323b2c62139e86d3d7e003f6653a3def7b5f2 Gerrit-Change-Number: 48348 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: device/azalia_device.c: Remove debug prints
by Angel Pons (Code Review) 17 Dec '20

17 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48347 ) Change subject: device/azalia_device.c: Remove debug prints ...................................................................... device/azalia_device.c: Remove debug prints The other six copies of this function in the tree do not have these debug prints. Remove them from here for consistency. Change-Id: I999032af1628bf8d66a057dc72368f02ef6eb8d1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/azalia_device.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/48347/1 diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 543d5cb..e12ffad 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -87,9 +87,6 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) { - printk(BIOS_DEBUG, "azalia_audio: dev=%s\n", dev_path(dev)); - printk(BIOS_DEBUG, "azalia_audio: Reading viddid=%x\n", viddid); - int idx = 0; while (idx < (cim_verb_data_size / sizeof(u32))) { -- To view, visit https://review.coreboot.org/c/coreboot/+/48347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I999032af1628bf8d66a057dc72368f02ef6eb8d1 Gerrit-Change-Number: 48347 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: azalia: Make `set_bits` function non-static
by Angel Pons (Code Review) 17 Dec '20

17 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48346 ) Change subject: azalia: Make `set_bits` function non-static ...................................................................... azalia: Make `set_bits` function non-static Rename it to `azalia_set_bits` as the function is now globally visible. Also select AZALIA_PLUGIN_SUPPORT since azalia_device.c depends on it. Change-Id: Iff3520131ec7bc8554612969e3a2fe9cdbc9305e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/azalia_device.c M src/include/device/azalia_device.h M src/soc/intel/common/Kconfig.common M src/soc/intel/common/hda_verb.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/azalia.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/hda_verb.c 16 files changed, 32 insertions(+), 213 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/48346/1 diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index 4ab45bc..543d5cb 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -7,7 +7,7 @@ #include <device/mmio.h> #include <delay.h> -static int set_bits(void *port, u32 mask, u32 val) +int azalia_set_bits(void *port, u32 mask, u32 val) { u32 reg32; int count; @@ -40,7 +40,7 @@ int count; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* clear STATESTS bits (BAR + 0xe)[2:0] */ @@ -62,11 +62,11 @@ goto no_codec; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, 1, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -80,7 +80,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, 1, 0); + azalia_set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "azalia_audio: No codec!\n"); return 0; } diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index d682772..7bb8e10 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -18,6 +18,7 @@ #define HDA_ICII_BUSY (1 << 0) #define HDA_ICII_VALID (1 << 1) +int azalia_set_bits(void *port, u32 mask, u32 val); void azalia_audio_init(struct device *dev); extern struct device_operations default_azalia_audio_ops; diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common index ba0b2db..1a59d04 100644 --- a/src/soc/intel/common/Kconfig.common +++ b/src/soc/intel/common/Kconfig.common @@ -1,5 +1,6 @@ config SOC_INTEL_COMMON bool + select AZALIA_PLUGIN_SUPPORT select HAVE_DISPLAY_MTRRS help common code for Intel SOCs diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index 83bbb59..57104c4 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -7,39 +7,12 @@ #include "hda_verb.h" -static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to match what was just written to it */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - int hda_codec_detect(u8 *base) { u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Write back the value once reset bit is set. */ @@ -51,11 +24,11 @@ write8(base + HDA_STATESTS_REG, 0xf); /* Turn off the link and poll RESET# bit until it reads back as 0 */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, ~HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, ~HDA_GCTL_CRST) < 0) goto no_codec; /* Turn on the link and poll RESET# bit until it reads back as 1 */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0]*/ @@ -69,7 +42,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0); + azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0); printk(BIOS_DEBUG, "HDA: No codec!\n"); return 0; } diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 7852ace..3b05a3e 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -11,6 +11,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select AZALIA_PLUGIN_SUPPORT select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 972b253..5e810c4 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -14,39 +14,12 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to match what was just written to it */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - static int codec_detect(u8 *base) { u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Write back the value once reset bit is set. */ @@ -63,7 +36,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, 1, 0); + azalia_set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 50f7c60..2d3bf24 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801GX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select AZALIA_PLUGIN_SUPPORT select IOAPIC select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 1927adc..a511468 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -11,43 +11,16 @@ #include "chip.h" #include "i82801gx.h" -static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to match what was just written to it */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - static int codec_detect(u8 *base) { u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -61,7 +34,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, 1, 0); + azalia_set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 11a6d39..be640db 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select AZALIA_PLUGIN_SUPPORT select HAVE_SMI_HANDLER if !NO_SMM select HAVE_USBDEBUG_OPTIONS select INTEL_DESCRIPTOR_MODE_CAPABLE diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index d6c7533..7078e67 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -11,43 +11,16 @@ #include "chip.h" #include "i82801ix.h" -static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to match what was just written to it */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - static int codec_detect(u8 *base) { u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -61,7 +34,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, 1, 0); + azalia_set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 6abeac1..687cb45 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -3,6 +3,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select AZALIA_PLUGIN_SUPPORT select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index bf41490..982efb7 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -11,43 +11,16 @@ #include "chip.h" #include "i82801jx.h" -static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to match what was just written to it */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - static int codec_detect(u8 *base) { u32 reg32; /* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0) < 0) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0] */ @@ -61,7 +34,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, 1, 0); + azalia_set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 07f9b6b..c54c7e4 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -8,6 +8,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select AZALIA_PLUGIN_SUPPORT select IOAPIC select HAVE_SMI_HANDLER select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 97e705e2..0c19598 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -10,39 +10,12 @@ #include <device/azalia_device.h> #include "pch.h" -static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to match what was just written to it */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - static int codec_detect(u8 *base) { u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Write back the value once reset bit is set. */ @@ -59,7 +32,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, 1, 0); + azalia_set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 7ba86b8..a88a9a8 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -8,6 +8,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select AZALIA_PLUGIN_SUPPORT select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index 24897ca..7c6537d 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -8,39 +8,12 @@ #include "pch.h" #include "hda_verb.h" -static int set_bits(void *port, u32 mask, u32 val) -{ - u32 reg32; - int count; - - /* Write (val & mask) to port */ - val &= mask; - reg32 = read32(port); - reg32 &= ~mask; - reg32 |= val; - write32(port, reg32); - - /* Wait for readback of register to match what was just written to it */ - count = 50; - do { - /* Wait 1ms based on BKDG wait time */ - mdelay(1); - reg32 = read32(port); - reg32 &= mask; - } while ((reg32 != val) && --count); - - /* Timeout occurred */ - if (!count) - return -1; - return 0; -} - int hda_codec_detect(u8 *base) { u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) + if (azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0) goto no_codec; /* Write back the value once reset bit is set. */ @@ -57,7 +30,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0); + azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0); printk(BIOS_DEBUG, "HDA: No codec!\n"); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/48346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff3520131ec7bc8554612969e3a2fe9cdbc9305e Gerrit-Change-Number: 48346 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/coffeelake_rvp/var/cfl_u: Add empty verb table
by Angel Pons (Code Review) 17 Dec '20

17 Dec '20

Hello Felix Singer, Nico Huber, Arthur Heymans, Michael Niewöhner, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48360 to review the following change. Change subject: mb/intel/coffeelake_rvp/var/cfl_u: Add empty verb table ...................................................................... mb/intel/coffeelake_rvp/var/cfl_u: Add empty verb table The code in soc/intel/common is rather messy, so there's no easy way to conditionally build a verb table with the changes that follow this one. Change-Id: I00d968563539a4e1b8d1e12145293439d8358555 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/intel/coffeelake_rvp/variants/cfl_u/hda_verb.h 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/48360/1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/hda_verb.h b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/hda_verb.h new file mode 100644 index 0000000..d4c6273 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_u/hda_verb.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* VerbTable: CFL Display Audio Codec */ + 0x8086280b, + 0xffffffff, + 0, +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00d968563539a4e1b8d1e12145293439d8358555 Gerrit-Change-Number: 48360 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 17

Change in coreboot[master]: amd_blobs: Add cezanne files
by Marshall Dawson (Code Review) 17 Dec '20

17 Dec '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48647 ) Change subject: amd_blobs: Add cezanne files ...................................................................... amd_blobs: Add cezanne files Add blobs from the 1.0.0.1 release of CezannePI-FP6. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Iebfbe819ed429a7aed1882964061e1bc98f3bc39 --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/48647/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index d0a9215..3e4a2e5 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit d0a92151d387b5296b6c5fbff4e4d66839c5c2dd +Subproject commit 3e4a2e530f6f6dab7e9dc4af3feff9bdb2073b18 -- To view, visit https://review.coreboot.org/c/coreboot/+/48647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebfbe819ed429a7aed1882964061e1bc98f3bc39 Gerrit-Change-Number: 48647 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: sb/amd/pi/hudson: Fixes for common GPIO API
by Kyösti Mälkki (Code Review) 17 Dec '20

17 Dec '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42733 to look at the new patch set (#11). Change subject: sb/amd/pi/hudson: Fixes for common GPIO API ...................................................................... sb/amd/pi/hudson: Fixes for common GPIO API Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Kconfig A src/southbridge/amd/pi/hudson/soc/gpio.h A src/southbridge/amd/pi/hudson/soc/smi.h M src/vendorcode/amd/pi/Makefile.inc 4 files changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/42733/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/42733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Gerrit-Change-Number: 42733 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/amd/common: Refactor single GPIO programming
by Kyösti Mälkki (Code Review) 17 Dec '20

17 Dec '20

Kyösti Mälkki has restored this change. ( https://review.coreboot.org/c/coreboot/+/42691 ) Change subject: soc/amd/common: Refactor single GPIO programming ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/42691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa6bd6996fd14dde4b1abcccbd2ae6ef933c87b Gerrit-Change-Number: 42691 Gerrit-PatchSet: 10 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: restore

1 0

Change in coreboot[master]: soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config
by Kyösti Mälkki (Code Review) 17 Dec '20

17 Dec '20

Kyösti Mälkki has restored this change. ( https://review.coreboot.org/c/coreboot/+/42685 ) Change subject: soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/42685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c8ce8de0a6ab0ed41e7e8a5980d0f0510aaa993 Gerrit-Change-Number: 42685 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: restore

1 0

Change in coreboot[master]: mb/supermicro/x11ssm-f: configure the BMC jumper JPB1
by Michał Żygowski (Code Review) 17 Dec '20

17 Dec '20

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48095 ) Change subject: mb/supermicro/x11ssm-f: configure the BMC jumper JPB1 ...................................................................... Patch Set 30: How about other X11 variants? -- To view, visit https://review.coreboot.org/c/coreboot/+/48095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8581556d915cbad2c743a79db273479ba55798fb Gerrit-Change-Number: 48095 Gerrit-PatchSet: 30 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 17 Dec 2020 11:41:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in em100[master]: trace: Use dynamic address bytes everywhere we should.
by Stefan Reinauer (Code Review) 17 Dec '20

17 Dec '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/48597 ) Change subject: trace: Use dynamic address bytes everywhere we should. ...................................................................... trace: Use dynamic address bytes everywhere we should. Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Change-Id: I0614bd39d0b47331ffb96195da3624240ef29ffa --- M trace.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/97/48597/1 diff --git a/trace.c b/trace.c index 22517f9..88265b5 100644 --- a/trace.c +++ b/trace.c @@ -201,6 +201,7 @@ } for (i = 0; i < count; i++) { unsigned int j = additional_pad_bytes; + unsigned int address_bytes = 0; additional_pad_bytes = 0; unsigned char cmd = data[2 + i*8]; @@ -246,7 +247,7 @@ j = 1; /* skip command byte */ } else { /* If address_mode > 1 -> always decode 4 bytes */ - int address_bytes = + address_bytes = (spi_cmd_vals->uses_address == 1) ? address_mode : 4; if (address_mode == 3) @@ -288,7 +289,7 @@ printf("\n : "); } } - printf("%02x ", data[i * 8 + 4 + j]); + printf("%02x ", data[i * 8 + address_bytes + 1 + j]); outbytes++; if (outbytes == 16) { outbytes = 0; -- To view, visit https://review.coreboot.org/c/em100/+/48597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I0614bd39d0b47331ffb96195da3624240ef29ffa Gerrit-Change-Number: 48597 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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