Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48654 )
Change subject: mb/ocp/tiagopass/devicetree.cb: Add P2SB device ......................................................................
mb/ocp/tiagopass/devicetree.cb: Add P2SB device
This fixes ocp/tiagopass not booting as after FSP-S the P2SB is accessed to read out or reconfigure the HPET and PCH IOAPIC DBF.
Change-Id: Ia37bd0f14627980345cd07f20e935a10d4760b69 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/ocp/tiogapass/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/48654/1
diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 008633b..488f677 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -77,6 +77,7 @@ register "bmc_boot_timeout" = "90" end end # Intel Corporation C621 Series Chipset LPC/eSPI Controller + device pci 1f.1 hidden end # p2sb device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48654 )
Change subject: mb/ocp/tiagopass/devicetree.cb: Add P2SB device ......................................................................
Patch Set 1: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/48654/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48654/1//COMMIT_MSG@9 PS1, Line 9: tiago tioga
https://review.coreboot.org/c/coreboot/+/48654/1//COMMIT_MSG@10 PS1, Line 10: DBF BDF
Marc Jones has uploaded a new patch set (#2) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/48654 )
Change subject: mb/ocp/tiogapass/devicetree.cb: Add P2SB device ......................................................................
mb/ocp/tiogapass/devicetree.cb: Add P2SB device
This fixes ocp/tiagopass not booting as after FSP-S the P2SB is accessed to read out or reconfigure the HPET and PCH IOAPIC BDF.
Change-Id: Ia37bd0f14627980345cd07f20e935a10d4760b69 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/ocp/tiogapass/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/48654/2
Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48654 )
Change subject: mb/ocp/tiogapass/devicetree.cb: Add P2SB device ......................................................................
Patch Set 2: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/48654/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48654/1//COMMIT_MSG@9 PS1, Line 9: tiago
tioga
Done
https://review.coreboot.org/c/coreboot/+/48654/1//COMMIT_MSG@10 PS1, Line 10: DBF
BDF
Done
Marc Jones has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48654 )
Change subject: mb/ocp/tiogapass/devicetree.cb: Add P2SB device ......................................................................
mb/ocp/tiogapass/devicetree.cb: Add P2SB device
This fixes ocp/tiagopass not booting as after FSP-S the P2SB is accessed to read out or reconfigure the HPET and PCH IOAPIC BDF.
Change-Id: Ia37bd0f14627980345cd07f20e935a10d4760b69 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/48654 Reviewed-by: Marc Jones marc@marcjonesconsulting.com Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/ocp/tiogapass/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 008633b..488f677 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -77,6 +77,7 @@ register "bmc_boot_timeout" = "90" end end # Intel Corporation C621 Series Chipset LPC/eSPI Controller + device pci 1f.1 hidden end # p2sb device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller
Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48654 )
Change subject: mb/ocp/tiogapass/devicetree.cb: Add P2SB device ......................................................................
Patch Set 3:
Can we - even on commits that do fix the master for boards again - keep the 24 hour rule? Or get additional +2's..
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48654 )
Change subject: mb/ocp/tiogapass/devicetree.cb: Add P2SB device ......................................................................
Patch Set 3:
(1 comment)
Patch Set 3:
Can we - even on commits that do fix the master for boards again - keep the 24 hour rule? Or get additional +2's..
I second that. For reference, here's the guidelines: https://doc.coreboot.org/getting_started/gerrit_guidelines.html
https://review.coreboot.org/c/coreboot/+/48654/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48654/1//COMMIT_MSG@9 PS1, Line 9: tiago
Done
That wasn't changed, but it's too late now
Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48654 )
Change subject: mb/ocp/tiogapass/devicetree.cb: Add P2SB device ......................................................................
Patch Set 3:
(1 comment)
Patch Set 3:
(1 comment)
Patch Set 3:
Can we - even on commits that do fix the master for boards again - keep the 24 hour rule? Or get additional +2's..
I second that. For reference, here's the guidelines: https://doc.coreboot.org/getting_started/gerrit_guidelines.html
Sorry, Thought 2 was enough. I'll leave them next time.
https://review.coreboot.org/c/coreboot/+/48654/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48654/1//COMMIT_MSG@9 PS1, Line 9: tiago
That wasn't changed, but it's too late now
ah darn, I changed the one above and missed this one.
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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Christian Walter (Code Review)
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Marc Jones (Code Review)