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Change in coreboot[master]: soc/mediatek/mt8192: return correct voltage of VM18
by hsin-hsiung wang (Code Review) 16 Dec '20

16 Dec '20

hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48110 ) Change subject: soc/mediatek/mt8192: return correct voltage of VM18 ...................................................................... soc/mediatek/mt8192: return correct voltage of VM18 The voltage of vm18 should be microvolt instead of millivolt. BUG=b:155253454 BRANCH=none TEST=boot asurada correctly Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: Iea5b46c1df358dc350506d29cc033d01631b37b0 --- M src/soc/mediatek/mt8192/mt6359p.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/48110/1 diff --git a/src/soc/mediatek/mt8192/mt6359p.c b/src/soc/mediatek/mt8192/mt6359p.c index 1646e53..0c34db3 100644 --- a/src/soc/mediatek/mt8192/mt6359p.c +++ b/src/soc/mediatek/mt8192/mt6359p.c @@ -417,7 +417,7 @@ reg_vol = 100 * mt6359p_read_field(PMIC_VM18_ANA_CON0, 0xF, VM18_VOL_REG_SHIFT); reg_cali = 10 * mt6359p_read_field(PMIC_VM18_ANA_CON0, 0xF, 0); - return 600 + reg_vol + reg_cali; + return 1000 * (600 + reg_vol + reg_cali); } static void init_pmif_arb(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/48110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea5b46c1df358dc350506d29cc033d01631b37b0 Gerrit-Change-Number: 48110 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: soc/mediatek/mt8192: Keep CONN MCU in reset state
by Yidi Lin (Code Review) 16 Dec '20

16 Dec '20

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46447 to review the following change. Change subject: soc/mediatek/mt8192: Keep CONN MCU in reset state ...................................................................... soc/mediatek/mt8192: Keep CONN MCU in reset state Keep the CONN MCU in reset state to prevent CONN from asserting the clk26m request to SPM. TEST=clk26m request from conn has been released. Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: Ia1b706da497ba2827341051459c3628e2ae9240f --- M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/46447/1 diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 35e8ff2..cafa1dd 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -306,6 +306,9 @@ DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) +DEFINE_BITFIELD(WDT_SWSYSRST_KEY, 31, 24) +DEFINE_BITFIELD(WDT_SWSYSRST_CONN_MCU, 12, 12) + enum { INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = ((0x1f << 12) | \ (0x1 << 17) | \ diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 0366cd6..fdd0b1e 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -10,6 +10,7 @@ #include <soc/infracfg.h> #include <soc/mcucfg.h> #include <soc/pll.h> +#include <soc/wdt.h> enum mux_id { TOP_AXI_SEL, @@ -460,6 +461,11 @@ /* enable [14] dramc_pll104m_ck */ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); + + /* reset CONNSYS MCU */ + SET32_BITFIELDS(&mtk_wdt->wdt_swsysrst, + WDT_SWSYSRST_KEY, 0x88, + WDT_SWSYSRST_CONN_MCU, 1); } void mt_pll_raise_little_cpu_freq(u32 freq) -- To view, visit https://review.coreboot.org/c/coreboot/+/46447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b706da497ba2827341051459c3628e2ae9240f Gerrit-Change-Number: 46447 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: mb/google/poppy: Fix race condition in acpi camera_pmic
by Ricardo Ribalda (Code Review) 16 Dec '20

16 Dec '20

Ricardo Ribalda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48631 ) Change subject: mb/google/poppy: Fix race condition in acpi camera_pmic ...................................................................... mb/google/poppy: Fix race condition in acpi camera_pmic Newer kernels can re-schedule new acpi command calls during a Sleep(). This causes that the following trace fails to detect the cameras: [ 15.764725] drivers/acpi/power.c:358 Power resource [OVFI] turned on start [ 15.772180] drivers/acpi/power.c:358 Power resource [OVTH] turned on start [ 15.834970] drivers/acpi/power.c:362 Power resource [OVFI] turned on start [ 15.852456] drivers/acpi/power.c:415 Power resource [OVFI] turned off start [ 15.955987] drivers/acpi/power.c:420 Power resource [OVFI] turned off end ERROR!! [ 16.030896] drivers/acpi/power.c:362 Power resource [OVTH] turned on end Which can be triggered more frequently if the Sleep() commands in OVTH _ON Method are increased. To avoid the race condition, we create a new Power Resource that handles the common resources of both cameras and make both cameras depend on that resource. This also simplifies the acpi table by removing a Mutex. BUG=c:171955583 TEST=while true; do if ssh $DUT "dmesg | grep \"failed to find sensor\" "; then break; fi; ssh $DUT reboot; sleep 30 ; done Signed-off-by: Ricardo Ribalda <ribalda(a)chromium.org> Change-Id: I25df0225699759c1828b8791c5bdee66529858a7 --- M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl 3 files changed, 78 insertions(+), 96 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/48631/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl index 8f3ae53..2d5dd0a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam0.asl @@ -23,8 +23,8 @@ ) }) - Name (_PR0, Package () { ^^I2C2.PMIC.OVTH }) - Name (_PR3, Package () { ^^I2C2.PMIC.OVTH }) + Name (_PR0, Package () {^^I2C2.PMIC.OVCM, ^^I2C2.PMIC.OVTH}) + Name (_PR3, Package () {^^I2C2.PMIC.OVCM, ^^I2C2.PMIC.OVTH}) /* Port0 of CAM0 is connected to port0 of CIO2 device */ Name (_DSD, Package () { diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl index 7e20575..c41ebca 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/cam1.asl @@ -23,8 +23,8 @@ ) }) - Name (_PR0, Package () { ^^I2C2.PMIC.OVFI }) - Name (_PR3, Package () { ^^I2C2.PMIC.OVFI }) + Name (_PR0, Package () {^^I2C2.PMIC.OVCM, ^^I2C2.PMIC.OVFI}) + Name (_PR3, Package () {^^I2C2.PMIC.OVCM, ^^I2C2.PMIC.OVFI}) /* Port0 of CAM1 is connected to port1 of CIO2 device */ Name (_DSD, Package () { diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 5ad10ef..3ce5555 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -313,76 +313,50 @@ PODV, 32, } - /* CLE0 and CLE1 are used to determine if both the clocks - are enabled or disabled. */ - Mutex (MUTC, 0) - Name (CLE0, 0) - Name (CLE1, 0) - Method (CLKE, 0, Serialized) { - /* save Acquire result so we can check for - Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) - /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { - /* Enable clocks only when a sensor is turned on and - both the clocks are disabled */ - If (LNot (LOr (CLE0, CLE1))) { - /* Set boost clock divider */ - BODI = 3 - /* Set buck clock divider */ - BUDI = 2 - /* Set the PLL_REF_CLK cyles */ - PSWR = 19 - /* Set the reference crystal divider */ - XTDV = 170 - /* Set PLL feedback divider */ - PLDV = 32 - /* Set PLL output divider for HCLK_A */ - PODV = 1 - /* Set PLL output divider for HCLK_B */ - PDV2 = 1 - /* Enable clocks for both the sensors - * CFG1: output selection for HCLK_A and - * HCLK_B. - * CFG2: set drive strength for HCLK_A - * and HCLK_B. - */ - CFG2 = 5 - CFG1 = 10 - /* Enable PLL output, crystal oscillator - * input capacitance control and set - * Xtal oscillator as clock source. - */ - PCTL = 209 - Sleep(1) - } - Release (MUTC) - } - } - - /* Clocks need to be disabled only if both the sensors are - turned off */ - Method (CLKD, 0, Serialized) { - /* save Acquire result so we can check for - Mutex acquired */ - Store (Acquire (MUTC, 1000), Local0) - /* check for Mutex acquired */ - If (LEqual (Local0, Zero)) { - If (LNot (LOr (CLE0, CLE1))) { - BODI = 0 - BUDI = 0 - PSWR = 0 - XTDV = 0 - PLDV = 0 - PODV = 0 - PDV2 = 0 - /* Disable clocks for both the - sensors */ - CFG2 = 0 - CFG1 = 0 - PCTL = 0 - } - Release (MUTC) + Method (CLK, 1, Serialized) { + If (LEqual (Arg0, Zero)) { + BODI = 0 + BUDI = 0 + PSWR = 0 + XTDV = 0 + PLDV = 0 + PODV = 0 + PDV2 = 0 + /* Disable clocks for both the + sensors */ + CFG2 = 0 + CFG1 = 0 + PCTL = 0 + Sleep(1) + } ElseIf (LEqual (Arg0, 1)) { + /* Set boost clock divider */ + BODI = 3 + /* Set buck clock divider */ + BUDI = 2 + /* Set the PLL_REF_CLK cyles */ + PSWR = 19 + /* Set the reference crystal divider */ + XTDV = 170 + /* Set PLL feedback divider */ + PLDV = 32 + /* Set PLL output divider for HCLK_A */ + PODV = 1 + /* Set PLL output divider for HCLK_B */ + PDV2 = 1 + /* Enable clocks for both the sensors + * CFG1: output selection for HCLK_A and + * HCLK_B. + * CFG2: set drive strength for HCLK_A + * and HCLK_B. + */ + CFG2 = 5 + CFG1 = 10 + /* Enable PLL output, crystal oscillator + * input capacitance control and set + * Xtal oscillator as clock source. + */ + PCTL = 209 + Sleep(1) } } @@ -425,6 +399,36 @@ } } + /* Power resource methods for both CAMs */ + PowerResource (OVCM, 0, 0) { + Name (STA, 0) + Method (_ON, 0, Serialized) { + If (LEqual (AVBL, 1)) { + If (LEqual (STA, 0)) { + /* Enable VSIO regulator + + daisy chain */ + DOVD(1) + + CLK(1) + STA = 1 + } + } + } + Method (_OFF, 0, Serialized) { + If (LEqual (AVBL, 1)) { + If (LEqual (STA, 1)) { + CLK(0) + Sleep(2) + DOVD(0) + } + } + STA = 0 + } + Method (_STA, 0, NotSerialized) { + Return (STA) + } + } + /* Power resource methods for CAM0 */ PowerResource (OVTH, 0, 0) { Name (STA, 0) @@ -432,10 +436,6 @@ /* TODO: Read Voltage and Sleep values from Sensor Obj */ If (LEqual (AVBL, 1)) { If (LEqual (STA, 0)) { - /* Enable VSIO regulator + - daisy chain */ - DOVD(1) - \_SB.PCI0.I2C2.PMIC.CGP1() \_SB.PCI0.I2C2.PMIC.CGP2() @@ -447,9 +447,6 @@ DCVA = 12 VDCT = 1 - \_SB.PCI0.I2C2.PMIC.CLKE() - CLE0 = 1 - /* * Wait for all regulator * outputs to settle. @@ -473,16 +470,12 @@ If (LEqual (AVBL, 1)) { If (LEqual (STA, 1)) { Sleep(2) - CLE0 = 0 - \_SB.PCI0.I2C2.PMIC.CLKD() - Sleep(2) \_SB.PCI0.I2C2.PMIC.CRST(0) Sleep(3) VDCT = 0 Sleep(3) VACT = 0 Sleep(1) - DOVD(0) } } STA = 0 @@ -499,10 +492,6 @@ /* TODO: Read Voltage and Sleep values from Sensor Obj */ If (LEqual (AVBL, 1)) { If (LEqual (STA, 0)) { - /* Enable VSIO regulator + - daisy chain */ - DOVD(1) - /* Set VAUX2 as 1.8006 V */ AX2V = 52 VAX2 = 1 /* Enable VAUX2 */ @@ -522,9 +511,6 @@ /* Wait for VDD to settle. */ Sleep(1) - \_SB.PCI0.I2C2.PMIC.CLKE() - CLE1 = 1 - \_SB.PCI0.I2C2.PMIC.CGP5(1) /* * Ensure 10 ms between @@ -540,9 +526,6 @@ If (LEqual (AVBL, 1)) { If (LEqual (STA, 1)) { Sleep(2) - CLE1 = 0 - \_SB.PCI0.I2C2.PMIC.CLKD() - Sleep(2) \_SB.PCI0.I2C2.PMIC.CGP5(0) Sleep(3) VAX1 = 0 @@ -551,7 +534,6 @@ Sleep(1) VAX2 = 0 Sleep(1) - DOVD(0) } STA = 0 } -- To view, visit https://review.coreboot.org/c/coreboot/+/48631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25df0225699759c1828b8791c5bdee66529858a7 Gerrit-Change-Number: 48631 Gerrit-PatchSet: 1 Gerrit-Owner: Ricardo Ribalda <ribalda(a)chromium.org> Gerrit-MessageType: newchange

3 16

Change in coreboot[master]: mb/google/zork/: Remove WRDD from Vilboz
by EricR Lai (Code Review) 16 Dec '20

16 Dec '20

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48621 ) Change subject: mb/google/zork/: Remove WRDD from Vilboz ...................................................................... mb/google/zork/: Remove WRDD from Vilboz After checked, this project doesn't need this feature. BUG=b:173066178 BRANCH=zork TEST=check no WRDD method in acpi. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I9a662953f3047d771f2df919ac80d0440842738e --- A src/mainboard/google/brya/spd/Makefile.inc A src/mainboard/google/brya/spd/dram_id.generated.txt A src/mainboard/google/brya/spd/mem_list_variant.txt M src/mainboard/google/zork/Kconfig A src/soc/intel/alderlake/spd/lp4x-spd-1.hex A src/soc/intel/alderlake/spd/lp4x-spd-2.hex A src/soc/intel/alderlake/spd/lp4x-spd-3.hex A src/soc/intel/alderlake/spd/lp4x-spd-4.hex A src/soc/intel/alderlake/spd/lp4x-spd-5.hex A src/soc/intel/alderlake/spd/lp4x-spd-6.hex A src/soc/intel/alderlake/spd/lp4x-spd-7.hex A src/soc/intel/alderlake/spd/lp4x-spd-8.hex A src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt M util/spd_tools/lp4x/gen_spd.go 14 files changed, 296 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/48621/1 diff --git a/src/mainboard/google/brya/spd/Makefile.inc b/src/mainboard/google/brya/spd/Makefile.inc new file mode 100644 index 0000000..37e4c22 --- /dev/null +++ b/src/mainboard/google/brya/spd/Makefile.inc @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AA-MGCL +SPD_SOURCES += lp4x-spd-4.hex # ID = 2(0b0010) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE diff --git a/src/mainboard/google/brya/spd/dram_id.generated.txt b/src/mainboard/google/brya/spd/dram_id.generated.txt new file mode 100644 index 0000000..637fd23 --- /dev/null +++ b/src/mainboard/google/brya/spd/dram_id.generated.txt @@ -0,0 +1,6 @@ +DRAM Part Name ID to assign +K4U6E3S4AA-MGCL 0 (0000) +K4UBE3D4AA-MGCL 1 (0001) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 2 (0010) +H9HCNNNFAMMLXR-NEE 3 (0011) diff --git a/src/mainboard/google/brya/spd/mem_list_variant.txt b/src/mainboard/google/brya/spd/mem_list_variant.txt new file mode 100644 index 0000000..c532d0d --- /dev/null +++ b/src/mainboard/google/brya/spd/mem_list_variant.txt @@ -0,0 +1,5 @@ +K4U6E3S4AA-MGCL +K4UBE3D4AA-MGCL +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +H9HCNNNFAMMLXR-NEE diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index c1cbae9..88d6e97 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -267,6 +267,5 @@ select SAR_ENABLE select USE_SAR select GEO_SAR_ENABLE - select HAVE_REGULATORY_DOMAIN if BOARD_GOOGLE_VILBOZ endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/soc/intel/alderlake/spd/lp4x-spd-1.hex b/src/soc/intel/alderlake/spd/lp4x-spd-1.hex new file mode 100644 index 0000000..50f50e2 --- /dev/null +++ b/src/soc/intel/alderlake/spd/lp4x-spd-1.hex @@ -0,0 +1,32 @@ +23 11 11 0E 16 21 04 08 00 00 00 00 02 22 00 00 +00 00 04 FF 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 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00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/alderlake/spd/lp4x-spd-2.hex b/src/soc/intel/alderlake/spd/lp4x-spd-2.hex new file mode 100644 index 0000000..866b466 --- /dev/null +++ b/src/soc/intel/alderlake/spd/lp4x-spd-2.hex @@ -0,0 +1,32 @@ +23 11 11 0E 17 29 98 08 00 00 00 00 09 22 00 00 +00 00 04 FF 12 29 15 00 96 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E2 00 E0 00 00 +00 00 00 00 00 00 00 00 00 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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/alderlake/spd/lp4x-spd-3.hex b/src/soc/intel/alderlake/spd/lp4x-spd-3.hex new file mode 100644 index 0000000..6db2d80 --- /dev/null +++ b/src/soc/intel/alderlake/spd/lp4x-spd-3.hex @@ -0,0 +1,32 @@ +23 11 11 0E 16 21 94 08 00 00 00 00 0A 22 00 00 +00 00 04 FF 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 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b/src/soc/intel/alderlake/spd/lp4x-spd-4.hex new file mode 100644 index 0000000..c4180b6 --- /dev/null +++ b/src/soc/intel/alderlake/spd/lp4x-spd-4.hex @@ -0,0 +1,32 @@ +23 11 11 0E 17 29 04 08 00 00 00 00 02 22 00 00 +00 00 04 FF 92 54 05 00 87 00 90 A8 90 E0 0B F0 +05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/alderlake/spd/lp4x-spd-5.hex b/src/soc/intel/alderlake/spd/lp4x-spd-5.hex new file mode 100644 index 0000000..77230e7 --- /dev/null +++ b/src/soc/intel/alderlake/spd/lp4x-spd-5.hex @@ -0,0 +1,32 @@ +23 11 11 0E 16 21 94 08 00 00 00 00 02 22 00 00 +00 00 04 FF 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/alderlake/spd/lp4x-spd-6.hex b/src/soc/intel/alderlake/spd/lp4x-spd-6.hex new file mode 100644 index 0000000..8da34f1 --- /dev/null +++ b/src/soc/intel/alderlake/spd/lp4x-spd-6.hex @@ -0,0 +1,32 @@ +23 11 11 0E 17 29 94 08 00 00 00 00 02 22 00 00 +00 00 04 FF 92 54 05 00 87 00 90 A8 90 E0 0B F0 +05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/alderlake/spd/lp4x-spd-7.hex b/src/soc/intel/alderlake/spd/lp4x-spd-7.hex new file mode 100644 index 0000000..2fe6757 --- /dev/null +++ b/src/soc/intel/alderlake/spd/lp4x-spd-7.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 19 04 08 00 00 00 00 02 22 00 00 +00 00 05 0A 80 54 01 00 89 00 90 A8 90 A0 05 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 FB 00 A6 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/alderlake/spd/lp4x-spd-8.hex b/src/soc/intel/alderlake/spd/lp4x-spd-8.hex new file mode 100644 index 0000000..1fe256a --- /dev/null +++ b/src/soc/intel/alderlake/spd/lp4x-spd-8.hex @@ -0,0 +1,32 @@ +23 11 11 0E 16 21 B4 08 00 00 00 00 0A 22 00 00 +00 00 04 FF 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 E5 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt b/src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt new file mode 100644 index 0000000..2b44d5b --- /dev/null +++ b/src/soc/intel/alderlake/spd/lp4x_spd_manifest.generated.txt @@ -0,0 +1,19 @@ +H9HCNNNBKMMLXR-NEE,lp4x-spd-1.hex +H9HCNNNFAMMLXR-NEE,lp4x-spd-2.hex +K4U6E3S4AA-MGCL,lp4x-spd-1.hex +K4UBE3D4AA-MGCL,lp4x-spd-3.hex +MT53E1G32D2NP-046 WT:A,lp4x-spd-4.hex +H9HKNNNCRMBVAR-NEH,lp4x-spd-5.hex +MT53E1G64D4SQ-046 WT:A,lp4x-spd-6.hex +MT53E512M32D2NP-046 WT:F,lp4x-spd-1.hex +NT6AP256T32AV-J2,lp4x-spd-7.hex +K4U6E3S4AA-MGCR,lp4x-spd-1.hex +MT53E512M32D2NP-046 WT:E,lp4x-spd-1.hex +H9HCNNNCPMMLXR-NEE,lp4x-spd-3.hex +K4UBE3D4AA-MGCR,lp4x-spd-3.hex +MT53E512M64D4NW-046 WT:E,lp4x-spd-5.hex +MT53E1G64D8NW-046 WT:E,lp4x-spd-8.hex +H9HCNNNCRMBLPR-NEE,lp4x-spd-5.hex +H9HCNNNFBMBLPR-NEE,lp4x-spd-8.hex +MT53D1G64D4NW-046 WT:A,lp4x-spd-6.hex +MT53D512M64D4NW-046 WT:F,lp4x-spd-5.hex diff --git a/util/spd_tools/lp4x/gen_spd.go b/util/spd_tools/lp4x/gen_spd.go index e63ca8d..94cfb8d 100644 --- a/util/spd_tools/lp4x/gen_spd.go +++ b/util/spd_tools/lp4x/gen_spd.go @@ -29,11 +29,13 @@ PlatformTGL = 0 PlatformJSL = 1 + PlatformADL = 0 ) var platformMap = map[string]int { "TGL": PlatformTGL, "JSL": PlatformJSL, + "ADL": PlatformADL, } var currPlatform int -- To view, visit https://review.coreboot.org/c/coreboot/+/48621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a662953f3047d771f2df919ac80d0440842738e Gerrit-Change-Number: 48621 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/purism/librem_cnl: Use FMAP-based SPD cache
by Matt DeVillier (Code Review) 16 Dec '20

16 Dec '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48549 ) Change subject: mb/purism/librem_cnl: Use FMAP-based SPD cache ...................................................................... mb/purism/librem_cnl: Use FMAP-based SPD cache Use a FMAP region to cache SPD data, providing improvements in boot time and detection of change in DIMM population (whcih FSP will sometimes fail to detect / fail to invalidate the MRC cache). Adapted from implemention used in google/hatch. Test: build/boot Librem Mini v2, verify SPD cache used, changes in DIMM population properly detected. Change-Id: I15cb9aa8b00d39d098a0f901aee026bac1161a80 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/Kconfig M src/mainboard/purism/librem_cnl/romstage.c 2 files changed, 93 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/48549/1 diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig index 1d31ec6..d0282ad 100644 --- a/src/mainboard/purism/librem_cnl/Kconfig +++ b/src/mainboard/purism/librem_cnl/Kconfig @@ -8,6 +8,7 @@ select INTEL_GMA_HAVE_VBT select NO_UART_ON_SUPERIO select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPD_CACHE_IN_FMAP select SPD_READ_BY_WORD select USE_LEGACY_8254_TIMER diff --git a/src/mainboard/purism/librem_cnl/romstage.c b/src/mainboard/purism/librem_cnl/romstage.c index b7c57ee..44d8ad0 100644 --- a/src/mainboard/purism/librem_cnl/romstage.c +++ b/src/mainboard/purism/librem_cnl/romstage.c @@ -1,55 +1,104 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <spd_bin.h> +#include <spd_cache.h> #include "variant.h" -static const struct cnl_mb_cfg memcfg = { - - /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ - .spd[0] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa0}, - }, - .spd[1] = {.read_type = NOT_EXISTING}, - .spd[2] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa4}, - }, - .spd[3] = {.read_type = NOT_EXISTING}, - - /* - * Rcomp resistor values. These values represent the resistance in - * ohms of the three rcomp resistors attached to the DDR_COMP_0, - * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. - */ - .rcomp_resistor = { 121, 81, 100 }, - - /* Rcomp target values */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, - - /* - * Indicates whether memory is interleaved. - * Set to 1 for an interleaved design, - * set to 0 for non-interleaved design. - */ - .dq_pins_interleaved = 1, - - /* - * VREF_CA configuration. - * Set to 0 VREF_CA goes to both CH_A and CH_B, - * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, - * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. - */ - .vref_ca_config = 2, - - /* Early Command Training */ - .ect = 0, -}; - void mainboard_memory_init_params(FSPM_UPD *memupd) { FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + + struct cnl_mb_cfg memcfg = { + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + .rcomp_resistor = { 121, 81, 100 }, + + /* Rcomp target values */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + .dq_pins_interleaved = 1, + + /* + * VREF_CA configuration. + * Set to 0 VREF_CA goes to both CH_A and CH_B, + * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, + * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + */ + .vref_ca_config = 2, + + /* Early Command Training */ + .ect = 0, + }; + + + /* Read spd block to get memory config */ + struct spd_block blk = { + .addr_map = { 0x50, 0x52, }, + }; + + uint8_t *spd_cache; + size_t spd_cache_sz; + bool need_update_cache = false; + bool dimm_changed = true; + + /* load spd cache from RW_SPD_CACHE */ + if (load_spd_cache(&spd_cache, &spd_cache_sz) == CB_SUCCESS) { + if (!spd_cache_is_valid(spd_cache, spd_cache_sz)) { + printk(BIOS_WARNING, "Invalid SPD cache\n"); + } else { + dimm_changed = check_if_dimm_changed(spd_cache, &blk); + if (dimm_changed && memupd->FspmArchUpd.NvsBufferPtr != NULL) { + /* Set mrc_cache as invalid */ + printk(BIOS_INFO, "Set mrc_cache as invalid\n"); + memupd->FspmArchUpd.NvsBufferPtr = NULL; + } + } + need_update_cache = true; + } + + if (!dimm_changed) { + spd_fill_from_cache(spd_cache, &blk); + } else { + /* Access memory info through SMBUS. */ + get_spd_smbus(&blk); + + if (need_update_cache && update_spd_cache(&blk) == CB_ERR) + printk(BIOS_WARNING, "update SPD cache failed\n"); + } + + if (blk.spd_array[0] == NULL) { + memcfg.spd[0].read_type = NOT_EXISTING; + } else { + memcfg.spd[0].read_type = READ_SPD_MEMPTR; + memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; + memcfg.spd[0].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[0]; + } + + memcfg.spd[1].read_type = NOT_EXISTING; + + if (blk.spd_array[1] == NULL) { + memcfg.spd[2].read_type = NOT_EXISTING; + } else { + memcfg.spd[2].read_type = READ_SPD_MEMPTR; + memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_len = blk.len; + memcfg.spd[2].spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)blk.spd_array[1]; + } + + memcfg.spd[3].read_type = NOT_EXISTING; + dump_spd_info(&blk); + cannonlake_memcfg_init(mem_cfg, &memcfg); variant_memory_init_params(mem_cfg); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15cb9aa8b00d39d098a0f901aee026bac1161a80 Gerrit-Change-Number: 48549 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc init settings
by CK HU (Code Review) 16 Dec '20

16 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44700 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc init settings ...................................................................... soc/mediatek/mt8192: Do dramc init settings Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ie4877b69de1bfa4ff981d8eb386efbddb9e0f5c2 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_basic_api.c A src/soc/mediatek/mt8192/dramc_pi_main.c A src/soc/mediatek/mt8192/dramc_utility.c M src/soc/mediatek/mt8192/emi.c 5 files changed, 242 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/44700/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index dd80beb..e82f182 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -16,6 +16,7 @@ verstage-y += ../common/uart.c romstage-y += ../common/cbmem.c +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_utility.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c new file mode 100644 index 0000000..9b1216c --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <string.h> +#include <timer.h> + +void global_option_init(struct ddr_cali *cali) +{ +} + +void dfs_init_for_calibration(const struct ddr_cali *cali) +{ +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c new file mode 100644 index 0000000..e2c7500 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <soc/mt6359p.h> + +static void set_vcore_voltage_for_each_freq(const struct ddr_cali *cali) +{ + u32 vcore = get_vcore_value(cali); + + dramc_info("Set DRAM vcore voltage to %u\n", vcore); + mt6359p_buck_set_voltage(MT6359P_GPU11, vcore); +} + +static void dramc_calibration_all_channels(struct ddr_cali *cali) +{ +} + +void init_dram(const struct dramc_data *dparam) +{ + u32 bc_bak; + u8 k_shuffle, k_shuffle_end; + u8 pll_mode = 0; + bool first_freq_k = true; + + struct ddr_cali cali = {0}; + struct mr_values mr_value; + const struct ddr_base_info *ddr_info = &dparam->ddr_info; + + cali.pll_mode = &pll_mode; + cali.mr_value = &mr_value; + cali.support_ranks = ddr_info->support_ranks; + cali.cbt_mode[RANK_0] = ddr_info->cbt_mode[RANK_0]; + cali.cbt_mode[RANK_1] = ddr_info->cbt_mode[RANK_1]; + cali.emi_config = &ddr_info->emi_config; + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + global_option_init(&cali); + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + dramc_set_broadcast(bc_bak); + + if (ddr_info->config_dvfs == DRAMC_ENABLE_DVFS) + k_shuffle_end = CALI_SEQ_MAX; + else + k_shuffle_end = CALI_SEQ1; + + for (k_shuffle = CALI_SEQ0; k_shuffle < k_shuffle_end; k_shuffle++) { + set_cali_datas(&cali, dparam, k_shuffle); + set_vcore_voltage_for_each_freq(&cali); + dfs_init_for_calibration(&cali); + + dramc_calibration_all_channels(&cali); + + first_freq_k= false; + } +} diff --git a/src/soc/mediatek/mt8192/dramc_utility.c b/src/soc/mediatek/mt8192/dramc_utility.c new file mode 100644 index 0000000..526059a --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_utility.c @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <soc/infracfg.h> + +struct dfs_frequency_table { + u32 frequency; + dram_freq_grp freq_group; + dram_div_mode div_mode; + dram_dfs_shu shuffle_saved; + vref_cali_mode vref_cali; + u32 vcore; +}; + +static const struct dfs_frequency_table freq_shuffle_table[DRAM_DFS_SHU_MAX] = { + /* frequency freq_group div_mode shuffle_saved vref_cali vcore*/ + [CALI_SEQ0] = {800, DDRFREQ_800, DIV8_MODE, DRAM_DFS_SHU4, VREF_CALI_ON, 650000}, + [CALI_SEQ1] = {1200, DDRFREQ_1200, DIV8_MODE, DRAM_DFS_SHU2, VREF_CALI_ON, 662500}, + [CALI_SEQ2] = {600, DDRFREQ_600, DIV8_MODE, DRAM_DFS_SHU5, VREF_CALI_OFF, 650000}, + [CALI_SEQ3] = {933, DDRFREQ_933, DIV8_MODE, DRAM_DFS_SHU3, VREF_CALI_OFF, 662500}, + [CALI_SEQ4] = {400, DDRFREQ_400, DIV4_MODE, DRAM_DFS_SHU6, VREF_CALI_OFF, 650000}, + [CALI_SEQ5] = {2133, DDRFREQ_2133, DIV8_MODE, DRAM_DFS_SHU0, VREF_CALI_ON, 725000}, + [CALI_SEQ6] = {1600, DDRFREQ_1600, DIV8_MODE, DRAM_DFS_SHU1, VREF_CALI_OFF, 687500}, +}; + +void dramc_set_broadcast(u32 onoff) +{ + write32(&mt8192_infracfg->dramc_wbr, onoff); +} + +u32 dramc_get_broadcast(void) +{ + return read32(&mt8192_infracfg->dramc_wbr); +} + +u8 get_fsp(const struct ddr_cali *cali) +{ + return cali->fsp; +} + +dram_div_mode get_div_mode(const struct ddr_cali *cali) +{ + return cali->div_mode; +} + +dram_freq_grp get_freq_group(const struct ddr_cali *cali) +{ + return cali->freq_group; +} + +dbi_mode get_write_dbi(const struct ddr_cali *cali) +{ + return cali->w_dbi[get_fsp(cali)]; +} + +dram_odt_state get_odt_state(const struct ddr_cali *cali) +{ + return cali->odt_onoff; +} + +dram_dfs_shu get_shu(const struct ddr_cali *cali) +{ + return cali->shu; +} + +dram_cbt_mode get_cbt_mode(const struct ddr_cali *cali) +{ + return cali->cbt_mode[cali->rank]; +} + +u32 get_vcore_value(const struct ddr_cali *cali) +{ + return cali->vcore_voltage; +} + +u32 get_frequency(const struct ddr_cali *cali) +{ + return cali->frequency; +} + +vref_cali_mode get_vref_cali(const struct ddr_cali *cali) +{ + return cali->vref_cali; +} + +dram_pinmux_type get_pinmux_type(const struct ddr_cali *cali) +{ + return cali->pinmux_type; +} + +u8 get_mck2ui_div_shift(const struct ddr_cali *cali) +{ + if (get_div_mode(cali) == DIV4_MODE) + return 2; + else + return 3; +} + +dram_dfs_shu get_shu_save_by_k_shu(dram_cali_seq k_shu) +{ + return freq_shuffle_table[k_shu].shuffle_saved; +} + +dram_freq_grp get_freq_group_by_shu_save(dram_dfs_shu shu) +{ + for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++) + if (freq_shuffle_table[k_shu].shuffle_saved == shu) + return freq_shuffle_table[k_shu].freq_group; + + dramc_err("Invalid shuffle:%d\n", shu); + return DDRFREQ_800; +} + +u32 get_frequency_by_shu(dram_dfs_shu shu) +{ + for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++) + if (freq_shuffle_table[k_shu].shuffle_saved == shu) + return freq_shuffle_table[k_shu].frequency; + + dramc_err("Invalid shuffle:%d\n", shu); + return 800; +} + +dram_freq_grp get_highest_freq_group(void) +{ + dram_freq_grp highest_freq = DDRFREQ_800; + + for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++) + if (freq_shuffle_table[k_shu].freq_group > highest_freq) + highest_freq = freq_shuffle_table[k_shu].freq_group; + + dramc_dbg("Highest freq is :%d\n", highest_freq); + return highest_freq; +} + +void set_cali_datas(struct ddr_cali *cali, const struct dramc_data *dparam, dram_cali_seq k_shu) +{ + cali->chn = CHANNEL_A; + cali->rank = RANK_0; + cali->fsp = (freq_shuffle_table[k_shu].freq_group < DDRFREQ_1600) ? FSP_0 : FSP_1; + cali->w_dbi[FSP_0] = DBI_OFF; + cali->w_dbi[FSP_1] = DBI_ON; + cali->frequency = freq_shuffle_table[k_shu].frequency; + cali->freq_group = freq_shuffle_table[k_shu].freq_group; + cali->div_mode = freq_shuffle_table[k_shu].div_mode; + cali->shu = freq_shuffle_table[k_shu].shuffle_saved; + cali->vref_cali = freq_shuffle_table[k_shu].vref_cali; + cali->vcore_voltage = freq_shuffle_table[k_shu].vcore; + cali->odt_onoff = (cali->fsp == FSP_0) ? ODT_OFF : ODT_ON; + cali->params = &dparam->freq_params[cali->shu]; + + dramc_dbg("cali data(size:%ld) use fsp:%d, freq_group:%d, div_mode:%d, shu:%d, vref_cali:%d, odt_onoff:%d, vcore:%d\n", + sizeof(*cali), cali->fsp, cali->freq_group, cali->div_mode, cali->shu, + cali->vref_cali, cali->odt_onoff, cali->vcore_voltage); +} + +void dramc_auto_refresh_switch(u8 chn, bool enable) +{ + SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, enable ? 0 : 1); + + if (!enable) { + udelay(READ32_BITFIELD(&ch[chn].nao.misc_statusa, + MISC_STATUSA_REFRESH_QUEUE_CNT)); + } +} diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c index 9e48918..f83acd3 100644 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/emi.h> +#include <soc/dramc_pi_api.h> size_t sdram_size(void) { @@ -11,4 +11,5 @@ void mt_set_emi(const struct dramc_data *dparam) { + init_dram(dparam); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4877b69de1bfa4ff981d8eb386efbddb9e0f5c2 Gerrit-Change-Number: 44700 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 75

Change in coreboot[master]: soc/amd/common: Use only byte access for IOMUX
by Kyösti Mälkki (Code Review) 16 Dec '20

16 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42978 ) Change subject: soc/amd/common: Use only byte access for IOMUX ...................................................................... soc/amd/common: Use only byte access for IOMUX Change-Id: Ia3c4fb41b5851b1c0ffc6bbec7d1c051e232fc94 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h 1 file changed, 2 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/42978/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index e684e36..34300af 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -239,36 +239,18 @@ write8(acpimmio_smbus + reg, value); } +/* These iomux_read/write8 are to be deprecated to enforce proper + use of <gpio.h> API for pin configurations. */ static inline uint8_t iomux_read8(uint8_t reg) { return read8(acpimmio_iomux + reg); } -static inline uint16_t iomux_read16(uint8_t reg) -{ - return read16(acpimmio_iomux + reg); -} - -static inline uint32_t iomux_read32(uint8_t reg) -{ - return read32(acpimmio_iomux + reg); -} - static inline void iomux_write8(uint8_t reg, uint8_t value) { write8(acpimmio_iomux + reg, value); } -static inline void iomux_write16(uint8_t reg, uint16_t value) -{ - write16(acpimmio_iomux + reg, value); -} - -static inline void iomux_write32(uint8_t reg, uint32_t value) -{ - write32(acpimmio_iomux + reg, value); -} - static inline uint8_t misc_read8(uint8_t reg) { return read8(acpimmio_misc + reg); -- To view, visit https://review.coreboot.org/c/coreboot/+/42978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3c4fb41b5851b1c0ffc6bbec7d1c051e232fc94 Gerrit-Change-Number: 42978 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: mb/google/octopus/variants/casta: Add support zinitix touchpad
by shkim (Code Review) 16 Dec '20

16 Dec '20

Hello SH Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/48634 to review the following change. Change subject: mb/google/octopus/variants/casta: Add support zinitix touchpad ...................................................................... mb/google/octopus/variants/casta: Add support zinitix touchpad This change adds support zinitix touchpad for casta/bluebird. BRANCH=firmware-octopus-11297.B BUG=b:175618033 TEST=built and verified touchpad worked on casta Change-Id: I1a8f562de19d1a8160d52c65400553f0c68393e0 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/casta/overridetree.cb 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/48634/1 diff --git a/src/mainboard/google/octopus/variants/casta/overridetree.cb b/src/mainboard/google/octopus/variants/casta/overridetree.cb index 3f2a884..be322f5 100644 --- a/src/mainboard/google/octopus/variants/casta/overridetree.cb +++ b/src/mainboard/google/octopus/variants/casta/overridetree.cb @@ -137,6 +137,16 @@ register "probed" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""ZNT0000"" + register "generic.cid" = ""PNP0C50"" + register "generic.desc" = ""Zinitix Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPIO_135_IRQ)" + register "generic.wake" = "GPE0_DW3_27" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0xE" + device i2c 40 on end + end end # - I2C 6 end -- To view, visit https://review.coreboot.org/c/coreboot/+/48634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8f562de19d1a8160d52c65400553f0c68393e0 Gerrit-Change-Number: 48634 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: WIP: dcm: mt8192: Enable DCM
by Yidi Lin (Code Review) 16 Dec '20

16 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46407 ) Change subject: WIP: dcm: mt8192: Enable DCM ...................................................................... WIP: dcm: mt8192: Enable DCM Enable DCM settings. /* INFRACFG_AO */ dcm_infracfg_ao_aximem_bus_dcm(on); dcm_infracfg_ao_infra_bus_dcm(on); dcm_infracfg_ao_infra_conn_bus_dcm(on); dcm_infracfg_ao_infra_rx_p2p_dcm(on); dcm_infracfg_ao_peri_bus_dcm(on); dcm_infracfg_ao_peri_module_dcm(on); /* INFRA_AO_BCRM */ dcm_infra_ao_bcrm_infra_bus_dcm(on); dcm_infra_ao_bcrm_peri_bus_dcm(on); /* INFRACFG_AO_MEM */ /* move to preloader */ /* dcm_infracfg_ao_mem_dcm_emi_group(on); */ Change-Id: I5528d176b6bb1f9a5960de981766235510e6ebf1 --- M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 2 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/46407/1 diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 09c4c471..35e8ff2 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -306,4 +306,59 @@ DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) +enum { + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = ((0x1f << 12) | \ + (0x1 << 17) | \ + (0x1 << 18)), + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = ((0x10 << 12) | \ + (0x1 << 17) | \ + (0x0 << 18)), + INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x1 << 3) | \ + (0x1 << 4) | \ + (0x1f << 5) | \ + (0x1f << 10) | \ + (0x1 << 20) | \ + (0x1 << 23) | \ + (0x1 << 30)), + INFRACFG_AO_INFRA_BUS_DCM_REG0_ON = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x0 << 3) | \ + (0x0 << 4) | \ + (0x10 << 5) | \ + (0x1 << 10) | \ + (0x1 << 20) | \ + (0x1 << 23) | \ + (0x1 << 30)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK = ((0x1 << 8)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON = ((0x1 << 8)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK = ((0x1 << 8)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON = ((0x0 << 8)), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK = ((0xf << 0)), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON = ((0x0 << 0)), + INFRACFG_AO_PERI_BUS_DCM_REG0_MASK = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x1 << 3) | \ + (0x1 << 4) | \ + (0x1f << 5) | \ + (0x1f << 10) | \ + (0x1f << 15) | \ + (0x1 << 20) | \ + (0x1 << 21)), + INFRACFG_AO_PERI_BUS_DCM_REG0_ON = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x0 << 3) | \ + (0x0 << 4) | \ + (0x1f << 5) | \ + (0x0 << 10) | \ + (0x1f << 15) | \ + (0x1 << 20) | \ + (0x1 << 21)), + INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK = ((0x1 << 29) | \ + (0x1 << 31)), + INFRACFG_AO_PERI_MODULE_DCM_REG0_ON = ((0x1 << 29) | \ + (0x1 << 31)), +}; + #endif /* SOC_MEDIATEK_MT8192_PLL_H */ diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 24cfafd..0366cd6 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -427,6 +427,27 @@ /* enable infrasys DCM */ setbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + // dcm_infracfg_ao_aximem_bus_dcm + clrsetbits_le32(&mt8192_infracfg->infra_aximem_idle_bit_en_0, + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK, INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON); + // dcm_infracfg_ao_infra_bus_dcm + clrsetbits_le32(&mt8192_infracfg->infra_bus_dcm_ctrl, + INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK, INFRACFG_AO_INFRA_BUS_DCM_REG0_ON); + // dcm_infracfg_ao_infra_conn_bus_dcm + clrsetbits_le32(&mt8192_infracfg->module_sw_cg_2_set, + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON); + clrsetbits_le32(&mt8192_infracfg->module_sw_cg_2_clr, + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON); + // dcm_infracfg_ao_infra_rx_p2p_dcm + clrsetbits_le32(&mt8192_infracfg->p2p_rx_clk_on, + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK, INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON); + // dcm_infracfg_ao_peri_bus_dcm + clrsetbits_le32(&mt8192_infracfg->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_BUS_DCM_REG0_MASK, INFRACFG_AO_PERI_BUS_DCM_REG0_ON); + // dcm_infracfg_ao_peri_module_dcm + clrsetbits_le32(&mt8192_infracfg->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK, INFRACFG_AO_PERI_MODULE_DCM_REG0_ON); + /* initialize SPM request */ setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff); clrsetbits32(&mtk_topckgen->clk_scp_cfg_1, 0x100c, 0x3); -- To view, visit https://review.coreboot.org/c/coreboot/+/46407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5528d176b6bb1f9a5960de981766235510e6ebf1 Gerrit-Change-Number: 46407 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

4 47

Change in coreboot[master]: soc/mediatek/mt8192: ufs: disable refer clk
by Yidi Lin (Code Review) 16 Dec '20

16 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46408 ) Change subject: soc/mediatek/mt8192: ufs: disable refer clk ...................................................................... soc/mediatek/mt8192: ufs: disable refer clk ufs refer clk is enabled by default, which will cause the UFSHCI hold the SPM signal and lead to suspend fail. Since ufs kernel driver is not built-in, so disable refer clk in coreboot stage. Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Signed-off-by: Chaotian Jing <chaotian.jing(a)mediatek.com> Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 33 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 4ce5e6a..7b098e8 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -48,6 +48,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c ramstage-y += devapc.c +ramstage-y += ufs.c ramstage-y += mcupm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 19728a3..85eac5b 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -47,6 +47,7 @@ SPI7_BASE = IO_PHYS + 0x0101E000, SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, SFLASH_REG_BASE = IO_PHYS + 0x01234000, + UFSHCI_BASE = IO_PHYS + 0x01270000, EFUSEC_BASE = IO_PHYS + 0x01C10000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, IOCFG_BM_BASE = IO_PHYS + 0x01D10000, diff --git a/src/soc/mediatek/mt8192/include/soc/ufs.h b/src/soc/mediatek/mt8192/include/soc/ufs.h new file mode 100644 index 0000000..259aaf4 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/ufs.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_UFS_H +#define SOC_MEDIATEK_MT8192_UFS_H + +#include <device/mmio.h> +#include <soc/addressmap.h> + +void ufs_disable_refclk(void); + +enum ufshci_offset { + REG_UFS_REFCLK_CTRL = 0x144, +}; + +#define UFS_REFCLK_CTRL (ufshci_base + (unsigned long)REG_UFS_REFCLK_CTRL) + +#endif /* SOC_MEDIATEK_MT8192_UFS_H */ diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index ba153f2..c865e6f 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -6,6 +6,7 @@ #include <symbols.h> #include <soc/devapc.h> #include <soc/mcupm.h> +#include <soc/ufs.h> static void soc_read_resources(struct device *dev) { @@ -16,7 +17,8 @@ { mtk_mmu_disable_l2c_sram(); dapc_init(); - mcupm_init(); + mcupm_init(); + ufs_disable_refclk(); } static struct device_operations soc_ops = { diff --git a/src/soc/mediatek/mt8192/ufs.c b/src/soc/mediatek/mt8192/ufs.c new file mode 100644 index 0000000..854ef4c --- /dev/null +++ b/src/soc/mediatek/mt8192/ufs.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ufs.h> + +static unsigned long ufshci_base = (unsigned long)UFSHCI_BASE; + +void ufs_disable_refclk(void) +{ + /* disable ref clock to let UFSHCI release SPM signal */ + write32((void*)UFS_REFCLK_CTRL, 0); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 Gerrit-Change-Number: 46408 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit December 2020