Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48559 )
Change subject: soc/intel/xeon_sp/skx: Hook up microcode blob ......................................................................
soc/intel/xeon_sp/skx: Hook up microcode blob
TESTED on ocp/tiagopass: MCU are correctly updated (installed revision reported with an out of tree patch)
Change-Id: I05ddc64090424aa333848d9a0f54f21538faf94c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.inc 3 files changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/48559/1
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 2028a5e..664f960 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -57,7 +57,6 @@ select TSC_MONOTONIC_TIMER select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS - select MICROCODE_BLOB_NOT_HOOKED_UP select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_CAR select CPU_INTEL_COMMON_SMM diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 369d474..43337b5 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -2,6 +2,10 @@
if SOC_INTEL_COOPERLAKE_SP
+config SOC_SPECIFIC_OPTIONS + def_bool y + select MICROCODE_BLOB_NOT_HOOKED_UP + config FSP_HEADER_PATH string "Location of FSP headers" depends on MAINBOARD_USES_FSP2_0 diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index 6ee610e..085dd20 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -29,4 +29,6 @@
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/skx/include -I$(src)/soc/intel/xeon_sp/skx
+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-04 + endif ## CONFIG_SOC_INTEL_SKYLAKE_SP
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48559 )
Change subject: soc/intel/xeon_sp/skx: Hook up microcode blob ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/48559/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48559/1//COMMIT_MSG@9 PS1, Line 9: MCU are correctly updated microcode is correctly updated
Hello build bot (Jenkins), Marc Jones, Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48559
to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp/skx: Hook up microcode blob ......................................................................
soc/intel/xeon_sp/skx: Hook up microcode blob
TESTED on ocp/tiagopass: Microcode updates are properly applied (via FIT). Tested with out of tree patches to report the revision.
Change-Id: I05ddc64090424aa333848d9a0f54f21538faf94c Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.inc 3 files changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/48559/2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48559 )
Change subject: soc/intel/xeon_sp/skx: Hook up microcode blob ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48559/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48559/1//COMMIT_MSG@9 PS1, Line 9: MCU are correctly updated
microcode is correctly updated
Done
Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48559 )
Change subject: soc/intel/xeon_sp/skx: Hook up microcode blob ......................................................................
soc/intel/xeon_sp/skx: Hook up microcode blob
TESTED on ocp/tiagopass: Microcode updates are properly applied (via FIT). Tested with out of tree patches to report the revision.
Change-Id: I05ddc64090424aa333848d9a0f54f21538faf94c Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/48559 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.inc 3 files changed, 6 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 2028a5e..664f960 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -57,7 +57,6 @@ select TSC_MONOTONIC_TIMER select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS - select MICROCODE_BLOB_NOT_HOOKED_UP select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_CAR select CPU_INTEL_COMMON_SMM diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 369d474..43337b5 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -2,6 +2,10 @@
if SOC_INTEL_COOPERLAKE_SP
+config SOC_SPECIFIC_OPTIONS + def_bool y + select MICROCODE_BLOB_NOT_HOOKED_UP + config FSP_HEADER_PATH string "Location of FSP headers" depends on MAINBOARD_USES_FSP2_0 diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index 6ee610e..085dd20 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -29,4 +29,6 @@
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/skx/include -I$(src)/soc/intel/xeon_sp/skx
+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-04 + endif ## CONFIG_SOC_INTEL_SKYLAKE_SP
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)