Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48589 )
Change subject: nb/intel/ironlake: Add comment about MCH scan chains ......................................................................
nb/intel/ironlake: Add comment about MCH scan chains
Change-Id: I3e60cfc1fd3352b8b0c7460503179425cc593d36 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/48589/1
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index ecf8ef8..beb2244 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -101,6 +101,15 @@ out[1] = ret.hi; }
+/* + * Ironlake memory I/O timings are located in scan chains, accessible + * through MCHBAR register groups. Each channel has a scan chain, and + * there's a global scan chain too. Each chain is broken into smaller + * sections of N bits, where N <= 32. Each section allows reading and + * writing a certain parameter. Each section contains N - 2 data bits + * and two additional bits: a Mask bit, and a Halt bit. + */ + /* OK */ static void write_1d0(u32 val, u16 addr, int bits, int flag) {
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48589 )
Change subject: nb/intel/ironlake: Add comment about MCH scan chains ......................................................................
Patch Set 1: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48589 )
Change subject: nb/intel/ironlake: Add comment about MCH scan chains ......................................................................
nb/intel/ironlake: Add comment about MCH scan chains
Change-Id: I3e60cfc1fd3352b8b0c7460503179425cc593d36 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48589 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 9 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index ecf8ef8..beb2244 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -101,6 +101,15 @@ out[1] = ret.hi; }
+/* + * Ironlake memory I/O timings are located in scan chains, accessible + * through MCHBAR register groups. Each channel has a scan chain, and + * there's a global scan chain too. Each chain is broken into smaller + * sections of N bits, where N <= 32. Each section allows reading and + * writing a certain parameter. Each section contains N - 2 data bits + * and two additional bits: a Mask bit, and a Halt bit. + */ + /* OK */ static void write_1d0(u32 val, u16 addr, int bits, int flag) {
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Angel Pons (Code Review) -
Arthur Heymans (Code Review)
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Hung-Te Lin (Code Review)