Change in coreboot[master]: WIP: soc/mediatek/mt8192: Add display controller driver

[yongqiang niu (Code Review)]

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: WIP: soc/mediatek/mt8192: Add display controller driver
......................................................................

WIP: soc/mediatek/mt8192: Add display controller driver

The MT8192 SOC has a DISP (display controller) that supports
overlay, read/write DMA, ... etc. The output of DISP goes to
display interface DSI, DPI or DBI directly.

BUG=b:80501386,b:155713214
BRANCH=none
TEST=Boots correctly on asurada

Signed-off-by: Yongqiang Niu 
Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/ddp.c
M src/soc/mediatek/mt8192/include/soc/addressmap.h
A src/soc/mediatek/mt8192/include/soc/ddp.h
4 files changed, 485 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46577/1

diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index b2a8a9e..119d999 100755
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -59,6 +59,7 @@
 ramstage-y += ../common/uart.c
 ramstage-y += ../common/usb.c usb.c

+ramstage-y += ../common/ddp.c ddp.c
 ramstage-y += ../common/dsi.c dsi.c

MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192
diff --git a/src/soc/mediatek/mt8192/ddp.c b/src/soc/mediatek/mt8192/ddp.c
new file mode 100644
index 0000000..0d5eab5
--- /dev/null
+++ b/src/soc/mediatek/mt8192/ddp.c
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <edid.h>
+#include <soc/addressmap.h>
+#include <soc/ddp.h>
+
+static void disp_config_main_path_connection(void)
+{
+	/* ovl0->ovl0_2l */
+	write32(&mmsys_cfg->mmsys_ovl_mout_en,
+		(DISP_OVL0_GO_BG | DISP_OVL0_2L_GO_BLEND));
+	write32(&mmsys_cfg->ovl0_2l_mout_en, OVL0_MOUT_EN_DISP_RDMA0);
+	write32(&mmsys_cfg->rdma0_sel_in, RDMA0_SEL_IN_OVL0_2L);
+	write32(&mmsys_cfg->rdma0_sout_sel, RDMA0_SOUT_COLOR0);
+	write32(&mmsys_cfg->ccorr0_sout_sel, CCORR0_SOUT_AAL0);
+	write32(&mmsys_cfg->aal0_sel_in, AAL0_SEL_IN_CCORR0);
+	write32(&mmsys_cfg->dither0_mout_en, DITHER0_MOUT_DSI0);
+	write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0);
+}
+
+static void disp_config_main_path_mutex(void)
+{
+	write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH);
+
+	/* Clock source from DSI0 */
+	write32(&disp_mutex->mutex[0].ctl,
+		MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6));
+	write32(&disp_mutex->mutex[0].en, BIT(0));
+}
+
+static void ovl_bgclr_in_sel(u32 idx)
+{
+	setbits32(&disp_ovl[idx]->datapath_con, BIT(2));
+}
+
+static void ovl_layer_smi_id_en(u32 idx)
+{
+	printk(BIOS_INFO, "%s\n", __func__);
+
+	setbits32(&disp_ovl[idx]->datapath_con, BIT(0));
+}
+
+static void ccorr_config(u32 width, u32 height)
+{
+	struct disp_ccorr_regs *const regs = disp_ccorr;
+	int enable_relay = 0;
+
+	printk(BIOS_INFO, "%s\n", __func__);
+
+	write32(&regs->size, width << 16 | height);
+
+	if (enable_relay) {
+		setbits32(&regs->cfg, PQ_RELAY_MODE);
+		clrbits32(&regs->cfg, PQ_ENGINE_EN);
+	} else {
+		clrbits32(&regs->cfg, PQ_RELAY_MODE);
+		setbits32(&regs->cfg, PQ_ENGINE_EN);
+	}
+
+	write32(&regs->en, PQ_EN);
+}
+
+static void aal_config(u32 width, u32 height)
+{
+	struct disp_aal_regs *const regs = disp_aal;
+	int enable_relay = 1;
+
+	printk(BIOS_INFO, "%s\n", __func__);
+
+	write32(&regs->size, width << 16 | height);
+	write32(&regs->output_size, width << 16 | height);
+
+	if (enable_relay) {
+		setbits32(&regs->cfg, PQ_RELAY_MODE);
+		clrbits32(&regs->cfg, PQ_ENGINE_EN);
+	} else {
+		clrbits32(&regs->cfg, PQ_RELAY_MODE);
+		setbits32(&regs->cfg, PQ_ENGINE_EN);
+	}
+
+	write32(&regs->en, PQ_EN);
+}
+
+static void gamma_config(u32 width, u32 height)
+{
+	struct disp_gamma_regs *const regs = disp_gamma;
+	int enable_relay = 0;
+
+	printk(BIOS_INFO, "%s\n", __func__);
+
+	write32(&regs->size, width << 16 | height);
+
+	if (enable_relay)
+		setbits32(&regs->cfg, PQ_RELAY_MODE);
+	else
+		clrbits32(&regs->cfg, PQ_RELAY_MODE);
+
+	write32(&regs->en, PQ_EN);
+}
+
+static void postmask_config(u32 width, u32 height)
+{
+	struct disp_postmask_regs *const regs = disp_postmask;
+	int enable_relay = 1;
+
+	printk(BIOS_INFO, "%s\n", __func__);
+
+	write32(&regs->size, width << 16 | height);
+
+	if (enable_relay)
+		setbits32(&regs->cfg, PQ_RELAY_MODE);
+	else
+		clrbits32(&regs->cfg, PQ_RELAY_MODE);
+
+	write32(&regs->en, PQ_EN);
+}
+
+static void dither_config(u32 width, u32 height)
+{
+	struct disp_dither_regs *const regs = disp_dither;
+	int enable_relay = 1;
+
+	printk(BIOS_INFO, "%s\n", __func__);
+
+	write32(&regs->size, width << 16 | height);
+
+	if (enable_relay)
+		setbits32(&regs->cfg, PQ_RELAY_MODE);
+	else
+		clrbits32(&regs->cfg, PQ_RELAY_MODE);
+
+	write32(&regs->en, PQ_EN);
+}
+
+
+static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh)
+{
+	u32 idx = 0;
+	u32 pixel_clk = width * height * vrefresh;
+
+	printk(BIOS_INFO, "%s\n", __func__);
+
+	for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) {
+		ovl_set_roi(idx, width, height, idx ? 0 : 0xff0000ff);
+		ovl_layer_smi_id_en(idx);
+	}
+
+	rdma_config(width, height, pixel_clk, 5 * KiB);
+	color_start(width, height);
+	ccorr_config(width, height);
+	aal_config(width, height);
+	gamma_config(width, height);
+	postmask_config(width, height);
+	dither_config(width, height);
+	disp_config_main_path_connection();
+	disp_config_main_path_mutex();
+}
+
+static void disp_clock_on(void)
+{
+	clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL);
+
+	clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_ALL);
+
+	clrbits32(&mmsys_cfg->mmsys_cg_con2, CG_CON2_DISP_ALL);
+}
+
+void mtk_ddp_init(void)
+{
+	disp_clock_on();
+	/* Turn off M4U port. */
+	write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_DISP_POSTMASK0), 0);
+	write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0_HDR), 0);
+	write32((void *)(SMI_LARB0 + SMI_LARB_L0_OVL_RDMA0), 0);
+}
+
+void mtk_ddp_mode_set(const struct edid *edid)
+{
+	u32 fmt = OVL_INFMT_RGBA8888;
+	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+	u32 width = edid->mode.ha;
+	u32 height = edid->mode.va;
+	u32 vrefresh = edid->mode.refresh;
+
+	printk(BIOS_INFO, "%s display resolution: %dx%d@%d bpp %d\n",
+		__func__, width, height, vrefresh, bpp);
+
+	if (!vrefresh) {
+		vrefresh = 60;
+		printk(BIOS_INFO, "%s invalid vrefresh %d\n",
+		__func__, vrefresh);
+	}
+
+	main_disp_path_setup(width, height, vrefresh);
+	rdma_start();
+	ovl_layer_config(fmt, bpp, width, height);
+	ovl_bgclr_in_sel(1);
+}
diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h
index eac4a9a..198beaa 100644
--- a/src/soc/mediatek/mt8192/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h
@@ -65,6 +65,19 @@
    MSDC0_BASE		= IO_PHYS + 0x01F60000,
    DEVAPC_INFRA_AO_BASE		= IO_PHYS + 0x00030000,
    MIPITX_BASE		= IO_PHYS + 0x01E50000,
+	MMSYS_BASE		= IO_PHYS + 0x04000000,
+	DISP_MUTEX_BASE		= IO_PHYS + 0x04001000,
+	SMI_BASE		= IO_PHYS + 0x04002000,
+	SMI_LARB0		= IO_PHYS + 0x04003000,
+	DISP_OVL0_BASE		= IO_PHYS + 0x04005000, /* ovl0 */
+	DISP_OVL1_BASE		= IO_PHYS + 0x04006000, /* ovl0_2l */
+	DISP_RDMA0_BASE		= IO_PHYS + 0x04007000,
+	DISP_COLOR0_BASE	= IO_PHYS + 0x04009000,
+	DISP_CCORR0_BASE	= IO_PHYS + 0x0400A000,
+	DISP_AAL0_BASE		= IO_PHYS + 0x0400B000,
+	DISP_GAMMA0_BASE	= IO_PHYS + 0x0400C000,
+	DISP_POSTMASK0_BASE	= IO_PHYS + 0x0400D000,
+	DISP_DITHER0_BASE	= IO_PHYS + 0x0400E000,
    DSI0_BASE		= IO_PHYS + 0x04010000,
 };

diff --git a/src/soc/mediatek/mt8192/include/soc/ddp.h b/src/soc/mediatek/mt8192/include/soc/ddp.h
new file mode 100644
index 0000000..18b2e27
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/ddp.h
@@ -0,0 +1,272 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MT8183_SOC_DDP_H_
+#define _MT8183_SOC_DDP_H_
+
+#include <soc/addressmap.h>
+#include <soc/ddp_common.h>
+#include <types.h>
+
+#define MAIN_PATH_OVL_NR 2
+
+struct mmsys_cfg_regs {
+	u32 reserved_0x000[64];		/* 0x000 */
+	u32 mmsys_cg_con0;		/* 0x100 */
+	u32 mmsys_cg_set0;		/* 0x104 */
+	u32 mmsys_cg_clr0;		/* 0x108 */
+	u32 reserved_0x10C;		/* 0x10C */
+	u32 mmsys_cg_con1;		/* 0x110 */
+	u32 mmsys_cg_set1;		/* 0x114 */
+	u32 mmsys_cg_clr1;		/* 0x118 */
+	u32 reserved_0x11C[33];		/* 0x11C */
+	u32 mmsys_cg_con2;		/* 0x1A0 */
+	u32 mmsys_cg_set2;		/* 0x1A4 */
+	u32 mmsys_cg_clr2;		/* 0x1A8 */
+	u32 reserved_0x1AC[853];	/* 0x1AC */
+	u32 reserved_0xF00;		/* 0xF00 */
+	u32 mmsys_ovl_mout_en;		/* 0xF04 */
+	u32 reserved_0xF08;		/* 0xF08 */
+	u32 reserved_0xF0C;		/* 0xF0C */
+	u32 reserved_0xF10;		/* 0xF10 */
+	u32 reserved_0xF14;		/* 0xF14 */
+	u32 ovl0_2l_mout_en;		/* 0xF18 */
+	u32 ovl0_mout_en;		/* 0xF1C */
+	u32 reserved_0xF20;		/* 0xF20 */
+	u32 reserved_0xF24;		/* 0xF24 */
+	u32 reserved_0xF28;		/* 0xF28 */
+	u32 rdma0_sel_in;		/* 0xF2C */
+	u32 rdma0_sout_sel;		/* 0xF30 */
+	u32 ccorr0_sout_sel;		/* 0xF34 */
+	u32 aal0_sel_in;		/* 0xF38 */
+	u32 dither0_mout_en;		/* 0xF3C*/
+	u32 dsi0_sel_in;		/* 0xF40*/
+};
+
+check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100);
+check_member(mmsys_cfg_regs, mmsys_cg_con1, 0x110);
+check_member(mmsys_cfg_regs, mmsys_cg_con2, 0x1A0);
+check_member(mmsys_cfg_regs, mmsys_ovl_mout_en, 0xF04);
+check_member(mmsys_cfg_regs, ovl0_2l_mout_en, 0xF18);
+check_member(mmsys_cfg_regs, dsi0_sel_in, 0xF40);
+static struct mmsys_cfg_regs *const mmsys_cfg =
+	(void *)MMSYS_BASE;
+
+
+/* DISP_REG_CONFIG_MMSYS_CG_CON0
+   Configures free-run clock gating 0
+	0: Enable clock
+	1: Clock gating  */
+enum {
+	CG_CON0_DISP_MUTEX0	= BIT(0),
+	CG_CON0_DISPSYS_CONFIG	= BIT(1),
+	CG_CON0_DISP_OVL0	= BIT(2),
+	CG_CON0_DISP_RDMA0	= BIT(3),
+	CG_CON0_DISP_OVL0_2L	= BIT(4),
+	CG_CON0_DISP_AAL0	= BIT(8),
+	CG_CON0_DISP_CCORR0	= BIT(9),
+	CG_CON0_DISP_DITHER0	= BIT(10),
+	CG_CON0_SMI_INFRA	= BIT(11),
+	CG_CON0_DISP_GAMMA0	= BIT(12),
+	CG_CON0_DISP_POSTMASK0	= BIT(13),
+	CG_CON0_DISP_DSI0	= BIT(15),
+	CG_CON0_DISP_COLOR0	= BIT(16),
+	CG_CON0_SMI_COMMON	= BIT(17),
+
+	CG_CON0_SMI_GALS	= BIT(27),
+	CG_CON0_DISP_ALL	= CG_CON0_SMI_INFRA |
+				  CG_CON0_SMI_COMMON |
+				  CG_CON0_SMI_GALS |
+				  CG_CON0_DISP_MUTEX0 |
+				  CG_CON0_DISPSYS_CONFIG |
+				  CG_CON0_DISP_OVL0 |
+				  CG_CON0_DISP_RDMA0 |
+				  CG_CON0_DISP_OVL0_2L |
+				  CG_CON0_DISP_AAL0 |
+				  CG_CON0_DISP_CCORR0 |
+				  CG_CON0_DISP_DITHER0 |
+				  CG_CON0_DISP_GAMMA0 |
+				  CG_CON0_DISP_POSTMASK0 |
+				  CG_CON0_DISP_DSI0 |
+				  CG_CON0_DISP_COLOR0,
+	CG_CON0_ALL		= 0xffffffff
+};
+
+/* DISP_REG_CONFIG_MMSYS_CG_CON1
+   Configures free-run clock gating 1
+	0: Enable clock
+	1: Clock gating */
+enum {
+	CG_CON1_SMI_IOMMU	= BIT(0),
+	CG_CON1_DISP_ALL	= CG_CON1_SMI_IOMMU,
+	CG_CON1_ALL		= 0xffffffff
+};
+
+enum {
+	CG_CON2_DSI_DSI0	= BIT(0),
+	CG_CON2_DPI_DPI0	= BIT(8),
+	CG_CON2_MM_26MHZ	= BIT(24),
+	CG_CON2_DISP_ALL	= CG_CON2_DSI_DSI0 |
+				  CG_CON2_MM_26MHZ,
+	CG_CON2_ALL		= 0xffffffff
+};
+
+
+enum {
+	DISP_OVL0_GO_BLEND	= BIT(0),
+	DISP_OVL0_GO_BG		= BIT(1),
+	DISP_OVL0_2L_GO_BLEND	= BIT(2),
+	DISP_OVL0_2L_GO_BG	= BIT(3),
+	OVL0_MOUT_EN_DISP_RDMA0	= BIT(0),
+	DITHER0_MOUT_DSI0	= BIT(0),
+};
+
+enum {
+	RDMA0_SEL_IN_OVL0_2L	= 0x3,
+	RDMA0_SOUT_COLOR0	= 0x1,
+	CCORR0_SOUT_AAL0	= 0x1,
+	AAL0_SEL_IN_CCORR0	= 0x1,
+	DSI0_SEL_IN_DITHER0	= 0x1,
+};
+
+struct disp_mutex_regs {
+	u32 inten;
+	u32 intsta;
+	u32 reserved0[6];
+	struct {
+		u32 en;
+		u32 dummy;
+		u32 rst;
+		u32 ctl;
+		u32 mod;
+		u32 reserved[3];
+	} mutex[12];
+};
+
+static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE;
+
+enum {
+	MUTEX_MOD_DISP_OVL0		= BIT(0),
+	MUTEX_MOD_DISP_OVL0_2L		= BIT(1),
+	MUTEX_MOD_DISP_RDMA0		= BIT(2),
+	MUTEX_MOD_DISP_COLOR0		= BIT(4),
+	MUTEX_MOD_DISP_CCORR0		= BIT(5),
+	MUTEX_MOD_DISP_AAL0		= BIT(6),
+	MUTEX_MOD_DISP_GAMMA0		= BIT(7),
+	MUTEX_MOD_DISP_POSTMASK0	= BIT(8),
+	MUTEX_MOD_DISP_DITHER0		= BIT(9),
+	MUTEX_MOD_MAIN_PATH		= MUTEX_MOD_DISP_OVL0 |
+					  MUTEX_MOD_DISP_OVL0_2L |
+					  MUTEX_MOD_DISP_RDMA0 |
+					  MUTEX_MOD_DISP_COLOR0 |
+					  MUTEX_MOD_DISP_CCORR0 |
+					  MUTEX_MOD_DISP_AAL0 |
+					  MUTEX_MOD_DISP_GAMMA0 |
+					  MUTEX_MOD_DISP_POSTMASK0 |
+					  MUTEX_MOD_DISP_DITHER0,
+};
+
+enum {
+	MUTEX_SOF_SINGLE_MODE = 0,
+	MUTEX_SOF_DSI0 = 1,
+	MUTEX_SOF_DPI0 = 2,
+};
+
+struct disp_ccorr_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 status;
+	u32 reserved0[3];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+	u32 reserved2[27];
+	u32 shadow;
+};
+check_member(disp_ccorr_regs, shadow, 0xA0);
+
+struct disp_gamma_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 status;
+	u32 reserved0[3];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+};
+check_member(disp_gamma_regs, size, 0x30);
+
+struct disp_aal_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 status;
+	u32 reserved0[3];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+	u32 reserved2[47];
+	u32 shadow;
+	u32 reserved3[249];
+	u32 output_size;
+};
+check_member(disp_aal_regs, shadow, 0xF0);
+check_member(disp_aal_regs, output_size, 0x4D8);
+
+struct disp_postmask_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 reserved0[4];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+};
+check_member(disp_postmask_regs, size, 0x30);
+
+struct disp_dither_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 status;
+	u32 reserved0[3];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+	u32 reserved2[51];
+	u32 shadow;
+};
+check_member(disp_dither_regs, shadow, 0x100);
+
+enum {
+	PQ_EN		= BIT(0),
+	PQ_RELAY_MODE	= BIT(0),
+	PQ_ENGINE_EN	= BIT(1),
+};
+
+static struct disp_ccorr_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE;
+
+static struct disp_aal_regs *const disp_aal = (void *)DISP_AAL0_BASE;
+
+static struct disp_gamma_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE;
+
+static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE;
+
+static struct disp_postmask_regs *const disp_postmask = (void *)DISP_POSTMASK0_BASE;
+
+enum {
+	SMI_LARB_PORT_L0_DISP_POSTMASK0	= 0x380,
+	SMI_LARB_PORT_L0_OVL_RDMA0_HDR	= 0x384,
+	SMI_LARB_L0_OVL_RDMA0	= 0x388,
+};
+
+void mtk_ddp_init(void);
+void mtk_ddp_mode_set(const struct edid *edid);
+
+#endif

[yongqiang niu (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46577

to look at the new patch set (#2).

Change subject: WIP: soc/mediatek/mt8192: Add display controller driver
......................................................................

WIP: soc/mediatek/mt8192: Add display controller driver

The MT8192 SOC has a DISP (display controller) that supports
overlay, read/write DMA, ... etc. The output of DISP goes to
display interface DSI, DPI or DBI directly.

BUG=b:80501386,b:155713214
BRANCH=none
TEST=Boots correctly on asurada

Signed-off-by: Yongqiang Niu 
Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/ddp.c
M src/soc/mediatek/mt8192/include/soc/addressmap.h
A src/soc/mediatek/mt8192/include/soc/ddp.h
4 files changed, 482 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46577/2

Change in coreboot[master]: soc/mediatek/mt8192: Add ddp driver

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has uploaded a new patch set (#6) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: soc/mediatek/mt8192: Add ddp driver
......................................................................

soc/mediatek/mt8192: Add ddp driver

Add ddp (display controller) driver that supports overlay, read/write
DMA, etc. The output goes to display interface DSI, DPI or DBI directly.

BUG=b:155713214
BRANCH=none
TEST=Boots correctly on asurada

Signed-off-by: Yongqiang Niu 
Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/ddp.c
M src/soc/mediatek/mt8192/include/soc/addressmap.h
A src/soc/mediatek/mt8192/include/soc/ddp.h
4 files changed, 482 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46577/6

Change in coreboot[master]: soc/mediatek/mt8192: Add ddp driver

[Yidi Lin (Code Review)]

Yidi Lin has uploaded a new patch set (#7) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: soc/mediatek/mt8192: Add ddp driver
......................................................................

soc/mediatek/mt8192: Add ddp driver

Add ddp (display controller) driver that supports overlay, read/write
DMA, etc. The output goes to display interface DSI, DPI or DBI directly.

BUG=b:155713214
BRANCH=none
TEST=Boots correctly on asurada

Signed-off-by: Yongqiang Niu 
Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/ddp.c
M src/soc/mediatek/mt8192/include/soc/addressmap.h
A src/soc/mediatek/mt8192/include/soc/ddp.h
4 files changed, 482 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46577/7

Change in coreboot[master]: soc/mediatek/mt8192: Add ddp driver

[Yidi Lin (Code Review)]

Yidi Lin has uploaded a new patch set (#8) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: soc/mediatek/mt8192: Add ddp driver
......................................................................

soc/mediatek/mt8192: Add ddp driver

Add ddp (display controller) driver that supports overlay, read/write
DMA, etc. The output goes to display interface DSI, DPI or DBI directly.

BUG=b:155713214
BRANCH=none
TEST=Boots correctly on asurada

Signed-off-by: Yongqiang Niu 
Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/ddp.c
M src/soc/mediatek/mt8192/include/soc/addressmap.h
A src/soc/mediatek/mt8192/include/soc/ddp.h
4 files changed, 482 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46577/8

Change in coreboot[master]: soc/mediatek/mt8192: Add ddp driver

[Yidi Lin (Code Review)]

Yidi Lin has uploaded a new patch set (#10) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: soc/mediatek/mt8192: Add ddp driver
......................................................................

soc/mediatek/mt8192: Add ddp driver

Add ddp (display controller) driver that supports overlay, read/write
DMA, etc. The output goes to display interface DSI, DPI or DBI directly.

BUG=b:155713214
BRANCH=none
TEST=Boots correctly on asurada

Signed-off-by: Yongqiang Niu 
Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/ddp.c
M src/soc/mediatek/mt8192/include/soc/addressmap.h
A src/soc/mediatek/mt8192/include/soc/ddp.h
4 files changed, 482 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46577/10

Change in coreboot[master]: soc/mediatek/mt8192: Add ddp driver

[Yidi Lin (Code Review)]

Yidi Lin has uploaded a new patch set (#11) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: soc/mediatek/mt8192: Add ddp driver
......................................................................

soc/mediatek/mt8192: Add ddp driver

Add ddp (display controller) driver that supports overlay, read/write
DMA, etc. The output goes to display interface DSI, DPI or DBI directly.

BUG=b:155713214
BRANCH=none
TEST=Boots correctly on asurada

Signed-off-by: Yongqiang Niu 
Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/ddp.c
M src/soc/mediatek/mt8192/include/soc/addressmap.h
A src/soc/mediatek/mt8192/include/soc/ddp.h
4 files changed, 482 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46577/11

Change in coreboot[master]: soc/mediatek/mt8192: Add ddp driver

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: soc/mediatek/mt8192: Add ddp driver
......................................................................

Patch Set 11:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46577/11/src/soc/mediatek/mt8192/dd... 
File src/soc/mediatek/mt8192/ddp.c:

https://review.coreboot.org/c/coreboot/+/46577/11/src/soc/mediatek/mt8192/dd... 
PS11, Line 45: static void ccorr_config(u32 width, u32 height)
             : {
             : 	struct disp_ccorr_regs *const regs = disp_ccorr;
             : 	int enable_relay = 0;
             : 
             : 	printk(BIOS_INFO, "%s\n", __func__);
             : 
             : 	write32(&regs->size, width << 16 | height);
             : 
             : 	if (enable_relay) {
             : 		setbits32(&regs->cfg, PQ_RELAY_MODE);
             : 		clrbits32(&regs->cfg, PQ_ENGINE_EN);
             : 	} else {
             : 		clrbits32(&regs->cfg, PQ_RELAY_MODE);
             : 		setbits32(&regs->cfg, PQ_ENGINE_EN);
             : 	}
             : 
             : 	write32(&regs->en, PQ_EN);
             : }
             : 
             : static void aal_config(u32 width, u32 height)
             : {
             : 	struct disp_aal_regs *const regs = disp_aal;
             : 	int enable_relay = 1;
             : 
             : 	printk(BIOS_INFO, "%s\n", __func__);
             : 
             : 	write32(&regs->size, width << 16 | height);
             : 	write32(&regs->output_size, width << 16 | height);
             : 
             : 	if (enable_relay) {
             : 		setbits32(&regs->cfg, PQ_RELAY_MODE);
             : 		clrbits32(&regs->cfg, PQ_ENGINE_EN);
             : 	} else {
             : 		clrbits32(&regs->cfg, PQ_RELAY_MODE);
             : 		setbits32(&regs->cfg, PQ_ENGINE_EN);
             : 	}
             : 
             : 	write32(&regs->en, PQ_EN);
             : }
             : 
             : static void gamma_config(u32 width, u32 height)
             : {
             : 	struct disp_gamma_regs *const regs = disp_gamma;
             : 	int enable_relay = 0;
             : 
             : 	printk(BIOS_INFO, "%s\n", __func__);
             : 
             : 	write32(&regs->size, width << 16 | height);
             : 
             : 	if (enable_relay)
             : 		setbits32(&regs->cfg, PQ_RELAY_MODE);
             : 	else
             : 		clrbits32(&regs->cfg, PQ_RELAY_MODE);
             : 
             : 	write32(&regs->en, PQ_EN);
             : }
             : 
             : static void postmask_config(u32 width, u32 height)
             : {
             : 	struct disp_postmask_regs *const regs = disp_postmask;
             : 	int enable_relay = 1;
             : 
             : 	printk(BIOS_INFO, "%s\n", __func__);
             : 
             : 	write32(&regs->size, width << 16 | height);
             : 
             : 	if (enable_relay)
             : 		setbits32(&regs->cfg, PQ_RELAY_MODE);
             : 	else
             : 		clrbits32(&regs->cfg, PQ_RELAY_MODE);
             : 
             : 	write32(&regs->en, PQ_EN);
             : }
             : 
             : static void dither_config(u32 width, u32 height)
             : {
             : 	struct disp_dither_regs *const regs = disp_dither;
             : 	int enable_relay = 1;
             : 
             : 	printk(BIOS_INFO, "%s\n", __func__);
             : 
             : 	write32(&regs->size, width << 16 | height);
             : 
             : 	if (enable_relay)
             : 		setbits32(&regs->cfg, PQ_RELAY_MODE);
             : 	else
             : 		clrbits32(&regs->cfg, PQ_RELAY_MODE);
             : 
             : 	write32(&regs->en, PQ_EN);
             : }
             : 
can we merge these just like the enable_pq in mt8183?

I know some bits have PQ_ENGINE_EN, and we can pass that as an extra arg:

static void enable_pq(struct disp_pq_regs *const regs, u32 width, u32 height,
                      int enable_relay, int has_engine_en)

Change in coreboot[master]: soc/mediatek/mt8192: Add ddp driver

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: soc/mediatek/mt8192: Add ddp driver
......................................................................

Patch Set 11:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46577/11/src/soc/mediatek/mt8192/dd... 
File src/soc/mediatek/mt8192/ddp.c:

https://review.coreboot.org/c/coreboot/+/46577/11/src/soc/mediatek/mt8192/dd... 
PS11, Line 45: static void ccorr_config(u32 width, u32 height)
             : {
             : 	struct disp_ccorr_regs *const regs = disp_ccorr;
             : 	int enable_relay = 0;
             : 
             : 	printk(BIOS_INFO, "%s\n", __func__);
             : 
             : 	write32(&regs->size, width << 16 | height);
             : 
             : 	if (enable_relay) {
             : 		setbits32(&regs->cfg, PQ_RELAY_MODE);
             : 		clrbits32(&regs->cfg, PQ_ENGINE_EN);
             : 	} else {
             : 		clrbits32(&regs->cfg, PQ_RELAY_MODE);
             : 		setbits32(&regs->cfg, PQ_ENGINE_EN);
             : 	}
             : 
             : 	write32(&regs->en, PQ_EN);
             : }
             : 
             : static void aal_config(u32 width, u32 height)
             : {
             : 	struct disp_aal_regs *const regs = disp_aal;
             : 	int enable_relay = 1;
             : 
             : 	printk(BIOS_INFO, "%s\n", __func__);
             : 
             : 	write32(&regs->size, width << 16 | height);
             : 	write32(&regs->output_size, width << 16 | height);
             : 
             : 	if (enable_relay) {
             : 		setbits32(&regs->cfg, PQ_RELAY_MODE);
             : 		clrbits32(&regs->cfg, PQ_ENGINE_EN);
             : 	} else {
             : 		clrbits32(&regs->cfg, PQ_RELAY_MODE);
             : 		setbits32(&regs->cfg, PQ_ENGINE_EN);
             : 	}
             : 
             : 	write32(&regs->en, PQ_EN);
             : }
             : 
             : static void gamma_config(u32 width, u32 height)
             : {
             : 	struct disp_gamma_regs *const regs = disp_gamma;
             : 	int enable_relay = 0;
             : 
             : 	printk(BIOS_INFO, "%s\n", __func__);
             : 
             : 	write32(&regs->size, width << 16 | height);
             : 
             : 	if (enable_relay)
             : 		setbits32(&regs->cfg, PQ_RELAY_MODE);
             : 	else
             : 		clrbits32(&regs->cfg, PQ_RELAY_MODE);
             : 
             : 	write32(&regs->en, PQ_EN);
             : }
             : 
             : static void postmask_config(u32 width, u32 height)
             : {
             : 	struct disp_postmask_regs *const regs = disp_postmask;
             : 	int enable_relay = 1;
             : 
             : 	printk(BIOS_INFO, "%s\n", __func__);
             : 
             : 	write32(&regs->size, width << 16 | height);
             : 
             : 	if (enable_relay)
             : 		setbits32(&regs->cfg, PQ_RELAY_MODE);
             : 	else
             : 		clrbits32(&regs->cfg, PQ_RELAY_MODE);
             : 
             : 	write32(&regs->en, PQ_EN);
             : }
             : 
             : static void dither_config(u32 width, u32 height)
             : {
             : 	struct disp_dither_regs *const regs = disp_dither;
             : 	int enable_relay = 1;
             : 
             : 	printk(BIOS_INFO, "%s\n", __func__);
             : 
             : 	write32(&regs->size, width << 16 | height);
             : 
             : 	if (enable_relay)
             : 		setbits32(&regs->cfg, PQ_RELAY_MODE);
             : 	else
             : 		clrbits32(&regs->cfg, PQ_RELAY_MODE);
             : 
             : 	write32(&regs->en, PQ_EN);
             : }
             :
> can we merge these just like the enable_pq in mt8183? […]

what about

struct disp_common_regs {
        u32 en;
        u32 reset;
        u32 inten;
        u32 intsta;
        union {
                struct {
                        u32 status;
                        u32 reserved0[3];
                };
                u32 reserved1[4];
        };
        u32 cfg;
        u32 reserved2[3];
        u32 size;
};

struct disp_ccorr_regs {
    struct disp_common_regs common;
    u32 reserved2[27];
    u32 shadow;
};

struct disp_aal_regs {
    struct disp_common_regs common;
    u32 reserved2[47];
    u32 shadow;
    u32 reserved3[249];
    u32 output_size;
};

...

then pass common registers to enable_pq() ?

Change in coreboot[master]: soc/mediatek/mt8192: Add ddp driver

[Yidi Lin (Code Review)]

Yidi Lin has uploaded a new patch set (#12) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: soc/mediatek/mt8192: Add ddp driver
......................................................................

soc/mediatek/mt8192: Add ddp driver

Add ddp (display controller) driver that supports overlay, read/write
DMA, etc. The output goes to display interface DSI, DPI or DBI directly.

BUG=b:155713214
BRANCH=none
TEST=Boots correctly on asurada

Signed-off-by: Yongqiang Niu 
Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/ddp.c
M src/soc/mediatek/mt8192/include/soc/addressmap.h
A src/soc/mediatek/mt8192/include/soc/ddp.h
4 files changed, 482 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46577/12

Change in coreboot[master]: soc/mediatek/mt8192: Add ddp driver

[Yidi Lin (Code Review)]

Yidi Lin has uploaded a new patch set (#13) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: soc/mediatek/mt8192: Add ddp driver
......................................................................

soc/mediatek/mt8192: Add ddp driver

Add ddp (display controller) driver that supports overlay, read/write
DMA, etc. The output goes to display interface DSI, DPI or DBI directly.

BUG=b:155713214
BRANCH=none
TEST=Boots correctly on asurada

Signed-off-by: Yongqiang Niu 
Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/ddp.c
M src/soc/mediatek/mt8192/include/soc/addressmap.h
A src/soc/mediatek/mt8192/include/soc/ddp.h
4 files changed, 482 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46577/13

Change in coreboot[master]: soc/mediatek/mt8192: Add ddp driver

[Yidi Lin (Code Review)]

Yidi Lin has uploaded a new patch set (#15) to the change originally created by yongqiang niu. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: soc/mediatek/mt8192: Add ddp driver
......................................................................

soc/mediatek/mt8192: Add ddp driver

Add ddp (display controller) driver that supports overlay, read/write
DMA, etc. The output goes to display interface DSI, DPI or DBI directly.

BUG=b:155713214
BRANCH=none
TEST=Boots correctly on asurada

Signed-off-by: Yongqiang Niu 
Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/ddp.c
M src/soc/mediatek/mt8192/include/soc/addressmap.h
A src/soc/mediatek/mt8192/include/soc/ddp.h
4 files changed, 482 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46577/15

Change in coreboot[master]: soc/mediatek/mt8192: Add ddp driver

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: soc/mediatek/mt8192: Add ddp driver
......................................................................

Patch Set 15: Code-Review+2

Change in coreboot[master]: soc/mediatek/mt8192: Add ddp driver

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: soc/mediatek/mt8192: Add ddp driver
......................................................................

Patch Set 16:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46577/11/src/soc/mediatek/mt8192/dd... 
File src/soc/mediatek/mt8192/ddp.c:

https://review.coreboot.org/c/coreboot/+/46577/11/src/soc/mediatek/mt8192/dd... 
PS11, Line 45: static void ccorr_config(u32 width, u32 height)
             : {
             : 	struct disp_ccorr_regs *const regs = disp_ccorr;
             : 	int enable_relay = 0;
             : 
             : 	printk(BIOS_INFO, "%s\n", __func__);
             : 
             : 	write32(&regs->size, width << 16 | height);
             : 
             : 	if (enable_relay) {
             : 		setbits32(&regs->cfg, PQ_RELAY_MODE);
             : 		clrbits32(&regs->cfg, PQ_ENGINE_EN);
             : 	} else {
             : 		clrbits32(&regs->cfg, PQ_RELAY_MODE);
             : 		setbits32(&regs->cfg, PQ_ENGINE_EN);
             : 	}
             : 
             : 	write32(&regs->en, PQ_EN);
             : }
             : 
             : static void aal_config(u32 width, u32 height)
             : {
             : 	struct disp_aal_regs *const regs = disp_aal;
             : 	int enable_relay = 1;
             : 
             : 	printk(BIOS_INFO, "%s\n", __func__);
             : 
             : 	write32(&regs->size, width << 16 | height);
             : 	write32(&regs->output_size, width << 16 | height);
             : 
             : 	if (enable_relay) {
             : 		setbits32(&regs->cfg, PQ_RELAY_MODE);
             : 		clrbits32(&regs->cfg, PQ_ENGINE_EN);
             : 	} else {
             : 		clrbits32(&regs->cfg, PQ_RELAY_MODE);
             : 		setbits32(&regs->cfg, PQ_ENGINE_EN);
             : 	}
             : 
             : 	write32(&regs->en, PQ_EN);
             : }
             : 
             : static void gamma_config(u32 width, u32 height)
             : {
             : 	struct disp_gamma_regs *const regs = disp_gamma;
             : 	int enable_relay = 0;
             : 
             : 	printk(BIOS_INFO, "%s\n", __func__);
             : 
             : 	write32(&regs->size, width << 16 | height);
             : 
             : 	if (enable_relay)
             : 		setbits32(&regs->cfg, PQ_RELAY_MODE);
             : 	else
             : 		clrbits32(&regs->cfg, PQ_RELAY_MODE);
             : 
             : 	write32(&regs->en, PQ_EN);
             : }
             : 
             : static void postmask_config(u32 width, u32 height)
             : {
             : 	struct disp_postmask_regs *const regs = disp_postmask;
             : 	int enable_relay = 1;
             : 
             : 	printk(BIOS_INFO, "%s\n", __func__);
             : 
             : 	write32(&regs->size, width << 16 | height);
             : 
             : 	if (enable_relay)
             : 		setbits32(&regs->cfg, PQ_RELAY_MODE);
             : 	else
             : 		clrbits32(&regs->cfg, PQ_RELAY_MODE);
             : 
             : 	write32(&regs->en, PQ_EN);
             : }
             : 
             : static void dither_config(u32 width, u32 height)
             : {
             : 	struct disp_dither_regs *const regs = disp_dither;
             : 	int enable_relay = 1;
             : 
             : 	printk(BIOS_INFO, "%s\n", __func__);
             : 
             : 	write32(&regs->size, width << 16 | height);
             : 
             : 	if (enable_relay)
             : 		setbits32(&regs->cfg, PQ_RELAY_MODE);
             : 	else
             : 		clrbits32(&regs->cfg, PQ_RELAY_MODE);
             : 
             : 	write32(&regs->en, PQ_EN);
             : }
             :
> what about […]

I'm fine either way, but anyway this is not super urgent.

Change in coreboot[master]: soc/mediatek/mt8192: Add ddp driver

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: soc/mediatek/mt8192: Add ddp driver
......................................................................

Patch Set 16:

conflict, please rebase.

Change in coreboot[master]: soc/mediatek/mt8192: Add ddp driver

[Yidi Lin (Code Review)]

Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: soc/mediatek/mt8192: Add ddp driver
......................................................................

Patch Set 17:
> Patch Set 16:
>
> conflict, please rebase.

done

Change in coreboot[master]: soc/mediatek/mt8192: Add ddp driver

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46577 )

Change subject: soc/mediatek/mt8192: Add ddp driver
......................................................................

soc/mediatek/mt8192: Add ddp driver

Add ddp (display controller) driver that supports overlay, read/write
DMA, etc. The output goes to display interface DSI, DPI or DBI directly.

BUG=b:155713214
BRANCH=none
TEST=Boots correctly on asurada

Signed-off-by: Yongqiang Niu 
Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46577
Reviewed-by: Hung-Te Lin 
Tested-by: build bot (Jenkins) 
---
M src/soc/mediatek/mt8192/Makefile.inc
A src/soc/mediatek/mt8192/ddp.c
M src/soc/mediatek/mt8192/include/soc/addressmap.h
A src/soc/mediatek/mt8192/include/soc/ddp.h
4 files changed, 482 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Hung-Te Lin: Looks good to me, approved

diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 157ada4..2379966 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -38,6 +38,7 @@
 romstage-y += mt6359p.c

ramstage-y += ../common/auxadc.c
+ramstage-y += ../common/ddp.c ddp.c
 ramstage-y += dpm.c
 ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
 ramstage-y += flash_controller.c
diff --git a/src/soc/mediatek/mt8192/ddp.c b/src/soc/mediatek/mt8192/ddp.c
new file mode 100644
index 0000000..f03a902
--- /dev/null
+++ b/src/soc/mediatek/mt8192/ddp.c
@@ -0,0 +1,198 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <edid.h>
+#include <soc/addressmap.h>
+#include <soc/ddp.h>
+
+static void disp_config_main_path_connection(void)
+{
+	/* ovl0->ovl0_2l */
+	write32(&mmsys_cfg->mmsys_ovl_mout_en,
+		(DISP_OVL0_GO_BG | DISP_OVL0_2L_GO_BLEND));
+	write32(&mmsys_cfg->ovl0_2l_mout_en, OVL0_MOUT_EN_DISP_RDMA0);
+	write32(&mmsys_cfg->rdma0_sel_in, RDMA0_SEL_IN_OVL0_2L);
+	write32(&mmsys_cfg->rdma0_sout_sel, RDMA0_SOUT_COLOR0);
+	write32(&mmsys_cfg->ccorr0_sout_sel, CCORR0_SOUT_AAL0);
+	write32(&mmsys_cfg->aal0_sel_in, AAL0_SEL_IN_CCORR0);
+	write32(&mmsys_cfg->dither0_mout_en, DITHER0_MOUT_DSI0);
+	write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0);
+}
+
+static void disp_config_main_path_mutex(void)
+{
+	write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH);
+
+	/* Clock source from DSI0 */
+	write32(&disp_mutex->mutex[0].ctl,
+		MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6));
+	write32(&disp_mutex->mutex[0].en, BIT(0));
+}
+
+static void ovl_bgclr_in_sel(u32 idx)
+{
+	setbits32(&disp_ovl[idx]->datapath_con, BIT(2));
+}
+
+static void ovl_layer_smi_id_en(u32 idx)
+{
+	printk(BIOS_INFO, "%s\n", __func__);
+
+	setbits32(&disp_ovl[idx]->datapath_con, BIT(0));
+}
+
+static void ccorr_config(u32 width, u32 height)
+{
+	struct disp_ccorr_regs *const regs = disp_ccorr;
+	int enable_relay = 0;
+
+	printk(BIOS_INFO, "%s\n", __func__);
+
+	write32(&regs->size, width << 16 | height);
+
+	if (enable_relay) {
+		setbits32(&regs->cfg, PQ_RELAY_MODE);
+		clrbits32(&regs->cfg, PQ_ENGINE_EN);
+	} else {
+		clrbits32(&regs->cfg, PQ_RELAY_MODE);
+		setbits32(&regs->cfg, PQ_ENGINE_EN);
+	}
+
+	write32(&regs->en, PQ_EN);
+}
+
+static void aal_config(u32 width, u32 height)
+{
+	struct disp_aal_regs *const regs = disp_aal;
+	int enable_relay = 1;
+
+	printk(BIOS_INFO, "%s\n", __func__);
+
+	write32(&regs->size, width << 16 | height);
+	write32(&regs->output_size, width << 16 | height);
+
+	if (enable_relay) {
+		setbits32(&regs->cfg, PQ_RELAY_MODE);
+		clrbits32(&regs->cfg, PQ_ENGINE_EN);
+	} else {
+		clrbits32(&regs->cfg, PQ_RELAY_MODE);
+		setbits32(&regs->cfg, PQ_ENGINE_EN);
+	}
+
+	write32(&regs->en, PQ_EN);
+}
+
+static void gamma_config(u32 width, u32 height)
+{
+	struct disp_gamma_regs *const regs = disp_gamma;
+	int enable_relay = 0;
+
+	printk(BIOS_INFO, "%s\n", __func__);
+
+	write32(&regs->size, width << 16 | height);
+
+	if (enable_relay)
+		setbits32(&regs->cfg, PQ_RELAY_MODE);
+	else
+		clrbits32(&regs->cfg, PQ_RELAY_MODE);
+
+	write32(&regs->en, PQ_EN);
+}
+
+static void postmask_config(u32 width, u32 height)
+{
+	struct disp_postmask_regs *const regs = disp_postmask;
+	int enable_relay = 1;
+
+	printk(BIOS_INFO, "%s\n", __func__);
+
+	write32(&regs->size, width << 16 | height);
+
+	if (enable_relay)
+		setbits32(&regs->cfg, PQ_RELAY_MODE);
+	else
+		clrbits32(&regs->cfg, PQ_RELAY_MODE);
+
+	write32(&regs->en, PQ_EN);
+}
+
+static void dither_config(u32 width, u32 height)
+{
+	struct disp_dither_regs *const regs = disp_dither;
+	int enable_relay = 1;
+
+	printk(BIOS_INFO, "%s\n", __func__);
+
+	write32(&regs->size, width << 16 | height);
+
+	if (enable_relay)
+		setbits32(&regs->cfg, PQ_RELAY_MODE);
+	else
+		clrbits32(&regs->cfg, PQ_RELAY_MODE);
+
+	write32(&regs->en, PQ_EN);
+}
+
+
+static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh)
+{
+	u32 idx = 0;
+	u32 pixel_clk = width * height * vrefresh;
+
+	printk(BIOS_INFO, "%s\n", __func__);
+
+	for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) {
+		ovl_set_roi(idx, width, height, idx ? 0 : 0xff0000ff);
+		ovl_layer_smi_id_en(idx);
+	}
+
+	rdma_config(width, height, pixel_clk, 5 * KiB);
+	color_start(width, height);
+	ccorr_config(width, height);
+	aal_config(width, height);
+	gamma_config(width, height);
+	postmask_config(width, height);
+	dither_config(width, height);
+	disp_config_main_path_connection();
+	disp_config_main_path_mutex();
+}
+
+static void disp_clock_on(void)
+{
+	clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL);
+
+	clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_ALL);
+
+	clrbits32(&mmsys_cfg->mmsys_cg_con2, CG_CON2_DISP_ALL);
+}
+
+void mtk_ddp_init(void)
+{
+	disp_clock_on();
+	/* Turn off M4U port. */
+	write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0);
+}
+
+void mtk_ddp_mode_set(const struct edid *edid)
+{
+	u32 fmt = OVL_INFMT_RGBA8888;
+	u32 bpp = edid->framebuffer_bits_per_pixel / 8;
+	u32 width = edid->mode.ha;
+	u32 height = edid->mode.va;
+	u32 vrefresh = edid->mode.refresh;
+
+	printk(BIOS_INFO, "%s display resolution: %dx%d@%d bpp %d\n",
+		__func__, width, height, vrefresh, bpp);
+
+	if (!vrefresh) {
+		vrefresh = 60;
+		printk(BIOS_INFO, "%s invalid vrefresh %d\n",
+		__func__, vrefresh);
+	}
+
+	main_disp_path_setup(width, height, vrefresh);
+	rdma_start();
+	ovl_layer_config(fmt, bpp, width, height);
+	ovl_bgclr_in_sel(1);
+}
diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h
index 6cee8f3..ab3bd75 100644
--- a/src/soc/mediatek/mt8192/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h
@@ -60,6 +60,19 @@
    IOCFG_TL_BASE		= IO_PHYS + 0x01F30000,
    MSDC0_TOP_BASE		= IO_PHYS + 0x01F50000,
    MSDC0_BASE		= IO_PHYS + 0x01F60000,
+	MMSYS_BASE		= IO_PHYS + 0x04000000,
+	DISP_MUTEX_BASE		= IO_PHYS + 0x04001000,
+	SMI_BASE		= IO_PHYS + 0x04002000,
+	SMI_LARB0		= IO_PHYS + 0x04003000,
+	DISP_OVL0_BASE		= IO_PHYS + 0x04005000, /* ovl0 */
+	DISP_OVL1_BASE		= IO_PHYS + 0x04006000, /* ovl0_2l */
+	DISP_RDMA0_BASE		= IO_PHYS + 0x04007000,
+	DISP_COLOR0_BASE	= IO_PHYS + 0x04009000,
+	DISP_CCORR0_BASE	= IO_PHYS + 0x0400A000,
+	DISP_AAL0_BASE		= IO_PHYS + 0x0400B000,
+	DISP_GAMMA0_BASE	= IO_PHYS + 0x0400C000,
+	DISP_POSTMASK0_BASE	= IO_PHYS + 0x0400D000,
+	DISP_DITHER0_BASE	= IO_PHYS + 0x0400E000,
    DSI0_BASE		= IO_PHYS + 0x04010000,
 };

diff --git a/src/soc/mediatek/mt8192/include/soc/ddp.h b/src/soc/mediatek/mt8192/include/soc/ddp.h
new file mode 100644
index 0000000..dba97f0
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/ddp.h
@@ -0,0 +1,270 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MT8183_SOC_DDP_H_
+#define _MT8183_SOC_DDP_H_
+
+#include <soc/addressmap.h>
+#include <soc/ddp_common.h>
+#include <types.h>
+
+#define MAIN_PATH_OVL_NR 2
+
+struct mmsys_cfg_regs {
+	u32 reserved_0x000[64];		/* 0x000 */
+	u32 mmsys_cg_con0;		/* 0x100 */
+	u32 mmsys_cg_set0;		/* 0x104 */
+	u32 mmsys_cg_clr0;		/* 0x108 */
+	u32 reserved_0x10C;		/* 0x10C */
+	u32 mmsys_cg_con1;		/* 0x110 */
+	u32 mmsys_cg_set1;		/* 0x114 */
+	u32 mmsys_cg_clr1;		/* 0x118 */
+	u32 reserved_0x11C[33];		/* 0x11C */
+	u32 mmsys_cg_con2;		/* 0x1A0 */
+	u32 mmsys_cg_set2;		/* 0x1A4 */
+	u32 mmsys_cg_clr2;		/* 0x1A8 */
+	u32 reserved_0x1AC[853];	/* 0x1AC */
+	u32 reserved_0xF00;		/* 0xF00 */
+	u32 mmsys_ovl_mout_en;		/* 0xF04 */
+	u32 reserved_0xF08;		/* 0xF08 */
+	u32 reserved_0xF0C;		/* 0xF0C */
+	u32 reserved_0xF10;		/* 0xF10 */
+	u32 reserved_0xF14;		/* 0xF14 */
+	u32 ovl0_2l_mout_en;		/* 0xF18 */
+	u32 ovl0_mout_en;		/* 0xF1C */
+	u32 reserved_0xF20;		/* 0xF20 */
+	u32 reserved_0xF24;		/* 0xF24 */
+	u32 reserved_0xF28;		/* 0xF28 */
+	u32 rdma0_sel_in;		/* 0xF2C */
+	u32 rdma0_sout_sel;		/* 0xF30 */
+	u32 ccorr0_sout_sel;		/* 0xF34 */
+	u32 aal0_sel_in;		/* 0xF38 */
+	u32 dither0_mout_en;		/* 0xF3C*/
+	u32 dsi0_sel_in;		/* 0xF40*/
+};
+
+check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100);
+check_member(mmsys_cfg_regs, mmsys_cg_con1, 0x110);
+check_member(mmsys_cfg_regs, mmsys_cg_con2, 0x1A0);
+check_member(mmsys_cfg_regs, mmsys_ovl_mout_en, 0xF04);
+check_member(mmsys_cfg_regs, ovl0_2l_mout_en, 0xF18);
+check_member(mmsys_cfg_regs, dsi0_sel_in, 0xF40);
+static struct mmsys_cfg_regs *const mmsys_cfg =
+	(void *)MMSYS_BASE;
+
+
+/* DISP_REG_CONFIG_MMSYS_CG_CON0
+   Configures free-run clock gating 0
+	0: Enable clock
+	1: Clock gating  */
+enum {
+	CG_CON0_DISP_MUTEX0	= BIT(0),
+	CG_CON0_DISPSYS_CONFIG	= BIT(1),
+	CG_CON0_DISP_OVL0	= BIT(2),
+	CG_CON0_DISP_RDMA0	= BIT(3),
+	CG_CON0_DISP_OVL0_2L	= BIT(4),
+	CG_CON0_DISP_AAL0	= BIT(8),
+	CG_CON0_DISP_CCORR0	= BIT(9),
+	CG_CON0_DISP_DITHER0	= BIT(10),
+	CG_CON0_SMI_INFRA	= BIT(11),
+	CG_CON0_DISP_GAMMA0	= BIT(12),
+	CG_CON0_DISP_POSTMASK0	= BIT(13),
+	CG_CON0_DISP_DSI0	= BIT(15),
+	CG_CON0_DISP_COLOR0	= BIT(16),
+	CG_CON0_SMI_COMMON	= BIT(17),
+
+	CG_CON0_SMI_GALS	= BIT(27),
+	CG_CON0_DISP_ALL	= CG_CON0_SMI_INFRA |
+				  CG_CON0_SMI_COMMON |
+				  CG_CON0_SMI_GALS |
+				  CG_CON0_DISP_MUTEX0 |
+				  CG_CON0_DISPSYS_CONFIG |
+				  CG_CON0_DISP_OVL0 |
+				  CG_CON0_DISP_RDMA0 |
+				  CG_CON0_DISP_OVL0_2L |
+				  CG_CON0_DISP_AAL0 |
+				  CG_CON0_DISP_CCORR0 |
+				  CG_CON0_DISP_DITHER0 |
+				  CG_CON0_DISP_GAMMA0 |
+				  CG_CON0_DISP_POSTMASK0 |
+				  CG_CON0_DISP_DSI0 |
+				  CG_CON0_DISP_COLOR0,
+	CG_CON0_ALL		= 0xffffffff
+};
+
+/* DISP_REG_CONFIG_MMSYS_CG_CON1
+   Configures free-run clock gating 1
+	0: Enable clock
+	1: Clock gating */
+enum {
+	CG_CON1_SMI_IOMMU	= BIT(0),
+	CG_CON1_DISP_ALL	= CG_CON1_SMI_IOMMU,
+	CG_CON1_ALL		= 0xffffffff
+};
+
+enum {
+	CG_CON2_DSI_DSI0	= BIT(0),
+	CG_CON2_DPI_DPI0	= BIT(8),
+	CG_CON2_MM_26MHZ	= BIT(24),
+	CG_CON2_DISP_ALL	= CG_CON2_DSI_DSI0 |
+				  CG_CON2_MM_26MHZ,
+	CG_CON2_ALL		= 0xffffffff
+};
+
+
+enum {
+	DISP_OVL0_GO_BLEND	= BIT(0),
+	DISP_OVL0_GO_BG		= BIT(1),
+	DISP_OVL0_2L_GO_BLEND	= BIT(2),
+	DISP_OVL0_2L_GO_BG	= BIT(3),
+	OVL0_MOUT_EN_DISP_RDMA0	= BIT(0),
+	DITHER0_MOUT_DSI0	= BIT(0),
+};
+
+enum {
+	RDMA0_SEL_IN_OVL0_2L	= 0x3,
+	RDMA0_SOUT_COLOR0	= 0x1,
+	CCORR0_SOUT_AAL0	= 0x1,
+	AAL0_SEL_IN_CCORR0	= 0x1,
+	DSI0_SEL_IN_DITHER0	= 0x1,
+};
+
+struct disp_mutex_regs {
+	u32 inten;
+	u32 intsta;
+	u32 reserved0[6];
+	struct {
+		u32 en;
+		u32 dummy;
+		u32 rst;
+		u32 ctl;
+		u32 mod;
+		u32 reserved[3];
+	} mutex[12];
+};
+
+static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE;
+
+enum {
+	MUTEX_MOD_DISP_OVL0		= BIT(0),
+	MUTEX_MOD_DISP_OVL0_2L		= BIT(1),
+	MUTEX_MOD_DISP_RDMA0		= BIT(2),
+	MUTEX_MOD_DISP_COLOR0		= BIT(4),
+	MUTEX_MOD_DISP_CCORR0		= BIT(5),
+	MUTEX_MOD_DISP_AAL0		= BIT(6),
+	MUTEX_MOD_DISP_GAMMA0		= BIT(7),
+	MUTEX_MOD_DISP_POSTMASK0	= BIT(8),
+	MUTEX_MOD_DISP_DITHER0		= BIT(9),
+	MUTEX_MOD_MAIN_PATH		= MUTEX_MOD_DISP_OVL0 |
+					  MUTEX_MOD_DISP_OVL0_2L |
+					  MUTEX_MOD_DISP_RDMA0 |
+					  MUTEX_MOD_DISP_COLOR0 |
+					  MUTEX_MOD_DISP_CCORR0 |
+					  MUTEX_MOD_DISP_AAL0 |
+					  MUTEX_MOD_DISP_GAMMA0 |
+					  MUTEX_MOD_DISP_POSTMASK0 |
+					  MUTEX_MOD_DISP_DITHER0,
+};
+
+enum {
+	MUTEX_SOF_SINGLE_MODE = 0,
+	MUTEX_SOF_DSI0 = 1,
+	MUTEX_SOF_DPI0 = 2,
+};
+
+struct disp_ccorr_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 status;
+	u32 reserved0[3];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+	u32 reserved2[27];
+	u32 shadow;
+};
+check_member(disp_ccorr_regs, shadow, 0xA0);
+
+struct disp_gamma_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 status;
+	u32 reserved0[3];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+};
+check_member(disp_gamma_regs, size, 0x30);
+
+struct disp_aal_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 status;
+	u32 reserved0[3];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+	u32 reserved2[47];
+	u32 shadow;
+	u32 reserved3[249];
+	u32 output_size;
+};
+check_member(disp_aal_regs, shadow, 0xF0);
+check_member(disp_aal_regs, output_size, 0x4D8);
+
+struct disp_postmask_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 reserved0[4];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+};
+check_member(disp_postmask_regs, size, 0x30);
+
+struct disp_dither_regs {
+	u32 en;
+	u32 reset;
+	u32 inten;
+	u32 intsta;
+	u32 status;
+	u32 reserved0[3];
+	u32 cfg;
+	u32 reserved1[3];
+	u32 size;
+	u32 reserved2[51];
+	u32 shadow;
+};
+check_member(disp_dither_regs, shadow, 0x100);
+
+enum {
+	PQ_EN		= BIT(0),
+	PQ_RELAY_MODE	= BIT(0),
+	PQ_ENGINE_EN	= BIT(1),
+};
+
+static struct disp_ccorr_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE;
+
+static struct disp_aal_regs *const disp_aal = (void *)DISP_AAL0_BASE;
+
+static struct disp_gamma_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE;
+
+static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE;
+
+static struct disp_postmask_regs *const disp_postmask = (void *)DISP_POSTMASK0_BASE;
+
+enum {
+	SMI_LARB_PORT_L0_OVL_RDMA0	= 0x388,
+};
+
+void mtk_ddp_init(void);
+void mtk_ddp_mode_set(const struct edid *edid);
+
+#endif