coreboot-gerrit December 2020

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Change in coreboot[master]: mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P)
by Michael Niewöhner (Code Review) 11 Dec '20

11 Dec '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P) ...................................................................... Patch Set 10: (11 comments) https://review.coreboot.org/c/coreboot/+/38978/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38978/7//COMMIT_MSG@37 PS7, Line 37: - Touchpad. Hangs off either EC or some I2C controller and needs ACPI. > Well, it's connected to the EC's PS/2 port 3 (according to the kb9012 ds). […] Done https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… PS5, Line 223: register "SendVrMbxCmd" = "2" > What I could find out: There are issues with (some) IMVP8 controllers. […] Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 37: register "SataTestMode" = "1" > Yes, I do want that. Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 40: register "SataPortsDevSlp[0]" = "0" : register "SataPortsDevSlp[1]" = "0" : > schematics say nooooo ;) Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 42: SataSpeedLimit" = "3" > speed 3 (also matches 0) is the default already Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 86: register "usb2_ports[3]" = "USB2_PORT_EMPTY" # N/C > not required anymore; drop; see CB:45106 Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 93: register "usb3_ports[1]" = "USB3_PORT_EMPTY" # N/C : register "usb3_ports[2]" = "USB3_PORT_EMPTY" # N/C : register "usb3_ports[3]" = "USB3_PORT_EMPTY" # N/C : > not required anymore; drop them; see CB:45106 Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 108: device pci 04.0 off end # CPU Thermal Subsystem > it's not about EC ACPI and it's not only about DPTF. […] Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/gpio.c: https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 7: #define PAD_CFG_NF_BUF_TRIG(a, b, c, d, e, f) PAD_CFG_NF(a, b, c, d) > I'd rather re-do the whole file. Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 144: _PAD_CFG_STRUCT(GPP_B3, : PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | : PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | : PAD_BUF(TX_DISABLE), : PAD_PULL(NONE)), : > I'll re-do the whole file Done https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/romstage.c: https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 32: /* These settings are most likely useless if using a release build of FSP */ : mem_cfg->PcdDebugInterfaceFlags = 2; /* 2: Enable UART */ : mem_cfg->PcdSerialIoUartNumber = 2; /* 2: Use UART #2 */ : mem_cfg->PcdSerialDebugBaudRate = 7; /* 7: 115200 baud */ : mem_cfg->PcdSerialDebugLevel = 3; /* 3: Log <= Info */ : > well, that's all fsp defaults (except the TH bit in PcdSerialIoUartNumber, which doesn't do anything […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 10 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Fri, 11 Dec 2020 19:29:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P)
by build bot (Jenkins) (Code Review) 11 Dec '20

11 Dec '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P) ...................................................................... Patch Set 10: (3 comments) https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-57… File src/mainboard/acer/es1-572/gpio.c: https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-57… PS10, Line 131: PAD_CFG_GPI_SCI_LOW(GPP_E16, UP_20K, DEEP, LEVEL),/* GPP_E16 / EC_SCI# */ // TODO SMI? smihandler line over 96 characters https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-57… File src/mainboard/acer/es1-572/romstage.c: https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-57… PS10, Line 20: FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV) https://review.coreboot.org/c/coreboot/+/38978/10/src/mainboard/acer/es1-57… PS10, Line 21: FSP_M_TEST_CONFIG *const test_cfg = &mupd->FspmTestConfig; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 10 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Fri, 11 Dec 2020 19:28:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P)
by Michael Niewöhner (Code Review) 11 Dec '20

11 Dec '20

Michael Niewöhner has uploaded a new patch set (#10) to the change originally created by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P) ...................................................................... mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P) Both the Acer Aspire ES1-572 and the Acer Extensa 2540 use the same mainboard, the Compal LA-E061P. This change adds support for it. See Documentation/mainboard/acer/aspire_es1-572_and_extensa_2540.md for what is working and what not. Needs test: - Battery - Touchpad (seems to work but hangs often.. maybe my tp is defective) - Card reader - Lid - Audio Todo: - make s3 work (again) - make LID ACPI code work - make ec acpi code actually work (currently just dropped in vendor code and applied some replacements like One -> 1 and so on) Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- A Documentation/mainboard/acer/aspire_es1-572_and_extensa_2540.md A Documentation/mainboard/acer/la-e061p_flash_diode_1.jpg A Documentation/mainboard/acer/la-e061p_flash_diode_2.jpg A Documentation/mainboard/acer/la-e061p_flash_diode_3.jpg A Documentation/mainboard/acer/la-e061p_uart.jpg M Documentation/mainboard/index.md A src/mainboard/acer/es1-572/Kconfig A src/mainboard/acer/es1-572/Kconfig.name A src/mainboard/acer/es1-572/Makefile.inc A src/mainboard/acer/es1-572/acpi/ec.asl A src/mainboard/acer/es1-572/acpi/lid.asl A src/mainboard/acer/es1-572/acpi/mainboard.asl A src/mainboard/acer/es1-572/acpi/superio.asl A src/mainboard/acer/es1-572/board_info.txt A src/mainboard/acer/es1-572/bootblock.c A src/mainboard/acer/es1-572/cmos.default A src/mainboard/acer/es1-572/cmos.layout A src/mainboard/acer/es1-572/data.vbt A src/mainboard/acer/es1-572/devicetree.cb A src/mainboard/acer/es1-572/dsdt.asl A src/mainboard/acer/es1-572/gma-mainboard.ads A src/mainboard/acer/es1-572/gpio.c A src/mainboard/acer/es1-572/gpio_early.c A src/mainboard/acer/es1-572/hda_verb.c A src/mainboard/acer/es1-572/include/mainboard/gpio.h A src/mainboard/acer/es1-572/ramstage.c A src/mainboard/acer/es1-572/romstage.c 27 files changed, 1,849 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/38978/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 10 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/fmap: Add null parameters handling
by Name of user not set (Code Review) 11 Dec '20

11 Dec '20

Name of user not set #1003143 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48531 ) Change subject: lib/fmap: Add null parameters handling ...................................................................... lib/fmap: Add null parameters handling Prevent segmentation fault when passing NULL as parameters. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ie712d040b1c2383dcc8884e5f779c3591ccf0163 --- M src/lib/fmap.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/48531/1 diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 2abe138..418e715 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -164,6 +164,9 @@ struct region_device fmrd; size_t offset; + if (name == NULL || ar == NULL) + return -1; + if (find_fmap_directory(&fmrd)) return -1; @@ -206,6 +209,9 @@ struct region_device fmrd; size_t offset; + if (name == NULL || ar == NULL) + return -1; + if (find_fmap_directory(&fmrd)) return -1; -- To view, visit https://review.coreboot.org/c/coreboot/+/48531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie712d040b1c2383dcc8884e5f779c3591ccf0163 Gerrit-Change-Number: 48531 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003143 Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11ssm-f: disable unconnected and unused/strap-only pads
by Michael Niewöhner (Code Review) 11 Dec '20

11 Dec '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48100 ) Change subject: mb/supermicro/x11ssm-f: disable unconnected and unused/strap-only pads ...................................................................... mb/supermicro/x11ssm-f: disable unconnected and unused/strap-only pads There is a whole bunch of pads being configured by the vendor firmware that are either unconnected due to unpopulated resistor pads, only connected to test points for vendor debugging purposes or just used as strap. Configure them as NC with an appropriate pull to disable the RX/TX functions. The pads have been determined by dissecting a dead board. This patch has been tested thoughroughly on a machine, normally used productive, to see if any issues arise. No problems occurred at all. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I06b942e3182469f87e41914c893e5b485ccca420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48100 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c 1 file changed, 35 insertions(+), 35 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c index 9294a0f..1470f00 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c @@ -22,9 +22,9 @@ PAD_NC(GPP_A13, UP_20K), PAD_NC(GPP_A14, UP_20K), PAD_NC(GPP_A15, UP_20K), - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_NC(GPP_A16, UP_20K), PAD_NC(GPP_A17, UP_20K), - PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), + PAD_NC(GPP_A18, NONE), /* GPP_A19 - RESERVED */ PAD_NC(GPP_A20, UP_20K), PAD_NC(GPP_A21, UP_20K), @@ -32,8 +32,8 @@ PAD_NC(GPP_A23, UP_20K), /* GPIO Group GPP_B */ - PAD_CFG_GPO_GPIO_DRIVER(GPP_B0, 1, DEEP, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_B1, 1, DEEP, NONE), + PAD_NC(GPP_B0, UP_20K), + PAD_NC(GPP_B1, UP_20K), PAD_NC(GPP_B2, NONE), PAD_NC(GPP_B3, UP_20K), PAD_NC(GPP_B4, UP_20K), @@ -43,7 +43,7 @@ PAD_NC(GPP_B8, UP_20K), PAD_NC(GPP_B9, UP_20K), PAD_NC(GPP_B10, UP_20K), - PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE), + PAD_NC(GPP_B11, DN_20K), PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), /* SPKR + JBR1 ("Top-Block Swap") */ @@ -63,12 +63,12 @@ PAD_NC(GPP_C2, NONE), /* GPP_C3 - RESERVED */ /* GPP_C4 - RESERVED */ - PAD_CFG_GPO_GPIO_DRIVER(GPP_C5, 1, DEEP, NONE), + PAD_NC(GPP_C5, NONE), /* GPP_C6 - RESERVED */ /* GPP_C7 - RESERVED */ - PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF), + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), PAD_NC(GPP_C11, NONE), PAD_NC(GPP_C12, UP_20K), PAD_NC(GPP_C13, UP_20K), @@ -130,7 +130,7 @@ PAD_NC(GPP_F2, UP_20K), PAD_NC(GPP_F3, UP_20K), PAD_NC(GPP_F4, UP_20K), - PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, PLTRST), + PAD_NC(GPP_F5, NONE), PAD_NC(GPP_F6, UP_20K), PAD_NC(GPP_F7, UP_20K), PAD_NC(GPP_F8, UP_20K), @@ -148,7 +148,7 @@ PAD_NC(GPP_F20, UP_20K), PAD_NC(GPP_F21, UP_20K), PAD_NC(GPP_F22, UP_20K), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, RSMRST, NONE), + PAD_NC(GPP_F23, NONE), /* GPIO Group GPP_G */ PAD_NC(GPP_G0, NONE), /* JPCIE6-A19 (DGPU_PWR_EN#) */ @@ -168,7 +168,7 @@ PAD_CFG_GPI(GPP_G14, NONE, PLTRST), /* SKU_ID[2] */ PAD_CFG_GPI(GPP_G15, NONE, PLTRST), /* SKU_ID[3] */ PAD_CFG_GPI(GPP_G16, NONE, PLTRST), /* SKU_ID[4] */ - PAD_NC(GPP_G17, NONE), + PAD_NC(GPP_G17, UP_20K), PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* BMC NMI# */ PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), /* BMC SMI# */ PAD_CFG_GPI(GPP_G20, NONE, PLTRST), /* JPI2C1 PWRFAIL# */ @@ -177,21 +177,21 @@ PAD_NC(GPP_G23, NONE), /* GPIO Group GPP_H */ - PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, DEEP, NONE), - PAD_CFG_GPI_INT(GPP_H1, NONE, PLTRST, OFF), + PAD_NC(GPP_H0, UP_20K), + PAD_NC(GPP_H1, NONE), PAD_NC(GPP_H2, UP_20K), PAD_NC(GPP_H3, UP_20K), - PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H5, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H6, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H7, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H8, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H9, 1, PLTRST, NONE), - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_NC(GPP_H4, UP_20K), + PAD_NC(GPP_H5, UP_20K), + PAD_NC(GPP_H6, UP_20K), + PAD_NC(GPP_H7, UP_20K), + PAD_NC(GPP_H8, UP_20K), + PAD_NC(GPP_H9, UP_20K), + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, UP_20K), PAD_NC(GPP_H12, UP_20K), PAD_NC(GPP_H13, NONE), - PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), + PAD_NC(GPP_H14, NONE), PAD_NC(GPP_H15, NONE), PAD_NC(GPP_H16, NONE), PAD_NC(GPP_H17, NONE), @@ -200,20 +200,20 @@ PAD_NC(GPP_H20, UP_20K), PAD_NC(GPP_H21, UP_20K), PAD_NC(GPP_H22, UP_20K), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H23, 1, PLTRST, NONE), + PAD_NC(GPP_H23, NONE), /* GPIO Group GPP_I */ - PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_NC(GPP_I0, NONE), + PAD_NC(GPP_I1, NONE), + PAD_NC(GPP_I2, NONE), + PAD_NC(GPP_I3, NONE), PAD_NC(GPP_I4, NONE), - PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + PAD_NC(GPP_I5, NONE), + PAD_NC(GPP_I6, UP_20K), + PAD_NC(GPP_I7, NONE), + PAD_NC(GPP_I8, UP_20K), + PAD_NC(GPP_I9, NONE), + PAD_NC(GPP_I10, UP_20K), /* GPIO Group GPD */ PAD_NC(GPD0, NONE), @@ -224,7 +224,7 @@ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), PAD_CFG_NF(GPD6, NONE, PWROK, NF1), PAD_NC(GPD7, UP_20K), - PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_NC(GPD8, UP_20K), PAD_NC(GPD9, UP_20K), PAD_NC(GPD10, UP_20K), PAD_NC(GPD11, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/48100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06b942e3182469f87e41914c893e5b485ccca420 Gerrit-Change-Number: 48100 Gerrit-PatchSet: 15 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the...
by Furquan Shaikh (Code Review) 11 Dec '20

11 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48280 ) Change subject: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/48280/2/src/soc/intel/jasperlake/r… File src/soc/intel/jasperlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/48280/2/src/soc/intel/jasperlake/r… PS2, Line 142: cse_fw_sync(); > Agree, I will explore the suggested method.. Yeah, I think the way we have it right now is okay for TGL/JSL. THe dram_init_done_hooks is mostly a good to have as future work. -- To view, visit https://review.coreboot.org/c/coreboot/+/48280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a Gerrit-Change-Number: 48280 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Dec 2020 18:32:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
by Sridhar Siricilla (Code Review) 11 Dec '20

11 Dec '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48281 ) Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/ro… File src/soc/intel/tigerlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/ro… PS4, Line 136: fsp_memory_init(s3wake); : pmc_set_disb(); : if (!s3wake) { : if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) : cse_fw_sync(); > > Is there a dependency on having FSP-M run before this? The HECI interface was initialized just bef […] >Yes, from past discussions Intel had mentioned that you cannot run HMRPFO when dram is not initialized. That is the reason this is being done after memory init. I think it would be good to add a comment here. That's true. I have added comment indicating cse_fw_sync() should be called after DRAM Init. -- To view, visit https://review.coreboot.org/c/coreboot/+/48281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856 Gerrit-Change-Number: 48281 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Dec 2020 18:19:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: hatch: enable genesis PCIe/USB devices
by Joe Tessler (Code Review) 11 Dec '20

11 Dec '20

Joe Tessler has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48523 ) Change subject: hatch: enable genesis PCIe/USB devices ...................................................................... hatch: enable genesis PCIe/USB devices Updates PCIe registers and GPIO CLKREQ lines to match the schematic. BUG=b:173566597,b:173567124,b:173566890 TEST=build AP firmware; flash device BRANCH=none Change-Id: Ibf519b812022839f749e503436f097d3b48c4383 Signed-off-by: Joe Tessler <jrt(a)google.com> --- M src/mainboard/google/hatch/variants/genesis/gpio.c M src/mainboard/google/hatch/variants/genesis/overridetree.cb 2 files changed, 75 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/48523/1 diff --git a/src/mainboard/google/hatch/variants/genesis/gpio.c b/src/mainboard/google/hatch/variants/genesis/gpio.c index 5a911fc..a095da1 100644 --- a/src/mainboard/google/hatch/variants/genesis/gpio.c +++ b/src/mainboard/google/hatch/variants/genesis/gpio.c @@ -14,6 +14,16 @@ /* B5 : LAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : M2_SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : M2_TPU0_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : CLK_PCIE_REQ3 (not connected) */ + PAD_NC(GPP_B8, NONE), + /* B9 : M2_TPU1_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : M2_WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* C0 : SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), diff --git a/src/mainboard/google/hatch/variants/genesis/overridetree.cb b/src/mainboard/google/hatch/variants/genesis/overridetree.cb index 835a8aa..f1186fa 100644 --- a/src/mainboard/google/hatch/variants/genesis/overridetree.cb +++ b/src/mainboard/google/hatch/variants/genesis/overridetree.cb @@ -53,12 +53,7 @@ }" # Type-A Port 4 register "usb2_ports[5]" = "{ .enable = 1, - .ocpin = OC0, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A port 0 + }" # M.2 Port for HDMI-to-USB register "usb2_ports[6]" = "USB2_PORT_EMPTY" register "usb2_ports[7]" = "USB2_PORT_EMPTY" register "usb2_ports[8]" = "USB2_PORT_EMPTY" @@ -185,13 +180,51 @@ # PCIe port 7 for LAN register "PcieRpEnable[6]" = "1" register "PcieRpLtrEnable[6]" = "1" - # PCIe port 11 (x2) for NVMe hybrid storage devices - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" # Uses CLK SRC 0 register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" + # PCIe port 8 for WLAN + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + # Uses CLK SRC 5 + register "PcieClkSrcUsage[5]" = "7" + register "PcieClkSrcClkReq[5]" = "5" + + # PCIe port 9 for TPU #0 + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + # RP 9 uses CLK SRC 2 + register "PcieClkSrcUsage[2]" = "8" + register "PcieClkSrcClkReq[2]" = "2" + + # PCIe port 10 for TPU #1 + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "1" + # RP 10 uses CLK SRC 4 + register "PcieClkSrcUsage[4]" = "9" + register "PcieClkSrcClkReq[4]" = "4" + + # PCIe port 11 (x2) for NVMe hybrid storage devices + register "PcieRpEnable[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + # RP 11 uses CLK SRC 1 + register "PcieClkSrcUsage[1]" = "10" + register "PcieClkSrcClkReq[1]" = "1" + # Disable the remaining port 12 + register "PcieRpEnable[11]" = "0" + + # PCIe port 13 for i350 NIC (x4) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + # RP 13 uses CLK SRC 3 + register "PcieClkSrcUsage[3]" = "12" + # RP 13 does not use a source clock request line + # Disable the remaining ports 14-16 + register "PcieRpEnable[13]" = "0" + register "PcieRpEnable[14]" = "0" + register "PcieRpEnable[15]" = "0" + # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" @@ -333,15 +366,13 @@ device usb 3.3 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 3.4 on end + # USB3 Port 5 is not populated + device usb 3.4 off end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Middle"" + register "desc" = ""USB3 M.2 HDMI-to-USB"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "group" = "ACPI_PLD_GROUP(2, 0)" device usb 3.5 on end end end @@ -383,8 +414,8 @@ end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1c.6 on - chip drivers/net + device pci 1c.6 on # PCI Express Port 7 (LAN) + chip drivers/net # RTL8111H Ethernet NIC register "customized_leds" = "0x05af" register "wake" = "GPE0_DW1_07" # GPP_C7 register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" @@ -394,8 +425,24 @@ register "device_index" = "0" device pci 00.0 on end end - end # RTL8111H Ethernet NIC + end + device pci 1c.7 on # PCI Express Port 8 (WLAN) + register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot + end + device pci 1d.0 on # PCI Express Port 9 (TPU) + register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot + end + device pci 1d.1 on # PCI Express Port 10 (TPU) + register "PcieRpSlotImplemented[9]" = "1" # M.2 Slot + end device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) + device pci 1d.3 off end # PCI Express Port 12 (non-root) + device pci 1d.4 on # PCI Express Port 13 (X4 i350 NIC) + register "PcieRpSlotImplemented[12]" = "0" # Built-in + end + device pci 1d.5 off end # PCI Express Port 14 (non-root) + device pci 1d.6 off end # PCI Express Port 15 (non-root) + device pci 1d.7 off end # PCI Express Port 16 (non-root) device pci 1e.3 off end # GSPI #1 end -- To view, visit https://review.coreboot.org/c/coreboot/+/48523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf519b812022839f749e503436f097d3b48c4383 Gerrit-Change-Number: 48523 Gerrit-PatchSet: 1 Gerrit-Owner: Joe Tessler <jrt(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Add data fabric read helper function
by Felix Held (Code Review) 11 Dec '20

11 Dec '20

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47726 ) Change subject: soc/amd/picasso: Add data fabric read helper function ...................................................................... soc/amd/picasso: Add data fabric read helper function Add new helper function to support reading a register from the data fabric. BUG=b:155307433 TEST=Boot trembyle with If64fd624597b2ced014ba7f0332a6a48143c0e8c and confirm read values match expected values. BRANCH=Zork Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1 Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47726 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/data_fabric.c M src/soc/amd/picasso/include/soc/data_fabric.h 2 files changed, 36 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/picasso/data_fabric.c b/src/soc/amd/picasso/data_fabric.c index 79fdba1..f576d89 100644 --- a/src/soc/amd/picasso/data_fabric.c +++ b/src/soc/amd/picasso/data_fabric.c @@ -167,3 +167,23 @@ .vendor = PCI_VENDOR_ID_AMD, .devices = pci_device_ids, }; + +uint32_t data_fabric_read_reg32(uint8_t function, uint16_t reg, uint8_t instance_id) +{ + uint32_t fabric_indirect_access_reg = 0; + + if (instance_id == BROADCAST_FABRIC_ID) + /* No bit masking required. Macros will apply mask to values. */ + return pci_read_config32(_SOC_DEV(DF_DEV, function), reg); + + fabric_indirect_access_reg |= DF_IND_CFG_INST_ACC_EN; + /* Register offset field [10:2] in this register corresponds to [10:2] of the + requested offset. */ + fabric_indirect_access_reg |= reg & DF_IND_CFG_ACC_REG_MASK; + fabric_indirect_access_reg |= + (function << DF_IND_CFG_ACC_FUN_SHIFT) & DF_IND_CFG_ACC_FUN_MASK; + fabric_indirect_access_reg |= instance_id << DF_IND_CFG_INST_ID_SHIFT; + pci_write_config32(SOC_DF_F4_DEV, DF_FICAA_BIOS, fabric_indirect_access_reg); + + return pci_read_config32(SOC_DF_F4_DEV, DF_FICAD_LO); +} diff --git a/src/soc/amd/picasso/include/soc/data_fabric.h b/src/soc/amd/picasso/include/soc/data_fabric.h index 842cb94..01fdc73 100644 --- a/src/soc/amd/picasso/include/soc/data_fabric.h +++ b/src/soc/amd/picasso/include/soc/data_fabric.h @@ -7,6 +7,7 @@ /* D18F0 - Fabric Configuration registers */ #define IOMS0_FABRIC_ID 9 +#define BROADCAST_FABRIC_ID 0xff #define D18F0_VGAEN 0x80 #define VGA_ADDR_ENABLE BIT(0) @@ -24,6 +25,21 @@ #define NB_MMIO_LIMIT(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_LIMIT0) #define NB_MMIO_CONTROL(reg) ((reg) * 4 * sizeof(uint32_t) + D18F0_MMIO_CTRL0) +#define DF_FICAA_BIOS 0x5C +#define DF_FICAD_LO 0x98 +#define DF_FICAD_HI 0x9C + +#define DF_IND_CFG_INST_ACC_EN (1 << 0) +#define DF_IND_CFG_ACC_REG_SHIFT 2 +#define DF_IND_CFG_ACC_REG_MASK (0x1ff << DF_IND_CFG_ACC_REG_SHIFT) +#define DF_IND_CFG_ACC_FUN_SHIFT 11 +#define DF_IND_CFG_ACC_FUN_MASK (0x7 << DF_IND_CFG_ACC_REG_SHIFT) +#define DF_IND_CFG_64B_EN_SHIFT 14 +#define DF_IND_CFG_64B_EN (0x1 << DF_IND_CFG_ACC_REG_SHIFT) +#define DF_IND_CFG_INST_ID_SHIFT 16 +#define DF_IND_CFG_INST_ID_MASK (0xff << DF_IND_CFG_ACC_REG_SHIFT) + void data_fabric_set_mmio_np(void); +uint32_t data_fabric_read_reg32(uint8_t function, uint16_t reg, uint8_t instance_id); #endif /* AMD_PICASSO_DATA_FABRIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1 Gerrit-Change-Number: 47726 Gerrit-PatchSet: 5 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: add 0xcf9 reset
by Felix Held (Code Review) 11 Dec '20

11 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48488 ) Change subject: soc/amd/cezanne: add 0xcf9 reset ...................................................................... soc/amd/cezanne: add 0xcf9 reset This also temporary adds a prototype for chipset_handle_reset that will be removed when the FSP integration gets added. Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/majolica/Kconfig M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/include/soc/iomap.h A src/soc/amd/cezanne/include/soc/reset.h M src/soc/amd/cezanne/include/soc/southbridge.h A src/soc/amd/cezanne/reset.c 7 files changed, 82 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/48488/1 diff --git a/src/mainboard/amd/majolica/Kconfig b/src/mainboard/amd/majolica/Kconfig index f811c39..cb3237c 100644 --- a/src/mainboard/amd/majolica/Kconfig +++ b/src/mainboard/amd/majolica/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_AMD_CEZANNE - select MISSING_BOARD_RESET config FMDFILE string diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index aec9a47..894d8e7 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -13,6 +13,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select HAVE_CF9_RESET select IOAPIC select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 946e480..15db2e6 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -6,10 +6,15 @@ bootblock-y += bootblock.c bootblock-y += early_fch.c +bootblock-y += reset.c +verstage_x86-y += reset.c + +romstage-y += reset.c romstage-y += romstage.c ramstage-y += chip.c +ramstage-y += reset.c CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 96313ea..4d47f7e 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -4,6 +4,7 @@ #define AMD_CEZANNE_IOMAP_H /* I/O Ranges */ -#define SMB_BASE_ADDR 0xb00 +#define NCP_ERR 0x00f0 +#define SMB_BASE_ADDR 0x0b00 #endif /* AMD_CEZANNE_IOMAP_H */ diff --git a/src/soc/amd/cezanne/include/soc/reset.h b/src/soc/amd/cezanne/include/soc/reset.h new file mode 100644 index 0000000..89dd63e --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/reset.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_RESET_H +#define AMD_CEZANNE_RESET_H + +void set_warm_reset_flag(void); +int is_warm_reset(void); + +/* TODO: remove when <fsp/util.h> gets added back */ +void chipset_handle_reset(uint32_t status); + +#endif /* AMD_CEZANNE_RESET_H */ diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 2456ebc..03ee2bb 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -5,6 +5,13 @@ #include <soc/iomap.h> +/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ +#define PWR_RESET_CFG 0x10 +#define TOGGLE_ALL_PWR_GOOD (1 << 1) + +/* IO 0xf0 NCP Error */ +#define NCP_WARM_BOOT (1 << 7) /* Write-once */ + void fch_pre_init(void); void fch_early_init(void); diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/cezanne/reset.c new file mode 100644 index 0000000..ea2c93f --- /dev/null +++ b/src/soc/amd/cezanne/reset.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <console/console.h> +#include <cf9_reset.h> +#include <reset.h> +#include <soc/reset.h> +#include <soc/southbridge.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/reset.h> +#include <assert.h> + +/* TODO: add <fsp/util.h> back during FSP integration */ + +void set_warm_reset_flag(void) +{ + uint8_t ncp = inw(NCP_ERR); + + outb(NCP_ERR, ncp | NCP_WARM_BOOT); +} + +int is_warm_reset(void) +{ + return !!(inb(NCP_ERR) & NCP_WARM_BOOT); +} + +void do_cold_reset(void) +{ + /* De-assert and then assert all PwrGood signals on CF9 reset. */ + pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | + TOGGLE_ALL_PWR_GOOD); + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void do_warm_reset(void) +{ + set_warm_reset_flag(); + + /* Assert reset signals only. */ + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void do_board_reset(void) +{ + /* TODO: Would a warm_reset() suffice? */ + do_cold_reset(); +} + +void chipset_handle_reset(uint32_t status) +{ + printk(BIOS_ERR, "Error: unexpected call to %s(0x%08x). Doing cold reset.\n", + __func__, status); + BUG(); + do_cold_reset(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Gerrit-Change-Number: 48488 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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