Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48280 )
Change subject: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48280/2/src/soc/intel/jasperlake/r…
File src/soc/intel/jasperlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48280/2/src/soc/intel/jasperlake/r…
PS2, Line 142: cse_fw_sync();
> Agree, I will explore the suggested method..
Yeah, I think the way we have it right now is okay for TGL/JSL. THe dram_init_done_hooks is mostly a good to have as future work.
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Gerrit-Comment-Date: Fri, 11 Dec 2020 18:32:13 +0000
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48281 )
Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/ro…
File src/soc/intel/tigerlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/ro…
PS4, Line 136: fsp_memory_init(s3wake);
: pmc_set_disb();
: if (!s3wake) {
: if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
: cse_fw_sync();
> > Is there a dependency on having FSP-M run before this? The HECI interface was initialized just bef […]
>Yes, from past discussions Intel had mentioned that you cannot run HMRPFO when dram is not initialized. That is the reason this is being done after memory init. I think it would be good to add a comment here.
That's true. I have added comment indicating cse_fw_sync() should be called after DRAM Init.
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48280 )
Change subject: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage
......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48280/2/src/soc/intel/jasperlake/r…
File src/soc/intel/jasperlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48280/2/src/soc/intel/jasperlake/r…
PS2, Line 138: if (!s3wake)
> I think it is safe to do the call to cse_fw_sync() before save_dimm_info() and also restrict the cal […]
Ack
https://review.coreboot.org/c/coreboot/+/48280/2/src/soc/intel/jasperlake/r…
PS2, Line 142: cse_fw_sync();
> I wonder if we should add dram_init_done_hooks just like we have cbmem_init_hooks. […]
Agree, I will explore the suggested method..
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Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Jamie Ryu, Tim Wawrzynczak, Rizwan Qureshi, Sugnan Prabhu S, Krishna P Bhat D, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48279
to look at the new patch set (#5).
Change subject: soc/intel/common: Move CSE Lite driver functionality into romstage
......................................................................
soc/intel/common: Move CSE Lite driver functionality into romstage
The patch sets up the CSE Lite driver in the romstage instead of ramstage.
With this change, CSE Lite driver sets CSE's boot partition and triggers
CSE FW update in the romstage. The cse_fw_sync() must be called after DRAM
initialized.
Test=Verified on JSL and TGL platforms
BUG=b:174694480
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73
---
M src/soc/intel/common/block/cse/Makefile.inc
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/common/block/include/intelblocks/cse.h
3 files changed, 3 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/48279/5
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