Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48521 )
Change subject: soc/amd/piasso,cezanne: add warning about using all-y in Makefile.inc
......................................................................
soc/amd/piasso,cezanne: add warning about using all-y in Makefile.inc
all-y will also add a compilation unit to the verstage on PSP build that
runs on an ARM code instead of a x86 one. At the moment Cezanne doesn't
have verstage on PSP support yet, but since it'll eventually land it
doesn't hurt to already add the comment now.
Change-Id: I15fb66e796cab48737ba5ac463c4c973794a005a
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/soc/amd/cezanne/Makefile.inc
M src/soc/amd/picasso/Makefile.inc
2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/48521/1
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 946e480..e7d0aea 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -2,6 +2,7 @@
ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
+# Beware that all-y also adds the compilation unit to verstage on PSP
all-y += config.c
bootblock-y += bootblock.c
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index 7cbae92..142fb0c 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -9,6 +9,7 @@
subdirs-y += ../../../cpu/x86/smm
subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
+# Beware that all-y also adds the compilation unit to verstage on PSP
all-y += config.c
all-y += aoac.c
--
To view, visit https://review.coreboot.org/c/coreboot/+/48521
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I15fb66e796cab48737ba5ac463c4c973794a005a
Gerrit-Change-Number: 48521
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newchange
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48485 )
Change subject: soc/amd/picasso/aoac: only check FCH_AOAC_UART_FOR_CONSOLE if used
......................................................................
soc/amd/picasso/aoac: only check FCH_AOAC_UART_FOR_CONSOLE if used
FCH_AOAC_UART_FOR_CONSOLE will only be used in the code if
PICASSO_CONSOLE_UART is selected, so only check if it's a valid value in
this case.
Change-Id: I103dd8d469a084c7dc7dcf55175b1f77f900adc5
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/soc/amd/picasso/aoac.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/48485/1
diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c
index 7fd839b..c97700d 100644
--- a/src/soc/amd/picasso/aoac.c
+++ b/src/soc/amd/picasso/aoac.c
@@ -12,7 +12,7 @@
: CONFIG_UART_FOR_CONSOLE == 2 ? FCH_AOAC_DEV_UART2 \
: CONFIG_UART_FOR_CONSOLE == 3 ? FCH_AOAC_DEV_UART3 \
: -1)
-#if FCH_AOAC_UART_FOR_CONSOLE == -1
+#if CONFIG(PICASSO_CONSOLE_UART) && FCH_AOAC_UART_FOR_CONSOLE == -1
# error Unsupported UART_FOR_CONSOLE chosen
#endif
--
To view, visit https://review.coreboot.org/c/coreboot/+/48485
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I103dd8d469a084c7dc7dcf55175b1f77f900adc5
Gerrit-Change-Number: 48485
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newchange
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48281 )
Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/ro…
File src/soc/intel/tigerlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/ro…
PS4, Line 136: fsp_memory_init(s3wake);
: pmc_set_disb();
: if (!s3wake) {
: if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
: cse_fw_sync();
> Is there a dependency on having FSP-M run before this? The HECI interface was initialized just before this on line 133
Yes, from past discussions Intel had mentioned that you cannot run HMRPFO when dram is not initialized. That is the reason this is being done after memory init. I think it would be good to add a comment here.
> Is the MRC cache data written back to the SPI ROM before CSE FW Sync.
Yes, with Shelley's recent changes, MRC data gets written to cache right away after training.
--
To view, visit https://review.coreboot.org/c/coreboot/+/48281
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856
Gerrit-Change-Number: 48281
Gerrit-PatchSet: 4
Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Thu, 10 Dec 2020 23:34:28 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-MessageType: comment
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48281 )
Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/ro…
File src/soc/intel/tigerlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/ro…
PS4, Line 136: fsp_memory_init(s3wake);
: pmc_set_disb();
: if (!s3wake) {
: if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
: cse_fw_sync();
> Is the MRC cache data written back to the SPI ROM before CSE FW Sync. […]
Yes, but if it runs before FSP-M in the first place, then there is no training on the first boot
--
To view, visit https://review.coreboot.org/c/coreboot/+/48281
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856
Gerrit-Change-Number: 48281
Gerrit-PatchSet: 4
Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Thu, 10 Dec 2020 23:34:02 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-MessageType: comment
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48281 )
Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/ro…
File src/soc/intel/tigerlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/ro…
PS4, Line 136: fsp_memory_init(s3wake);
: pmc_set_disb();
: if (!s3wake) {
: if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
: cse_fw_sync();
> Is there a dependency on having FSP-M run before this? The HECI interface was initialized just befor […]
Is the MRC cache data written back to the SPI ROM before CSE FW Sync. Otherwise, there might be more training.
--
To view, visit https://review.coreboot.org/c/coreboot/+/48281
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856
Gerrit-Change-Number: 48281
Gerrit-PatchSet: 4
Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Thu, 10 Dec 2020 23:27:01 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-MessageType: comment
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48281 )
Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/ro…
File src/soc/intel/tigerlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/ro…
PS4, Line 136: fsp_memory_init(s3wake);
: pmc_set_disb();
: if (!s3wake) {
: if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
: cse_fw_sync();
Is there a dependency on having FSP-M run before this? The HECI interface was initialized just before this on line 133
--
To view, visit https://review.coreboot.org/c/coreboot/+/48281
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856
Gerrit-Change-Number: 48281
Gerrit-PatchSet: 4
Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com>
Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Thu, 10 Dec 2020 23:23:34 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47726 )
Change subject: soc/amd/picasso: Add data fabric read helper function
......................................................................
Patch Set 4: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/47726
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1
Gerrit-Change-Number: 47726
Gerrit-PatchSet: 4
Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com>
Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Thu, 10 Dec 2020 21:51:42 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment