coreboot-gerrit December 2020

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Change in coreboot[master]: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin
by Tim Wawrzynczak (Code Review) 10 Dec '20

10 Dec '20

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48194 ) Change subject: mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin ...................................................................... mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbin In order to pass DB type-C Port 1 USB2 eye diagram, DB USB2 PHY register needs to be overridden. port#1 PortUsb20Enable=1 Usb2PhyPetxiset=3 Usb2PhyTxiset=2 Usb2PhyPredeemp=7 Usb2PhyPehalfbit=1 BUG=b:173676539 BRANCH=None TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48194 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/volteer/variants/delbin/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index c0eaedb..5774047 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -44,6 +44,14 @@ }, }, }" + #These settings improve the USB2 Port1 eye diagram + register "usb2_ports[3]" = "{ + .enable = 1, + .tx_bias = USB2_BIAS_28P15MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_56P3MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Acoustic settings register "AcousticNoiseMitigation" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/48194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 Gerrit-Change-Number: 48194 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer: Assert BT_DISABLE_L (GPP_A13) in early_gpio_table
by Alex Levin (Code Review) 10 Dec '20

10 Dec '20

Alex Levin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48518 ) Change subject: mb/google/volteer: Assert BT_DISABLE_L (GPP_A13) in early_gpio_table ...................................................................... mb/google/volteer: Assert BT_DISABLE_L (GPP_A13) in early_gpio_table BT_DISABLE_L (GPP_A13) has to asserted in early_gpio_table to reset bluetooth on reset. BUG=b:171085081 TEST=volteer2 boots; scope shows assertion of the signal Change-Id: Iaa5799e9cab69c074b7920604c8a6c85ad07358a --- M src/mainboard/google/volteer/variants/baseboard/gpio.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/48518/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index 5d367e7..47e6d65 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -400,7 +400,9 @@ static const struct pad_config early_gpio_table[] = { /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), - + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + /* assert reset on reboot */ + PAD_CFG_GPO(GPP_A13, 0, DEEP), /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_A17, NONE, DEEP), -- To view, visit https://review.coreboot.org/c/coreboot/+/48518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa5799e9cab69c074b7920604c8a6c85ad07358a Gerrit-Change-Number: 48518 Gerrit-PatchSet: 1 Gerrit-Owner: Alex Levin <levinale(a)google.com> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: soc/amd/picasso: factor out write_resume_eip to common code
by Felix Held (Code Review) 10 Dec '20

10 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48516 ) Change subject: soc/amd/picasso: factor out write_resume_eip to common code ...................................................................... soc/amd/picasso: factor out write_resume_eip to common code Change-Id: I24454aa9e2ccc98b2aceb6b189e072e6e50b8b30 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/cpu/noncar/Makefile.inc A src/soc/amd/common/block/cpu/noncar/write_resume_eip.c A src/soc/amd/common/block/include/amdblocks/cpu.h M src/soc/amd/picasso/bootblock.c 4 files changed, 36 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/48516/1 diff --git a/src/soc/amd/common/block/cpu/noncar/Makefile.inc b/src/soc/amd/common/block/cpu/noncar/Makefile.inc index 7a3be34..ed08d2a 100644 --- a/src/soc/amd/common/block/cpu/noncar/Makefile.inc +++ b/src/soc/amd/common/block/cpu/noncar/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR),y) bootblock-y += pre_c.S +bootblock-y += write_resume_eip.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR diff --git a/src/soc/amd/common/block/cpu/noncar/write_resume_eip.c b/src/soc/amd/common/block/cpu/noncar/write_resume_eip.c new file mode 100644 index 0000000..e9b59d9 --- /dev/null +++ b/src/soc/amd/common/block/cpu/noncar/write_resume_eip.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <arch/cpu.h> +#include <amdblocks/cpu.h> +#include <cpu/amd/msr.h> +#include <cpu/x86/msr.h> + +asmlinkage void bootblock_resume_entry(void); + +void write_resume_eip(void) +{ + msr_t s3_resume_entry = { + .hi = (uint64_t)(uintptr_t)bootblock_resume_entry >> 32, + .lo = (uintptr_t)bootblock_resume_entry & 0xffffffff, + }; + + /* + * Writing to the EIP register can only be done once, otherwise a fault is triggered. + * When this register is written, it will trigger the microcode to stash the CPU state + * (crX , mtrrs, registers, etc) into the CC6 save area. On resume, the state will be + * restored and execution will continue at the EIP. + */ + if (!acpi_is_wakeup_s3()) + wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); +} diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h new file mode 100644 index 0000000..0a93643 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/cpu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_CPU_H +#define AMD_BLOCK_CPU_H + +void write_resume_eip(void); + +#endif /* AMD_BLOCK_CPU_H */ diff --git a/src/soc/amd/picasso/bootblock.c b/src/soc/amd/picasso/bootblock.c index 0b52a17..7d1f01c 100644 --- a/src/soc/amd/picasso/bootblock.c +++ b/src/soc/amd/picasso/bootblock.c @@ -2,12 +2,12 @@ #include <stdint.h> #include <symbols.h> +#include <amdblocks/cpu.h> #include <amdblocks/reset.h> #include <bootblock_common.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/tsc.h> @@ -16,9 +16,6 @@ #include <soc/southbridge.h> #include <soc/i2c.h> #include <amdblocks/amd_pci_mmconf.h> -#include <acpi/acpi.h> - -asmlinkage void bootblock_resume_entry(void); /* PSP performs the memory training and setting up DRAM map prior to x86 cores being released. Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, @@ -91,23 +88,6 @@ enable_cache(); } -static void write_resume_eip(void) -{ - msr_t s3_resume_entry = { - .hi = (uint64_t)(uintptr_t)bootblock_resume_entry >> 32, - .lo = (uintptr_t)bootblock_resume_entry & 0xffffffff, - }; - - /* - * Writing to the EIP register can only be done once, otherwise a fault is triggered. - * When this register is written, it will trigger the microcode to stash the CPU state - * (crX , mtrrs, registers, etc) into the CC6 save area. On resume, the state will be - * restored and execution will continue at the EIP. - */ - if (!acpi_is_wakeup_s3()) - wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); -} - asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { set_caching(); -- To view, visit https://review.coreboot.org/c/coreboot/+/48516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24454aa9e2ccc98b2aceb6b189e072e6e50b8b30 Gerrit-Change-Number: 48516 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: soc/amd/picasso: move UART console code to common folder
by Felix Held (Code Review) 10 Dec '20

10 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48515 ) Change subject: soc/amd/picasso: move UART console code to common folder ...................................................................... soc/amd/picasso: move UART console code to common folder Change-Id: Ibc9a4c05bdfc7cd3cd0eada67563386c95d2b50e Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- A src/soc/amd/common/block/uart/Makefile.inc R src/soc/amd/common/block/uart/uart_console.c M src/soc/amd/picasso/Makefile.inc 3 files changed, 15 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/48515/1 diff --git a/src/soc/amd/common/block/uart/Makefile.inc b/src/soc/amd/common/block/uart/Makefile.inc new file mode 100644 index 0000000..9d96845 --- /dev/null +++ b/src/soc/amd/common/block/uart/Makefile.inc @@ -0,0 +1,15 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UART),y) + +bootblock-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c + +romstage-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c + +verstage_x86-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c + +ramstage-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c + +ifeq ($(CONFIG_DEBUG_SMI),y) +smm-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c +endif + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_UART diff --git a/src/soc/amd/picasso/uart_console.c b/src/soc/amd/common/block/uart/uart_console.c similarity index 100% rename from src/soc/amd/picasso/uart_console.c rename to src/soc/amd/common/block/uart/uart_console.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 783517d..3e04ecc 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -16,7 +16,6 @@ bootblock-y += early_fch.c bootblock-y += i2c.c bootblock-y += uart.c -bootblock-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c bootblock-y += gpio.c bootblock-y += reset.c @@ -26,14 +25,12 @@ romstage-y += reset.c romstage-y += memmap.c romstage-y += uart.c -romstage-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c romstage-y += psp.c romstage-y += mrc_cache.c verstage-y += i2c.c verstage_x86-y += gpio.c verstage_x86-y += uart.c -verstage_x86-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c verstage_x86-y += reset.c ramstage-y += i2c.c @@ -52,7 +49,6 @@ ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-y += uart.c -ramstage-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c ramstage-y += finalize.c ramstage-y += soc_util.c ramstage-y += psp.c @@ -66,7 +62,6 @@ smm-y += smihandler.c ifeq ($(CONFIG_DEBUG_SMI),y) smm-y += uart.c -smm-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c endif smm-y += gpio.c smm-y += psp.c -- To view, visit https://review.coreboot.org/c/coreboot/+/48515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc9a4c05bdfc7cd3cd0eada67563386c95d2b50e Gerrit-Change-Number: 48515 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/amd/picasso: rename PICASSO_CONSOLE_UART to AMD_SOC_CONSOLE_UART
by Felix Held (Code Review) 10 Dec '20

10 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48508 ) Change subject: soc/amd/picasso: rename PICASSO_CONSOLE_UART to AMD_SOC_CONSOLE_UART ...................................................................... soc/amd/picasso: rename PICASSO_CONSOLE_UART to AMD_SOC_CONSOLE_UART This allows factoring out the common initialization for the integrated UARTs. Change-Id: I7399a13b9280b732086c6f8e6dfd9f1207d8c8ff Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/Kconfig M src/mainboard/google/zork/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/aoac.c M src/soc/amd/picasso/early_fch.c 6 files changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/48508/1 diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 6776621..c1d68fa 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -12,7 +12,7 @@ select AZALIA_PLUGIN_SUPPORT select HAVE_ACPI_RESUME select DRIVERS_UART_ACPI - select PICASSO_CONSOLE_UART if !AMD_LPC_DEBUG_CARD + select AMD_SOC_CONSOLE_UART if !AMD_LPC_DEBUG_CARD config FMDFILE string @@ -26,7 +26,7 @@ help AMD's debug card contains an SMSC SIO1036 device which provides an I/O-mapped UART in the system. This is mutually exclusive with - PICASSO_CONSOLE_UART which selects the SoC's integrated memory-mapped + AMD_SOC_CONSOLE_UART which selects the SoC's integrated memory-mapped UART for coreboot console output. choice diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index d861f1d..c1cbae9 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -34,7 +34,7 @@ select GFXUMA select GOOGLE_SMBIOS_MAINBOARD_VERSION select MAINBOARD_HAS_CHROMEOS - select PICASSO_CONSOLE_UART + select AMD_SOC_CONSOLE_UART select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 select PCIEXP_ASPM diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index bd9964b..ab926aa 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -273,7 +273,7 @@ help Base address for the ACPI registers. -config PICASSO_CONSOLE_UART +config AMD_SOC_CONSOLE_UART bool "Use Picasso UART controller for console" default n select DRIVERS_UART_8250MEM @@ -289,7 +289,7 @@ choice prompt "UART Frequency" - depends on PICASSO_CONSOLE_UART + depends on AMD_SOC_CONSOLE_UART default PICASSO_UART_48MZ config PICASSO_UART_48MZ @@ -313,7 +313,7 @@ present when this option is used. config CONSOLE_UART_BASE_ADDRESS - depends on CONSOLE_SERIAL && PICASSO_CONSOLE_UART + depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART hex default 0xfedc9000 if UART_FOR_CONSOLE = 0 default 0xfedca000 if UART_FOR_CONSOLE = 1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 7cbae92..783517d 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -16,7 +16,7 @@ bootblock-y += early_fch.c bootblock-y += i2c.c bootblock-y += uart.c -bootblock-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +bootblock-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c bootblock-y += gpio.c bootblock-y += reset.c @@ -26,14 +26,14 @@ romstage-y += reset.c romstage-y += memmap.c romstage-y += uart.c -romstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +romstage-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c romstage-y += psp.c romstage-y += mrc_cache.c verstage-y += i2c.c verstage_x86-y += gpio.c verstage_x86-y += uart.c -verstage_x86-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +verstage_x86-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c verstage_x86-y += reset.c ramstage-y += i2c.c @@ -52,7 +52,7 @@ ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-y += uart.c -ramstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +ramstage-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c ramstage-y += finalize.c ramstage-y += soc_util.c ramstage-y += psp.c @@ -66,7 +66,7 @@ smm-y += smihandler.c ifeq ($(CONFIG_DEBUG_SMI),y) smm-y += uart.c -smm-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c +smm-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c endif smm-y += gpio.c smm-y += psp.c diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c index c97700d..aed6d74 100644 --- a/src/soc/amd/picasso/aoac.c +++ b/src/soc/amd/picasso/aoac.c @@ -12,7 +12,7 @@ : CONFIG_UART_FOR_CONSOLE == 2 ? FCH_AOAC_DEV_UART2 \ : CONFIG_UART_FOR_CONSOLE == 3 ? FCH_AOAC_DEV_UART3 \ : -1) -#if CONFIG(PICASSO_CONSOLE_UART) && FCH_AOAC_UART_FOR_CONSOLE == -1 +#if CONFIG(AMD_SOC_CONSOLE_UART) && FCH_AOAC_UART_FOR_CONSOLE == -1 # error Unsupported UART_FOR_CONSOLE chosen #endif @@ -43,13 +43,13 @@ for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) power_on_aoac_device(aoac_devs[i]); - if (CONFIG(PICASSO_CONSOLE_UART)) + if (CONFIG(AMD_SOC_CONSOLE_UART)) power_on_aoac_device(FCH_AOAC_UART_FOR_CONSOLE); /* Wait for AOAC devices to indicate power and clock OK */ for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) wait_for_aoac_enabled(aoac_devs[i]); - if (CONFIG(PICASSO_CONSOLE_UART)) + if (CONFIG(AMD_SOC_CONSOLE_UART)) wait_for_aoac_enabled(FCH_AOAC_UART_FOR_CONSOLE); } diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c index f56a758..a9118ad 100644 --- a/src/soc/amd/picasso/early_fch.c +++ b/src/soc/amd/picasso/early_fch.c @@ -39,7 +39,7 @@ */ clear_uart_legacy_config(); - if (CONFIG(PICASSO_CONSOLE_UART)) + if (CONFIG(AMD_SOC_CONSOLE_UART)) set_uart_config(CONFIG_UART_FOR_CONSOLE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/48508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7399a13b9280b732086c6f8e6dfd9f1207d8c8ff Gerrit-Change-Number: 48508 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: WIP
by Angel Pons (Code Review) 10 Dec '20

10 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48551 ) Change subject: WIP ...................................................................... WIP Change-Id: Ieb0a18b64a9d6218a300ee646185fe75b7a8e5aa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/early_init.c A src/northbridge/intel/sandybridge/early_peg.c M src/northbridge/intel/sandybridge/sandybridge.h 4 files changed, 284 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/48551/1 diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 6380681..02a4744 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -20,6 +20,7 @@ romstage-y += raminit_shared.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) romstage-y += early_dmi.c +romstage-y += early_peg.c romstage-y += raminit.c romstage-y += raminit_common.c romstage-y += raminit_iosav.c diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 45b5b8f..2a8b6f4 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/cpu.h> #include <console/console.h> +#include <cpu/intel/model_206ax/model_206ax.h> #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> @@ -121,8 +123,6 @@ static void start_peg_link_training(void) { - u32 deven; - const u16 base_rev = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID) & BASE_REV_MASK; /* * PEG on IvyBridge+ needs a special startup sequence. @@ -131,7 +131,10 @@ if ((base_rev != BASE_REV_IVB) || CONFIG(HAVE_MRC)) return; - deven = pci_read_config32(HOST_BRIDGE, DEVEN); + const u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN); + + if (deven & DEVEN_PEG10) + init_peg_pre(PCI_DEV(0, 1, 0)); /* * For each PEG device, set bit 5 to use three retries for OC (Offset Calibration). @@ -148,6 +151,9 @@ if (deven & DEVEN_PEG60) pci_update_config32(PCI_DEV(0, 6, 0), AFE_PWRON, ~(1 << 16), 1 << 5); + + if (deven & DEVEN_PEG10) + init_peg_post(PCI_DEV(0, 1, 0)); } void systemagent_early_init(void) diff --git a/src/northbridge/intel/sandybridge/early_peg.c b/src/northbridge/intel/sandybridge/early_peg.c new file mode 100644 index 0000000..30eb934 --- /dev/null +++ b/src/northbridge/intel/sandybridge/early_peg.c @@ -0,0 +1,270 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/cpu.h> +#include <console/console.h> +#include <cpu/intel/model_206ax/model_206ax.h> +#include <delay.h> +#include <device/mmio.h> +#include <device/device.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <northbridge/intel/sandybridge/sandybridge.h> + +static void peg_update_field( + const pci_devfn_t dev, + const u32 offset, + const u32 mask, + const u32 value, + const u8 shift) +{ + pci_update_config32(dev, offset, ~(mask << shift), value << shift); +} + +static void peg_update_bundles( + const pci_devfn_t dev, + const u32 offset, + const u32 mask, + const u32 val, + const u8 shift) +{ + for (int i = 0; i < 8; i++) + peg_update_field(dev, offset + (i << 5), mask, val, shift); +} + +static void peg_update_lanes( + const pci_devfn_t dev, + const u32 offset, + const u32 mask, + const u32 val, + const u8 shift) +{ + for (int i = 0; i < 16; i++) + peg_update_field(dev, offset + (i << 4), mask, val, shift); +} + +static void peg_recipe(const pci_devfn_t dev) +{ + const u32 cpuid = cpu_get_cpuid(); + const u8 stepping = cpuid & 0xf; + + u32 value; + + /* E1 PWRFSM fix */ + if (stepping == IVB_STEP_E1) + peg_update_bundles(dev, 0x914, 1, 1, 31); + + /* UneqMM steps */ + peg_update_lanes(dev, 0xa00, 3, 0, 26); + peg_update_lanes(dev, 0xa04, 1, 1, 11); + + /* UneqMM Gen3 FIXME: PEG10 only */ + if (stepping >= IVB_STEP_C0) + peg_update_bundles(dev, 0x700, 7, 4, 10); + + /* Disable the 2nd order loop */ + peg_update_bundles(dev, 0x904, 7, 0, 22); + peg_update_bundles(dev, 0x90c, 7, 0, 17); + + /* fixrtermoffset */ + peg_update_bundles(dev, 0x90c, 0xf, 5, 21); + + /* Sampler Calibration step is done separately */ + + /* setcdrpg (PGACQ and PGTRK) */ + peg_update_bundles(dev, 0x904, 0x3f, 0x18, 16); + peg_update_bundles(dev, 0x90c, 0x3f, 0x09, 5); + + /* setl0sfixes */ + if (stepping >= IVB_STEP_C0) + peg_update_bundles(dev, 0x700, 1, 1, 15); + + /* setdfemfc */ + peg_update_lanes(dev, 0xa04, 3, 1, 17); + + /* setdfegainacq */ + peg_update_bundles(dev, 0x904, 3, 1, 29); + + /* setg2rxctlepeak */ + peg_update_bundles(dev, 0x910, 0xf, 0, 10); + + /* setg3rxctlepeak */ + value = stepping <= IVB_STEP_B0 ? 0 : 12; + peg_update_bundles(dev, 0x910, 0xf, value, 6); + + /* setVrefAdap */ + peg_update_lanes(dev, 0xa00, 0x1f, 12, 1); + + /* setctleoc */ + value = stepping >= IVB_STEP_C0 ? 1 : 0; + peg_update_lanes(dev, 0xa04, 1, value, 12); + + if (stepping >= IVB_STEP_C0) { + /* setdfelsbsel */ + peg_update_bundles(dev, 0x900, 3, 0, 26); + + /* setagcgainacq */ + peg_update_bundles(dev, 0x908, 3, 2, 27); + + /* setagcacqlen */ + peg_update_lanes(dev, 0xa00, 3, 2, 17); + + /* setsampleratspeedcal */ + peg_update_bundles(dev, 0x700, 1, 1, 3); + + /* setoffcorgain */ + peg_update_bundles(dev, 0x904, 3, 1, 10); + + /* setdfesumctl */ + peg_update_lanes(dev, 0xa00, 3, 3, 24); + } + + /* setrxvcmdssel */ + peg_update_bundles(dev, 0x908, 3, 1, 30); + + /* Swing Control: Reduced */ + if (stepping >= IVB_STEP_C0) { + /* setpegirefctl */ + peg_update_bundles(dev, 0x904, 0x1f, 0x05, 0); + + /* setpegtxvref */ + peg_update_bundles(dev, 0x904, 0x1f, 0x14, 5); + } + + /* fixtxrtermoffset = -3 */ + peg_update_bundles(dev, 0x90c, 0x1f, 0x7, 25); + + if (stepping >= IVB_STEP_K0) { + /* setK0ctocfix */ + peg_update_bundles(dev, 0x700, 1, 1, 21); + + /* setK0l0sfreezefix */ + peg_update_bundles(dev, 0x700, 3, 1, 24); + + /* setK0samplerfix */ + peg_update_bundles(dev, 0x700, 1, 1, 19); + + /* setK0resetalignfix */ + peg_update_bundles(dev, 0x700, 1, 1, 23); + + /* setK0cdcprotfix */ + peg_update_bundles(dev, 0x700, 1, 1, 22); + } + + /* setctleocgen2 */ + if (stepping >= IVB_STEP_D0) + peg_update_bundles(dev, 0x914, 1, 1, 9); + + /* + * ECO(3621419): Aggresive Rx L0s freeze resulting in Rx + * errors since AGC is in open loop for long time (L0s Exit) + */ + if (stepping >= IVB_STEP_E0) + peg_update_bundles(dev, 0x914, 1, 1, 27); + + if (stepping >= IVB_STEP_D0) { + /* setctleocgen3 */ + peg_update_bundles(dev, 0x914, 1, 1, 10); + + /* setD0dfemfcgen3 */ + peg_update_bundles(dev, 0x700, 3, 1, 27); + + /* setD0dfemfcctlegaingen3 */ + peg_update_bundles(dev, 0x700, 7, 0, 29); + + /* afeln0cfg0_d1f0.useerrd */ + peg_update_lanes(dev, 0xa00, 1, 1, 21); + } + + /* setD0disableL1exitfix */ + if (stepping >= IVB_STEP_D0) + peg_update_field(dev, 0xc38, 1, 1, 27); + + if (stepping >= IVB_STEP_D0) { + /* setD0dfeidacpdgen1 */ + peg_update_bundles(dev, 0x904, 0xf, 5, 25); + + /* setD0dfeidacpdgen2 */ + peg_update_bundles(dev, 0x914, 0xf, 0xd, 13); + + /* setD0dfeidacpdgen3 */ + peg_update_bundles(dev, 0x914, 0xf, 5, 8); + } + + pci_update_config32(dev, 0x308, ~0x7fff, 0x126c); + pci_update_config32(dev, 0x314, ~(0x7f << 16), 0x13 << 16); +} + +static void do_peg_gen3_equalization(const pci_devfn_t dev) +{ + u8 RootPortPreset[16]; + u8 EndPointPreset[16]; + u8 EndPointHint[16]; + + pci_or_config32(dev, 0xdd8, 3 << 14); + + for (int i = 0; i < 16; i++) { + RootPortPreset[i] = 8; + EndPointPreset[i] = 7; + EndPointHint[i] = 2; + } + + for (int i = 0; i < 8; ++i) { + pci_update_config32(dev, 0xDA0 + i * 4, 0x80F080F0, + RootPortPreset[2 * i] | + (EndPointPreset[2 * i] << 8) | + (EndPointHint[2 * i] << 12) | + (RootPortPreset[2 * i + 1] << 16) | + (EndPointPreset[2 * i + 1] << 24) | + (EndPointHint[2 * i + 1] << 28)); + } +} + +static void retrain_peg(const pci_devfn_t dev) +{ + pci_or_config8(dev, 0xb0, 1 << 5); + + //while (pci_read_config16(dev, 0xb2) & (1 << 11)) + // ; +} + +static void additional_peg_steps(const pci_devfn_t dev) +{ + peg_update_field(dev, 0x1fc, 1, 1, 21); + + /* Update the N_FTS values, requires link retrain */ + peg_update_field(dev, 0x22c, 0xffff, 0x403c, 0); + peg_update_field(dev, 0x228, 0x00ff, 0x001c, 0); + + retrain_peg(dev); +} + +void init_peg_pre(const pci_devfn_t dev) +{ + const bool gen3_capable = !(pci_read_config32(HOST_BRIDGE, CAPID0_B) & 1 << 20); + + pci_or_config32(dev, 0x250, 1 << 2); + + peg_recipe(dev); + + if (gen3_capable) + do_peg_gen3_equalization(dev); + + const u32 link_speed = gen3_capable ? 3 : 2; + + const u32 link_width = 16; + + pci_update_config32(dev, 0xac, ~0x3ff, (link_width - 1) << 4 | link_speed); + pci_update_config16(dev, 0xd0, ~0xf, link_speed); +} + +void init_peg_post(const pci_devfn_t dev) +{ + mdelay(100); + + pci_and_config32(dev, 0x250, ~(1 << 2)); + + /* Disable PEG Debug Align Message */ + peg_update_field(dev, 0x258, 1, 1, 29); + + additional_peg_steps(dev); +} diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 235ca0e..80e62a3 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -84,6 +84,10 @@ void northbridge_romstage_finalize(int s3resume); void early_init_dmi(void); +#include <device/pci_type.h> +void init_peg_pre(const pci_devfn_t dev); +void init_peg_post(const pci_devfn_t dev); + /* mainboard_early_init: Optional callback, run after console init but before raminit. */ void mainboard_early_init(int s3resume); int mainboard_should_reset_usb(int s3resume); -- To view, visit https://review.coreboot.org/c/coreboot/+/48551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb0a18b64a9d6218a300ee646185fe75b7a8e5aa Gerrit-Change-Number: 48551 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/piasso,cezanne: add warning about using all-y in Makefile.inc
by Felix Held (Code Review) 10 Dec '20

10 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48521 ) Change subject: soc/amd/piasso,cezanne: add warning about using all-y in Makefile.inc ...................................................................... soc/amd/piasso,cezanne: add warning about using all-y in Makefile.inc all-y will also add a compilation unit to the verstage on PSP build that runs on an ARM code instead of a x86 one. At the moment Cezanne doesn't have verstage on PSP support yet, but since it'll eventually land it doesn't hurt to already add the comment now. Change-Id: I15fb66e796cab48737ba5ac463c4c973794a005a Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/picasso/Makefile.inc 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/48521/1 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 946e480..e7d0aea 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_AMD_CEZANNE),y) +# Beware that all-y also adds the compilation unit to verstage on PSP all-y += config.c bootblock-y += bootblock.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 7cbae92..142fb0c 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -9,6 +9,7 @@ subdirs-y += ../../../cpu/x86/smm subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage +# Beware that all-y also adds the compilation unit to verstage on PSP all-y += config.c all-y += aoac.c -- To view, visit https://review.coreboot.org/c/coreboot/+/48521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15fb66e796cab48737ba5ac463c4c973794a005a Gerrit-Change-Number: 48521 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: use all-y for aoac target
by Felix Held (Code Review) 10 Dec '20

10 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48506 ) Change subject: soc/amd/picasso: use all-y for aoac target ...................................................................... soc/amd/picasso: use all-y for aoac target Since aoac gets also linked into verstage on PSP, all-y can be used here. Change-Id: I74607123ebc8115aa7efbb9a364d9632372b52cb Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/Makefile.inc 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/48506/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 6e1d88b..7cbae92 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -10,9 +10,9 @@ subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage all-y += config.c +all-y += aoac.c bootblock-y += bootblock.c -bootblock-y += aoac.c bootblock-y += early_fch.c bootblock-y += i2c.c bootblock-y += uart.c @@ -27,12 +27,10 @@ romstage-y += memmap.c romstage-y += uart.c romstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c -romstage-y += aoac.c romstage-y += psp.c romstage-y += mrc_cache.c verstage-y += i2c.c -verstage-y += aoac.c verstage_x86-y += gpio.c verstage_x86-y += uart.c verstage_x86-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c @@ -47,7 +45,6 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c ramstage-y += gpio.c -ramstage-y += aoac.c ramstage-y += fch.c ramstage-y += reset.c ramstage-y += acp.c -- To view, visit https://review.coreboot.org/c/coreboot/+/48506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74607123ebc8115aa7efbb9a364d9632372b52cb Gerrit-Change-Number: 48506 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/aoac: only check FCH_AOAC_UART_FOR_CONSOLE if used
by Felix Held (Code Review) 10 Dec '20

10 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48485 ) Change subject: soc/amd/picasso/aoac: only check FCH_AOAC_UART_FOR_CONSOLE if used ...................................................................... soc/amd/picasso/aoac: only check FCH_AOAC_UART_FOR_CONSOLE if used FCH_AOAC_UART_FOR_CONSOLE will only be used in the code if PICASSO_CONSOLE_UART is selected, so only check if it's a valid value in this case. Change-Id: I103dd8d469a084c7dc7dcf55175b1f77f900adc5 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/aoac.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/48485/1 diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c index 7fd839b..c97700d 100644 --- a/src/soc/amd/picasso/aoac.c +++ b/src/soc/amd/picasso/aoac.c @@ -12,7 +12,7 @@ : CONFIG_UART_FOR_CONSOLE == 2 ? FCH_AOAC_DEV_UART2 \ : CONFIG_UART_FOR_CONSOLE == 3 ? FCH_AOAC_DEV_UART3 \ : -1) -#if FCH_AOAC_UART_FOR_CONSOLE == -1 +#if CONFIG(PICASSO_CONSOLE_UART) && FCH_AOAC_UART_FOR_CONSOLE == -1 # error Unsupported UART_FOR_CONSOLE chosen #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I103dd8d469a084c7dc7dcf55175b1f77f900adc5 Gerrit-Change-Number: 48485 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/voxel: change speaker smart amplifier to ALC1011
by Sheng-Liang Pan (Code Review) 10 Dec '20

10 Dec '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43549 ) Change subject: mb/google/volteer/var/voxel: change speaker smart amplifier to ALC1011 ...................................................................... mb/google/volteer/var/voxel: change speaker smart amplifier to ALC1011 voxel change amp to ALC1011 adding ALC1011 amp acpi info into devicetree BUG=b:160550394 BRANCH=None TEST=build and verify ALC1011 can be recognized. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: If3e7b829000a61a27f6a45a2688bb434e57f479a --- M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/variants/voxel/overridetree.cb 3 files changed, 15 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/43549/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 06bbc58..a3ece12 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -37,6 +37,8 @@ bool "-> Voxel" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + select CHROMEOS_DSM_CALIB + select DRIVERS_I2C_RT1011 config BOARD_GOOGLE_DELBIN bool "-> Delbin" diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 61e20f4..6cbde24 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -72,7 +72,8 @@ gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); } if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S)) || - fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S))) { + fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S)) || + fw_config_probe(FW_CONFIG(AUDIO, RT1011_ALC5682I_I2S))) { printk(BIOS_INFO, "Configure GPIOs for I2S audio.\n"); gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 2219de0..8838705 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -12,24 +12,23 @@ register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" device i2c 1a on + probe AUDIO RT1011_ALC5682I_I2S end end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "0" - register "imon_slot_no" = "1" + chip drivers/i2c/rt1011 + register "desc" = ""RT1011 Woofer Left Speaker Amp"" register "uid" = "0" - register "desc" = ""Right Speaker Amp"" - register "name" = ""MAXR"" - device i2c 31 on + register "name" = ""RTWL"" + device i2c 38 on + probe AUDIO RT1011_ALC5682I_I2S end end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "2" - register "imon_slot_no" = "3" + chip drivers/i2c/rt1011 + register "desc" = ""RT1011 Woofer Right Speaker Amp"" register "uid" = "1" - register "desc" = ""Left Speaker Amp"" - register "name" = ""MAXL"" - device i2c 32 on + register "name" = ""RTWR"" + device i2c 39 on + probe AUDIO RT1011_ALC5682I_I2S end end end # I2C #0 0xA0E8 -- To view, visit https://review.coreboot.org/c/coreboot/+/43549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3e7b829000a61a27f6a45a2688bb434e57f479a Gerrit-Change-Number: 43549 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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