coreboot-gerrit December 2020

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Change in coreboot[master]: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
by Tim Wawrzynczak (Code Review) 11 Dec '20

11 Dec '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48281 ) Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/ro… File src/soc/intel/tigerlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/ro… PS4, Line 136: fsp_memory_init(s3wake); : pmc_set_disb(); : if (!s3wake) { : if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) : cse_fw_sync(); Is there a dependency on having FSP-M run before this? The HECI interface was initialized just before this on line 133 -- To view, visit https://review.coreboot.org/c/coreboot/+/48281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856 Gerrit-Change-Number: 48281 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Dec 2020 23:23:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Add data fabric read helper function
by Felix Held (Code Review) 10 Dec '20

10 Dec '20

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47726 ) Change subject: soc/amd/picasso: Add data fabric read helper function ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1 Gerrit-Change-Number: 47726 Gerrit-PatchSet: 4 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Dec 2020 21:51:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Add data fabric read helper function
by Marshall Dawson (Code Review) 10 Dec '20

10 Dec '20

Marshall Dawson has uploaded a new patch set (#4) to the change originally created by Jason Glenesk. ( https://review.coreboot.org/c/coreboot/+/47726 ) Change subject: soc/amd/picasso: Add data fabric read helper function ...................................................................... soc/amd/picasso: Add data fabric read helper function Add new helper function to support reading a register from the data fabric. BUG=b:155307433 TEST=Boot trembyle with If64fd624597b2ced014ba7f0332a6a48143c0e8c and confirm read values match expected values. BRANCH=Zork Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1 Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M src/soc/amd/picasso/data_fabric.c M src/soc/amd/picasso/include/soc/data_fabric.h 2 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/47726/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/47726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1 Gerrit-Change-Number: 47726 Gerrit-PatchSet: 4 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Move CSE Lite driver functionality into romstage
by Sridhar Siricilla (Code Review) 10 Dec '20

10 Dec '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48279 ) Change subject: soc/intel/common: Move CSE Lite driver functionality into romstage ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/48279/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/48279/2//COMMIT_MSG@10 PS2, Line 10: triggeres > triggers Ack https://review.coreboot.org/c/coreboot/+/48279/2//COMMIT_MSG@13 PS2, Line 13: Verified on JSL and TGL platforms > For bookkeeping: did you check how much boot time is saved because of the reset being done earlier? Plan is to measure delta time between from romstage(after DRAM init) to ramstage(existing code location) when CSE boots from RO on cold reset. This delta will be boot improvement time. I will have latest numbers tomorrow. -- To view, visit https://review.coreboot.org/c/coreboot/+/48279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73 Gerrit-Change-Number: 48279 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Dec 2020 21:25:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Move CSE Lite driver functionality into romstage
by Sridhar Siricilla (Code Review) 10 Dec '20

10 Dec '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Jamie Ryu, Tim Wawrzynczak, Rizwan Qureshi, Sugnan Prabhu S, Krishna P Bhat D, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48279 to look at the new patch set (#3). Change subject: soc/intel/common: Move CSE Lite driver functionality into romstage ...................................................................... soc/intel/common: Move CSE Lite driver functionality into romstage The patch sets up the CSE Lite driver in the romstage instead of ramstage. With this change, CSE Lite driver sets CSE's boot partition and triggers CSE FW update in the romstage. Test=Verified on JSL and TGL platforms BUG=b:174694480 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73 --- M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/48279/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/48279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73 Gerrit-Change-Number: 48279 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the...
by Sridhar Siricilla (Code Review) 10 Dec '20

10 Dec '20

Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Tim Wawrzynczak, Paul Menzel, Sugnan Prabhu S, Rizwan Qureshi, Krishna P Bhat D, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48280 to look at the new patch set (#3). Change subject: soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage ...................................................................... soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage This patch sets up cse_fw_sync() call in the romstage. BUG=b:174694480 Test=Verified on Drawlet Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a --- M src/soc/intel/jasperlake/romstage/romstage.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/48280/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/48280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a Gerrit-Change-Number: 48280 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
by Sridhar Siricilla (Code Review) 10 Dec '20

10 Dec '20

Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Paul Menzel, Tim Wawrzynczak, Rizwan Qureshi, Sugnan Prabhu S, Krishna P Bhat D, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/48281 to look at the new patch set (#3). Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage ...................................................................... soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage This patch sets up cse_fw_sync() call in the romstage. BUG=b:174694480 Test=Verified on Tigerlake platform Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856 --- M src/soc/intel/tigerlake/romstage/romstage.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/48281/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/48281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856 Gerrit-Change-Number: 48281 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/uart: rework to use dummy device
by Furquan Shaikh (Code Review) 10 Dec '20

10 Dec '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48385 ) Change subject: soc/intel/common/block/uart: rework to use dummy device ...................................................................... Patch Set 3: > Patch Set 3: > > > Patch Set 3: > > > > > > > You really should check the history of drivers/wifi/generic, commit d436750 for example... > > > > > > > > Well, the history is one thing. The current code is what > > > > matters however. How about you read that? > > > > > > I did ;) Actually I meant that one change, the wording is just misleading > > > > One major difference in the way UART driver is being handled in this CL and how CNVi device is handled is: > > For CNVi: > > - PCI operations are still performed as part of the PCI driver for the CNVi controller > > - ACPI operations are performed as part of the chip driver written for the dummy device under CNVi controller > > > > For UART: > > - This change performs PCI and ACPI operations on the parent of the dummy device. This does not work for the platforms that do not add the dummy device in devicetree/overridetree. > > So, that's actually what I had marked here already, right? https://review.coreboot.org/c/coreboot/+/48385/1/src/soc/intel/common/block… You are going to need to allow PCI ops on the PCI device directly. And the separate chip driver for the dummy device will perform ACPI ops only. That will allow other mainboards to not use the dummy device at all. The way it is written currently in the link you pasted above - it assumes that the PCI device is always a parent of the dummy device which is not true for any other mainboards and hence it breaks the behavior. -- To view, visit https://review.coreboot.org/c/coreboot/+/48385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9c9398829b52e6b0523504b862aae9aff559bc7 Gerrit-Change-Number: 48385 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 10 Dec 2020 18:43:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ==== 2nd gen
by Marshall Dawson (Code Review) 10 Dec '20

10 Dec '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48545 ) Change subject: ==== 2nd gen ...................................................................... ==== 2nd gen Change-Id: I60e363da6ee6e22dbdf314c856cc5e3f1b0e776a --- M util/amdfwtool/amdfwtool.c 1 file changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/48545/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 36d669b..401cf20 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -323,6 +323,13 @@ { .type = AMD_BIOS_INVALID }, }; +struct second_gen_efs { /* todo: expand for Server products */ + int gen:1; /* Client products only use bit 0 */ + int reserved:31; +} __attribute__((packed)); + +#define EFS_SECOND_GEN 0 + typedef struct _embedded_firmware { uint32_t signature; /* 0x55aa55aa */ uint32_t imc_entry; @@ -333,7 +340,7 @@ uint32_t bios0_entry; /* todo: add way to select correct entry */ uint32_t bios1_entry; uint32_t bios2_entry; - uint32_t second_gen_efs; /* Client SKUs b0=1 is Gen1, b1=0 is Gen2, Servers TBD */ + struct second_gen_efs efs_gen; uint32_t bios3_entry; uint32_t reserved_2Ch; uint32_t promontory_fw_ptr; @@ -1187,6 +1194,8 @@ break; case PLATFORM_RAVEN: case PLATFORM_PICASSO: + /* amd_romsig->efs_gen introduced after RAVEN/PICASSO. + * Leave as 0xffffffff for first gen */ amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; switch (efs_spi_micron_flag) { @@ -1203,7 +1212,7 @@ break; case PLATFORM_RENOIR: case PLATFORM_LUCIENNE: - amd_romsig->second_gen_efs = 0xfffffffe; + amd_romsig->efs_gen.gen = EFS_SECOND_GEN; amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; switch (efs_spi_micron_flag) { -- To view, visit https://review.coreboot.org/c/coreboot/+/48545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60e363da6ee6e22dbdf314c856cc5e3f1b0e776a Gerrit-Change-Number: 48545 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM
by Duncan Laurie (Code Review) 10 Dec '20

10 Dec '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47682 ) Change subject: drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM ...................................................................... drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM Configure the CFG2 register to set the latency to <64us in order to ensure the L1 exit latency is consistent across devices and that L1 ASPM is always enabled. BUG=b:173207454 TEST=Verify the device and link capability and control for L1: DevCap: Latency L1 <64us LnkCap: Latency L1 <64us LnkCtl: ASPM L1 Enabled Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: Ie2b85a6697f164fbe4f84d8cd5acb2b5911ca7a9 --- M src/drivers/genesyslogic/gl9755/gl9755.c M src/drivers/genesyslogic/gl9755/gl9755.h 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47682/1 diff --git a/src/drivers/genesyslogic/gl9755/gl9755.c b/src/drivers/genesyslogic/gl9755/gl9755.c index c3cdef1..ed76457 100644 --- a/src/drivers/genesyslogic/gl9755/gl9755.c +++ b/src/drivers/genesyslogic/gl9755/gl9755.c @@ -12,13 +12,23 @@ static void gl9755_init(struct device *dev) { + uint32_t reg; + printk(BIOS_INFO, "GL9755: init\n"); pci_dev_init(dev); /* Set Vendor Config to be configurable */ pci_or_config32(dev, CFG, CFG_EN); + /* Set LTR value */ pci_write_config32(dev, LTR, NO_SNOOP_SCALE|NO_SNOOP_VALUE|SNOOP_SCALE|SNOOP_VALUE); + + /* Adjust L1 exit latency to enable ASPM */ + reg = pci_read_config32(dev, CFG2); + reg &= ~CFG2_LAT_L1_MASK; + reg |= CFG2_LAT_L1_ASPM; + pci_write_config32(dev, CFG2, reg); + /* Set Vendor Config to be non-configurable */ pci_and_config32(dev, CFG, ~CFG_EN); } diff --git a/src/drivers/genesyslogic/gl9755/gl9755.h b/src/drivers/genesyslogic/gl9755/gl9755.h index 2d20faf..0492fab 100644 --- a/src/drivers/genesyslogic/gl9755/gl9755.h +++ b/src/drivers/genesyslogic/gl9755/gl9755.h @@ -1,11 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef DRIVERS_GENESYSLOGIC_GL9755_H +#define DRIVERS_GENESYSLOGIC_GL9755_H + /* Definitions for Genesys Logic GL9755 */ #define CFG 0x800 #define CFG_EN 0x1 +#define CFG2 0x48 +#define CFG2_LAT_L1_MASK ((0x7 << 12) | (0x7 << 3)) +#define CFG2_LAT_L1_ASPM ((0x6 << 12) | (0x6 << 3)) #define LTR 0x5C #define SNOOP_VALUE 0x25 #define SNOOP_SCALE (0x3 << 10) #define NO_SNOOP_VALUE (0x25 << 16) #define NO_SNOOP_SCALE (0x3 << 26) + +#endif /* DRIVERS_GENESYSLOGIC_GL9755_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b85a6697f164fbe4f84d8cd5acb2b5911ca7a9 Gerrit-Change-Number: 47682 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit December 2020