coreboot-gerrit December 2020

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Change in coreboot[master]: soc/intel/{skl,cnl}: add NMI_{EN,STS} registers
by Tim Wawrzynczak (Code Review) 01 Dec '20

01 Dec '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48091 ) Change subject: soc/intel/{skl,cnl}: add NMI_{EN,STS} registers ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/48091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d57ae89423bdaacf84f0bb0282bbb1c9df94598 Gerrit-Change-Number: 48091 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Dec 2020 16:35:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/64bit/entry64: Use ramstage code segment in ramstage
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48176 ) Change subject: cpu/x86/64bit/entry64: Use ramstage code segment in ramstage ...................................................................... cpu/x86/64bit/entry64: Use ramstage code segment in ramstage Change-Id: I232370dd92f11e7ce897d41514cced751c7e573d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/entry64.inc 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/48176/1 diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 65c0fdc..1376fcc 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -14,9 +14,15 @@ #if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0 #error pagetables must be 4KiB aligned! #endif +#if defined(__RAMSTAGE__) +#include <arch/ram_segs.h> +#define CODE_SEG64 RAM_CODE_SEG64 +#else +#include <arch/rom_segs.h> +#define CODE_SEG64 ROM_CODE_SEG64 +#endif #include <cpu/x86/msr.h> -#include <arch/rom_segs.h> setup_longmode: /* Get page table address */ @@ -42,7 +48,7 @@ movl %eax, %cr0 /* use long jump to switch to 64-bit code segment */ - ljmp $ROM_CODE_SEG64, $__longmode_start + ljmp $CODE_SEG64, $__longmode_start .code64 __longmode_start: -- To view, visit https://review.coreboot.org/c/coreboot/+/48176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232370dd92f11e7ce897d41514cced751c7e573d Gerrit-Change-Number: 48176 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/smm/smihandler: Fix compilation under x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48172 ) Change subject: soc/intel/common/block/smm/smihandler: Fix compilation under x86_64 ...................................................................... soc/intel/common/block/smm/smihandler: Fix compilation under x86_64 Change-Id: Ie44ded11a6a9ddd2a1163d2f57dad6935e1ea167 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/smm/smihandler.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/48172/1 diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 270b1aa..74d5719 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -292,7 +292,7 @@ { u8 sub_command, ret; void *io_smi; - uint32_t reg_ebx; + uintptr_t reg_ebx; io_smi = find_save_state(save_state_ops, APM_CNT_SMMSTORE); if (!io_smi) @@ -409,7 +409,7 @@ if ((pm1_sts & PWRBTN_STS) && (pm1_en & PWRBTN_EN)) { /* power button pressed */ elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); - pmc_disable_pm1_control(-1UL); + pmc_disable_pm1_control(~0); pmc_enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie44ded11a6a9ddd2a1163d2f57dad6935e1ea167 Gerrit-Change-Number: 48172 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/cpu/car/exit_car: Fix compilation on x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48171 ) Change subject: soc/intel/common/block/cpu/car/exit_car: Fix compilation on x86_64 ...................................................................... soc/intel/common/block/cpu/car/exit_car: Fix compilation on x86_64 Change-Id: Ieac4a4924ff4684b2a419471cd54e3d3b1f5bbe6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/cpu/car/exit_car.S 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/48171/1 diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 9480a5a..191232a 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -28,7 +28,11 @@ * Retrieve return address from stack as it will get trashed below if * execution is utilizing the cache-as-ram stack. */ +#if ENV_X86_64 + pop %rbx +#else pop %ebx +#endif /* Disable MTRRs. */ mov $(MTRR_DEF_TYPE_MSR), %ecx @@ -95,4 +99,8 @@ #endif /* Return to caller. */ +#if ENV_X86_64 + jmp *%rbx +#else jmp *%ebx +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieac4a4924ff4684b2a419471cd54e3d3b1f5bbe6 Gerrit-Change-Number: 48171 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/cpu/car/cache_as_ram: Fix compilation on x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48170 ) Change subject: soc/intel/common/block/cpu/car/cache_as_ram: Fix compilation on x86_64 ...................................................................... soc/intel/common/block/cpu/car/cache_as_ram: Fix compilation on x86_64 Change-Id: I1b36ca8816dab9d30754aadd230c136978e3b344 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/48170/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 5af1fc6..167342f 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -9,6 +9,7 @@ #include <rules.h> #include <intelblocks/msr.h> +.code32 .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -161,6 +162,15 @@ /* Need to align stack to 16 bytes at call instruction. Account for the two pushes below. */ andl $0xfffffff0, %esp + +#if ENV_X86_64 + #include <cpu/x86/64bit/entry64.inc> + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + movd %mm0, %rsi +#else sub $8, %esp /* push TSC value to stack */ @@ -168,6 +178,7 @@ pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif before_carstage: post_code(0x2A) -- To view, visit https://review.coreboot.org/c/coreboot/+/48170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b36ca8816dab9d30754aadd230c136978e3b344 Gerrit-Change-Number: 48170 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/aspeed/common/ast: Fix compilation under x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48169 ) Change subject: drivers/aspeed/common/ast: Fix compilation under x86_64 ...................................................................... drivers/aspeed/common/ast: Fix compilation under x86_64 Change-Id: I5fb6594ff83904df02083bcbea14b2d0b89cd9dd Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/aspeed/common/ast_mode_corebootfb.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/48169/1 diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index bf974ff..bb30d20 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -32,7 +32,7 @@ return -ENOMEM; } - fb->mmio_addr = (u32)res2mmio(res, 4095, 4095); + fb->mmio_addr = (uintptr_t)res2mmio(res, 4095, 4095); ast_set_offset_reg(crtc); ast_set_start_address_crt1(ast, fb->mmio_addr); @@ -230,7 +230,7 @@ set_vbe_mode_info_valid(&edid, fb.mmio_addr); /* Clear display */ - memset((void *)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); + memset((void *)(uintptr_t)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/48169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fb6594ff83904df02083bcbea14b2d0b89cd9dd Gerrit-Change-Number: 48169 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0/notify: Fix compilation under x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48168 ) Change subject: drivers/intel/fsp2_0/notify: Fix compilation under x86_64 ...................................................................... drivers/intel/fsp2_0/notify: Fix compilation under x86_64 Change-Id: Id63b9b372bf23e80e25b7dbef09d1b8bfa9be069 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp2_0/notify.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/48168/1 diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 76cdf12..ee04630 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -57,7 +57,7 @@ static void fsp_notify_dummy(void *arg) { - enum fsp_notify_phase phase = (uint32_t)arg; + enum fsp_notify_phase phase = (uint32_t)(uintptr_t)arg; display_mtrrs(); -- To view, visit https://review.coreboot.org/c/coreboot/+/48168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id63b9b372bf23e80e25b7dbef09d1b8bfa9be069 Gerrit-Change-Number: 48168 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/systemagent: Fix compilation on x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48167 ) Change subject: soc/intel/common/block/systemagent: Fix compilation on x86_64 ...................................................................... soc/intel/common/block/systemagent: Fix compilation on x86_64 Change-Id: Ibc8dc1cf33f594284edb82d4730967e077739c3c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/common/block/systemagent/systemagent_early.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/48167/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 53d6077..ca11ee6 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -95,8 +95,8 @@ base = fixed_set_resources[i].base; index = fixed_set_resources[i].index; if (base >> 32) - write32((void *)(MCH_BASE_ADDRESS + index + 4), base >> 32); - write32((void *)(MCH_BASE_ADDRESS + index), (base & 0xffffffff) | 1); + write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index + 4), base >> 32); + write32((void *)(uintptr_t)(MCH_BASE_ADDRESS + index), (base & 0xffffffff) | 1); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc8dc1cf33f594284edb82d4730967e077739c3c Gerrit-Change-Number: 48167 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/reg_script: Add cast to fix compilation on x86_64
by Patrick Rudolph (Code Review) 01 Dec '20

01 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48166 ) Change subject: lib/reg_script: Add cast to fix compilation on x86_64 ...................................................................... lib/reg_script: Add cast to fix compilation on x86_64 Change-Id: Ia713e7dbe8c75b764f7a4ef1a029e64fb2d321fb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/lib/reg_script.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/48166/1 diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index e0ae68c..bad9d9c 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -150,11 +150,11 @@ switch (step->size) { case REG_SCRIPT_SIZE_8: - return read8((u8 *)step->reg); + return read8((u8 *)(uintptr_t)step->reg); case REG_SCRIPT_SIZE_16: - return read16((u16 *)step->reg); + return read16((u16 *)(uintptr_t)step->reg); case REG_SCRIPT_SIZE_32: - return read32((u32 *)step->reg); + return read32((u32 *)(uintptr_t)step->reg); } return 0; } @@ -165,13 +165,13 @@ switch (step->size) { case REG_SCRIPT_SIZE_8: - write8((u8 *)step->reg, step->value); + write8((u8 *)(uintptr_t)step->reg, step->value); break; case REG_SCRIPT_SIZE_16: - write16((u16 *)step->reg, step->value); + write16((u16 *)(uintptr_t)step->reg, step->value); break; case REG_SCRIPT_SIZE_32: - write32((u32 *)step->reg, step->value); + write32((u32 *)(uintptr_t)step->reg, step->value); break; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/48166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia713e7dbe8c75b764f7a4ef1a029e64fb2d321fb Gerrit-Change-Number: 48166 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/jslrvp: Modify the flash layout for fsp debug build
by Paul Fagerburg (Code Review) 01 Dec '20

01 Dec '20

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48154 ) Change subject: mb/intel/jslrvp: Modify the flash layout for fsp debug build ...................................................................... mb/intel/jslrvp: Modify the flash layout for fsp debug build Current flash layout doesn't support the fsp debug builds since the FW_MAIN_A/B doesn't have enough space to hold the fsp debug binaries along with ME RW binaries. This patch reduces the SI_ALL size to 3.5MiB and increase the SI_BIOS to 12.5MiB to include both ME RW and FSP debug binaries. BRANCH=dedede TEST=Build and Boot jslrvp with fsp debug enabled coreboot. Cq-Depend: chrome-internal:3425366 Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48154 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/intel/jasperlake_rvp/chromeos.fmd 1 file changed, 25 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Maulik V Vaghela: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, but someone else must approve Ronak Kanabar: Looks good to me, approved diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index 57be7f1..e4e0b24 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -1,37 +1,38 @@ FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x600000 { + SI_ALL@0x0 0x381000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x57F000 + SI_ME@0x81000 0x300000 } - SI_BIOS@0x600000 0xA00000 { - RW_SECTION_A@0x0 0x2d0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x12ffc0 - RW_FWID_A@0x13ffc0 0x40 - ME_RW_A(CBFS)@0x140000 0x190000 + SI_BIOS@0x381000 0xc7f000 { + RW_LEGACY(CBFS)@0x0 0x100000 + RW_SECTION_A@0x100000 0x3a4800 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x2127c0 + RW_FWID_A@0x2147c0 0x40 + ME_RW_A(CBFS)@0x214800 0x190000 } - RW_SECTION_B@0x2d0000 0x2d0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x12ffc0 - RW_FWID_B@0x13ffc0 0x40 - ME_RW_B(CBFS)@0x140000 0x190000 + RW_SECTION_B@0x4a4800 0x3a4800 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x2127c0 + RW_FWID_B@0x2147c0 0x40 + ME_RW_B(CBFS)@0x214800 0x190000 } - RW_MISC@0x5a0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { + RW_MISC@0x849000 0x36000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 + RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_ELOG(PRESERVE)@0x30000 0x1000 + RW_SHARED@0x31000 0x1000 { + SHARED_DATA@0x0 0x1000 } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_VPD(PRESERVE)@0x32000 0x2000 + RW_NVRAM(PRESERVE)@0x34000 0x2000 } - RW_LEGACY(CBFS)@0x5d0000 0x30000 - WP_RO@0x600000 0x400000 { + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x87f000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800 -- To view, visit https://review.coreboot.org/c/coreboot/+/48154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Gerrit-Change-Number: 48154 Gerrit-PatchSet: 5 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2020