Change in coreboot[master]: mb/intel/ehlcrb: Add initial mainboard code - coreboot-gerrit

18 Nov 2020

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47707 )
Change subject: mb/intel/ehlcrb: Add initial mainboard code
......................................................................
mb/intel/ehlcrb: Add initial mainboard code
This is a initial mainboard code cloned entirely from jasperlake_rvp
aimed to serve as base for further mainboard check-ins.
This patch is based on TGL_upstream series patches:
https://review.coreboot.org/c/coreboot/+/37868
List of changes on top off initial jasperlake_rvp clone:
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Replace "jslrvp" with "ehlcrb"
4. Remove unwanted SPD file, add empty SPD as placeholder
6. Empty romstage_fsp_params.c, to fill it later with SOC specific
   config
7. Empty GPIO configurations, to be filled as per board
8. Empty memory.c configurations, to be filled as per board
9. Add board support namely BOARD_INTEL_ELKHARTLAKE_CRB
10. Replace jslrvp variant with ehlcrb variant
Changes to follow on top of this:
 1. Add correct memory parameters, add SPDs
 2. Clean up devicetree as per tigerlake SOC
 3. Add GPIO support
 4. Update ehl fmd file to replace 32MB chromeos.fmd
Signed-off-by: Tan, Lean Sheng lean.sheng.tan@intel.com
Change-Id: I2cbe9f12468318680b148739edec5222582e42a0
---
A src/mainboard/intel/elkhartlake_crb/Kconfig
A src/mainboard/intel/elkhartlake_crb/Kconfig.name
A src/mainboard/intel/elkhartlake_crb/Makefile.inc
A src/mainboard/intel/elkhartlake_crb/board_id.c
A src/mainboard/intel/elkhartlake_crb/board_id.h
A src/mainboard/intel/elkhartlake_crb/board_info.txt
A src/mainboard/intel/elkhartlake_crb/bootblock.c
A src/mainboard/intel/elkhartlake_crb/chromeos.c
A src/mainboard/intel/elkhartlake_crb/chromeos.fmd
A src/mainboard/intel/elkhartlake_crb/dsdt.asl
A src/mainboard/intel/elkhartlake_crb/mainboard.c
A src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c
A src/mainboard/intel/elkhartlake_crb/smihandler.c
A src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc
A src/mainboard/intel/elkhartlake_crb/spd/empty.spd.hex
A src/mainboard/intel/elkhartlake_crb/spd/spd.h
A src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/ec.h
A src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/gpio.h
A src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h
A src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/Makefile.inc
A src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
A src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c
A src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c
23 files changed, 1,091 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/47707/1

diff --git a/src/mainboard/intel/elkhartlake_crb/Kconfig b/src/mainboard/intel/elkhartlake_crb/Kconfig
new file mode 100644
index 0000000..6456df7
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/Kconfig
@@ -0,0 +1,75 @@
+if BOARD_INTEL_ELKHARTLAKE_CRB
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DPTF_USE_EISA_HID
+	select DRIVERS_I2C_DA7219
+	select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_DPTF
+	select DRIVERS_I2C_GENERIC
+	select DRIVERS_I2C_MAX98373
+	select DRIVERS_INTEL_MIPI_CAMERA
+	select DRIVERS_SPI_ACPI
+	select DRIVERS_USB_ACPI
+	select EC_ACPI
+	select HAVE_SPD_IN_CBFS
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_HAS_CHROMEOS
+	select SOC_INTEL_COMMON_BLOCK_IPU
+	select SOC_INTEL_ELKHARTLAKE
+	select SOC_INTEL_COMMON_BLOCK_DTT
+	select SOC_INTEL_CSE_LITE_SKU
+
+config MAINBOARD_DIR
+	string
+	default "intel/elkhartlake_crb"
+
+config VARIANT_DIR
+	string
+	default "ehlcrb" if BOARD_INTEL_ELKHARTLAKE_CRB
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "ehlcrb"
+
+config MAINBOARD_FAMILY
+	string
+	default "Intel_ehlcrb"
+
+config MAX_CPUS
+	int
+	default 8
+
+config DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config CHROMEOS
+	bool
+	default y
+	select GBB_FLAG_FORCE_DEV_SWITCH_ON
+	select GBB_FLAG_FORCE_DEV_BOOT_USB
+	select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
+	select GBB_FLAG_FORCE_MANUAL_RECOVERY
+	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
+	select HAS_RECOVERY_MRC_CACHE
+
+config VBOOT
+	select VBOOT_LID_SWITCH
+	select VBOOT_MOCK_SECDATA if !MAINBOARD_HAS_TPM2
+
+config UART_FOR_CONSOLE
+	int
+	default 2 if INTEL_LPSS_UART_FOR_CONSOLE
+	default 0
+
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 45  # GPE0_DW1_13 (GPP_H13)
+endif
diff --git a/src/mainboard/intel/elkhartlake_crb/Kconfig.name b/src/mainboard/intel/elkhartlake_crb/Kconfig.name
new file mode 100644
index 0000000..3a20b88
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_INTEL_ELKHARTLAKE_CRB
+	bool "Elkhartlake LPDDR4x CRB"
diff --git a/src/mainboard/intel/elkhartlake_crb/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/Makefile.inc
new file mode 100644
index 0000000..2ac1b07
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/Makefile.inc
@@ -0,0 +1,24 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+subdirs-y += spd
+
+bootblock-y += bootblock.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += romstage_fsp_params.c
+romstage-y += board_id.c
+
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += mainboard.c
+ramstage-y += board_id.c
+
+smm-y += smihandler.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+subdirs-y += variants/$(VARIANT_DIR)
diff --git a/src/mainboard/intel/elkhartlake_crb/board_id.c b/src/mainboard/intel/elkhartlake_crb/board_id.c
new file mode 100644
index 0000000..90609ff
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/board_id.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boardid.h>
+#include <ec/acpi/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <stdint.h>
+
+#include "board_id.h"
+
+static uint32_t get_board_id_via_ext_ec(void)
+{
+	uint32_t id = BOARD_ID_INIT;
+
+	if (google_chromeec_get_board_version(&id))
+		id = BOARD_ID_UNKNOWN;
+
+	return id;
+}
+
+/*
+ * Get Board ID via EC I/O port write/read
+ * Board id is 5 bit, so mask other bits while returning board id.
+ */
+int get_board_id(void)
+{
+	MAYBE_STATIC_NONZERO int id = -1;
+
+	if (id < 0) {
+		if (CONFIG(EC_GOOGLE_CHROMEEC)) {
+			id = get_board_id_via_ext_ec();
+		} else {
+			uint8_t buffer[2];
+			uint8_t index;
+			if (send_ec_command(EC_FAB_ID_CMD) == 0) {
+				for (index = 0; index < sizeof(buffer); index++)
+					buffer[index] = recv_ec_data();
+				id = (buffer[0] << 8) | buffer[1];
+			}
+		}
+	}
+
+	return (id & 0x1f);
+}
diff --git a/src/mainboard/intel/elkhartlake_crb/board_id.h b/src/mainboard/intel/elkhartlake_crb/board_id.h
new file mode 100644
index 0000000..85c7c85
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/board_id.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MAINBOARD_COMMON_BOARD_ID_H_
+#define _MAINBOARD_COMMON_BOARD_ID_H_
+
+/* Board/FAB ID Command */
+#define EC_FAB_ID_CMD	0x0D
+
+/*
+ * Returns board information (board id[15:8] and
+ * Fab info[7:0]) on success and < 0 on error
+ */
+int get_board_id(void);
+
+#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */
diff --git a/src/mainboard/intel/elkhartlake_crb/board_info.txt b/src/mainboard/intel/elkhartlake_crb/board_info.txt
new file mode 100644
index 0000000..f2c19c0
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: Elkhartlake crb
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/intel/elkhartlake_crb/bootblock.c b/src/mainboard/intel/elkhartlake_crb/bootblock.c
new file mode 100644
index 0000000..a8f7e41
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/bootblock.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+#include <soc/gpio.h>
+
+void bootblock_mainboard_init(void)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_early_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+}
diff --git a/src/mainboard/intel/elkhartlake_crb/chromeos.c b/src/mainboard/intel/elkhartlake_crb/chromeos.c
new file mode 100644
index 0000000..c59fac8
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/chromeos.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES)
+int get_lid_switch(void)
+{
+	/* Lid always open */
+	return 1;
+}
+
+int get_recovery_mode_switch(void)
+{
+	return 0;
+}
+
+#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */
+
+int get_write_protect_state(void)
+{
+	/* No write protect */
+	return 0;
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	const struct cros_gpio *gpios;
+	size_t num;
+
+	gpios = variant_cros_gpios(&num);
+	chromeos_acpi_gpio_generate(gpios, num);
+}
diff --git a/src/mainboard/intel/elkhartlake_crb/chromeos.fmd b/src/mainboard/intel/elkhartlake_crb/chromeos.fmd
new file mode 100644
index 0000000..05f4592
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/chromeos.fmd
@@ -0,0 +1,43 @@
+FLASH@0xff000000 0x1000000 {
+	SI_ALL@0x0 0x600000 {
+		SI_DESC@0x0 0x1000
+		SI_EC@0x1000 0x80000
+		SI_ME@0x81000 0x57F000
+	}
+	SI_BIOS@0x600000 0xA00000 {
+		RW_SECTION_A@0x0 0x2d0000 {
+			VBLOCK_A@0x0 0x10000
+			FW_MAIN_A(CBFS)@0x10000 0x2bffc0
+			RW_FWID_A@0x2cffc0 0x40
+		}
+		RW_SECTION_B@0x2d0000 0x2d0000 {
+			VBLOCK_B@0x0 0x10000
+			FW_MAIN_B(CBFS)@0x10000 0x2bffc0
+			RW_FWID_B@0x2cffc0 0x40
+		}
+		RW_MISC@0x5a0000 0x30000 {
+			UNIFIED_MRC_CACHE@0x0 0x20000 {
+				RECOVERY_MRC_CACHE@0x0 0x10000
+				RW_MRC_CACHE@0x10000 0x10000
+			}
+			RW_ELOG(PRESERVE)@0x20000 0x4000
+			RW_SHARED@0x24000 0x4000 {
+				SHARED_DATA@0x0 0x2000
+				VBLOCK_DEV@0x2000 0x2000
+			}
+			RW_VPD(PRESERVE)@0x28000 0x2000
+			RW_NVRAM(PRESERVE)@0x2a000 0x6000
+		}
+		RW_LEGACY(CBFS)@0x5d0000 0x30000
+		WP_RO@0x600000 0x400000 {
+			RO_VPD(PRESERVE)@0x0 0x4000
+			RO_SECTION@0x4000 0x3fc000 {
+				FMAP@0x0 0x800
+				RO_FRID@0x800 0x40
+				RO_FRID_PAD@0x840 0x7c0
+				GBB@0x1000 0x3000
+				COREBOOT(CBFS)@0x4000 0x3f8000
+			}
+		}
+	}
+}
diff --git a/src/mainboard/intel/elkhartlake_crb/dsdt.asl b/src/mainboard/intel/elkhartlake_crb/dsdt.asl
new file mode 100644
index 0000000..2faa511
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/dsdt.asl
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <baseboard/ec.h>
+#include <baseboard/gpio.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	/* OEM revision */
+)
+{
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+
+	/* global NVS and variables */
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	/* CPU */
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+			#include <soc/intel/elkhartlake/acpi/southbridge.asl>
+		}
+	}
+
+#if CONFIG(CHROMEOS)
+	/* Chrome OS specific */
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+#endif
+
+#if CONFIG(EC_GOOGLE_CHROMEEC)
+	/* Chrome OS Embedded Controller */
+	Scope (_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
+#endif
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/intel/elkhartlake_crb/mainboard.c b/src/mainboard/intel/elkhartlake_crb/mainboard.c
new file mode 100644
index 0000000..315d47d
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/mainboard.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <device/device.h>
+#include <intelblocks/pcr.h>
+#include <soc/gpio.h>
+#include <soc/pcr_ids.h>
+#include <smbios.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#define SERIAL_IO_PCR_GPPRVRW4	0x60C
+
+static void mainboard_init(void *chip_info)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+
+	if (CONFIG(DRIVERS_INTEL_MIPI_CAMERA))
+		pcr_write32(PID_SERIALIO, SERIAL_IO_PCR_GPPRVRW4, BIT8);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
+}
+
+const char *smbios_system_sku(void)
+{
+	static const char *sku_str = "sku2147483647"; /* sku{0-1} */
+	return sku_str;
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c
new file mode 100644
index 0000000..1354edf
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include "board_id.h"
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	/* ToDo : Fill FSP-M spd related memory params */
+}
diff --git a/src/mainboard/intel/elkhartlake_crb/smihandler.c b/src/mainboard/intel/elkhartlake_crb/smihandler.c
new file mode 100644
index 0000000..be0066a
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/smihandler.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/smm.h>
+#include <elog.h>
+#include <intelblocks/smihandler.h>
+#include <baseboard/ec.h>
+
+void mainboard_smi_espi_handler(void)
+{
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
+					MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
+
+	return 0;
+}
+
+void elog_gsmi_cb_mainboard_log_wake_source(void)
+{
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+					MAINBOARD_EC_S3_WAKE_EVENTS);
+}
diff --git a/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc
new file mode 100644
index 0000000..1af6515
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+SPD_SOURCES = empty	# 0b000
diff --git a/src/mainboard/intel/elkhartlake_crb/spd/empty.spd.hex b/src/mainboard/intel/elkhartlake_crb/spd/empty.spd.hex
new file mode 100644
index 0000000..67b46cd
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/spd/empty.spd.hex
@@ -0,0 +1,32 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/elkhartlake_crb/spd/spd.h b/src/mainboard/intel/elkhartlake_crb/spd/spd.h
new file mode 100644
index 0000000..f667e74
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/spd/spd.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#include <stdint.h>
+
+#define RCOMP_TARGET_PARAMS	0x5
+
+void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr);
+void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr);
+void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr);
+void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr);
+void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr);
+void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr);
+#endif
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 0000000..f05cb77
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <baseboard/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/*
+ * EC can wake from S3 with lid or power button or key press or
+ * mode change event.
+ */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN	GPE_EC_WAKE
+
+#define SIO_EC_MEMMAP_ENABLE	/* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE	/* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K      /* Enable PS/2 Keyboard */
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000..de0adf6
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI	GPE0_ESPI
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+
+#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000..b7603ccd
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* The next set of functions return the gpio table and fill in the number of
+ * entries for each table. */
+
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+const struct mb_cfg *variant_memcfg_config(uint8_t board_id);
+
+#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/Makefile.inc
new file mode 100644
index 0000000..641e814
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/Makefile.inc
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
new file mode 100644
index 0000000..4611685
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
@@ -0,0 +1,474 @@
+chip soc/intel/elkhartlake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_H"
+	register "pmc_gpe0_dw2" = "GPP_E"
+
+	# FSP configuration
+	register "SaGv" = "SaGv_Enabled"
+	register "SmbusEnable" = "1"
+	register "ScsEmmcHs400Enabled" = "1"
+	register "SdCardPowerEnableActiveHigh" = "1"
+
+	# Display related UPDs
+	# Select eDP for port A (1 = eDP, 2 = MIPI)
+	register "DdiPortAConfig" = "1"
+
+	# Enable HPD for DDI ports B/C
+	register "DdiPortBHpd" = "1"
+	register "DdiPortCHpd" = "1"
+
+	# Enable DDC for DDI ports B/C
+	register "DdiPortBDdc" = "1"
+	register "DdiPortCDdc" = "1"
+
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)"	# Type-C Port1
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC2)"		# USB2 Type A port1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Type-C Port2
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"		# USB2 Type A port2
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# USB2 Bluetooth
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# USB2 WWAN
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC2)"		# USB2 Type A port3
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC3)"		# USB2 Type A port4
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C Port1
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C Port2
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# USB3/2 Type A port1
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)"	# USB3 WWAN
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)"	# UNUSED
+	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# UNUSED
+
+	# Enable Pch iSCLK
+	register "pch_isclk" = "1"
+
+	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+
+	# Skip the CPU repalcement check
+	register "SkipCpuReplacementCheck" = "1"
+
+	register "PchHdaDspEnable" = "1"
+	register "PchHdaAudioLinkHdaEnable" = "0"
+	register "PchHdaAudioLinkSspEnable[0]" = "1"
+	register "PchHdaAudioLinkSspEnable[1]" = "1"
+	register "PchHdaAudioLinkDmicEnable[0]" = "1"
+	register "PchHdaAudioLinkDmicEnable[1]" = "1"
+
+	# PCIe port 1 for M.2 E-key WLAN
+	# Enable Root Port 4(x4) for NVMe
+	register "PcieRpEnable[1]" = "1"
+	register "PcieRpEnable[4]" = "1"
+
+	# Enable ClkReqDetect 1 for WLAN
+	# Enable ClkReqDetect 4 for NVMe
+	register "PcieRpClkReqDetect[1]" = "1"
+	register "PcieRpClkReqDetect[4]" = "1"
+
+	register "PcieClkSrcUsage[0]" = "0x04"
+	register "PcieClkSrcUsage[1]" = "0x01"
+	register "PcieClkSrcUsage[2]" = "0xFF"
+	register "PcieClkSrcUsage[3]" = "0xFF"
+	register "PcieClkSrcUsage[4]" = "0xFF"
+	register "PcieClkSrcUsage[5]" = "0xFF"
+
+	register "PcieClkSrcClkReq[0]" = "0x00"
+	register "PcieClkSrcClkReq[1]" = "0x01"
+	register "PcieClkSrcClkReq[2]" = "0x02"
+	register "PcieClkSrcClkReq[3]" = "0x03"
+	register "PcieClkSrcClkReq[4]" = "0x04"
+	register "PcieClkSrcClkReq[5]" = "0x05"
+
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+	}"
+
+	register "SerialIoGSpiMode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+	}"
+
+	register "SerialIoGSpiCsMode" = "{
+		[PchSerialIoIndexGSPI0] = 1,
+		[PchSerialIoIndexGSPI1] = 1,
+		[PchSerialIoIndexGSPI2] = 1,
+	}"
+
+	register "SerialIoGSpiCsState" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 0,
+		[PchSerialIoIndexGSPI2] = 0,
+	}"
+
+	register "SerialIoUartMode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
+	}"
+
+	# Enable DPTF
+	register "dptf_enable" = "1"
+
+	# Add PL1 and PL2 values
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 6,
+		.tdp_pl2_override = 20,
+	}"
+
+	# Enable S0ix
+	register "s0ix_enable" = "1"
+
+	# GPIO for SD card detect
+	register "sdcard_cd_gpio" = "VGPIO_39"
+
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.gspi[1] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.speed_config[0] = {
+				.speed = I2C_SPEED_FAST,
+				.scl_lcnt = 176,
+				.scl_hcnt = 95,
+				.sda_hold = 36,
+			}
+		},
+		.i2c[4] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	# Set the minimum assertion width
+	register "PchPmSlpS3MinAssert"  = "3"  # 50ms
+	register "PchPmSlpS4MinAssert"  = "1"  # 1s
+	register "PchPmSlpSusMinAssert" = "3"  # 1s
+	register "PchPmSlpAMinAssert"   = "3"  # 98ms
+
+	# NOTE: Duration programmed in the below register should never be smaller than the
+	# stretch duration programmed in the following registers -
+	#       - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
+	#       - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
+	#       - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
+	#       - PM_CFG.SLP_LAN_MIN_ASST_WDTH
+	register "PchPmPwrCycDur" = "1"       # 1s
+
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on
+			chip drivers/intel/dptf
+				register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 1000)"
+				register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 119, SHUTDOWN)"
+
+				register "controls.power_limits.pl1" = "{
+					.min_power = 3000,
+					.max_power = 6000,
+					.time_window_min = 1 * MSECS_PER_SEC,
+					.time_window_max = 1 * MSECS_PER_SEC,
+					.granularity = 200,}"
+				register "controls.power_limits.pl2" = "{
+					.min_power = 20000,
+					.max_power = 20000,
+					.time_window_min = 1 * MSECS_PER_SEC,
+					.time_window_max = 1 * MSECS_PER_SEC,
+					.granularity = 1000,}"
+				device generic 0 on end
+			end
+		end # SA Thermal device
+
+		device pci 05.0 on
+			chip drivers/intel/mipi_camera
+				register "acpi_uid" = "0x50000"
+				register "acpi_name" = ""IPU0""
+				register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
+
+				register "cio2_num_ports" = "2"
+				register "cio2_lanes_used" = "{2,2}"
+				register "cio2_lane_endpoint[0]" = ""^I2C4.CAM0""
+				register "cio2_lane_endpoint[1]" = ""^I2C5.CAM1""
+				register "cio2_prt[0]" = "0"
+				register "cio2_prt[1]" = "2"
+				device generic 0 on end
+			end
+		end
+		device pci 12.0 off end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 14.0 on
+			chip drivers/usb/acpi
+				register "desc" = ""Root Hub""
+				register "type" = "UPC_TYPE_HUB"
+				device usb 0.0 on
+					chip drivers/usb/acpi
+						register "desc" = ""USB3/2 Type-A Left Lower""
+						register "type" = "UPC_TYPE_A"
+						device usb 2.0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""WWAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 2.1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 2.2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB C Connector 1""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device usb 2.3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB C Connector 2""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device usb 2.4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB C Connector 3""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device usb 2.5 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB C Connector 4""
+						register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+						device usb 2.6 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3/2 Type-A Left Upper""
+						register "type" = "UPC_TYPE_A"
+						device usb 2.7 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3/2 Type-A Left Lower""
+						register "type" = "UPC_TYPE_A"
+						device usb 3.0 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3/2 Type-A Left Upper""
+						register "type" = "UPC_TYPE_A"
+						device usb 3.1 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""WLAN""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 3.2 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Port Unused1""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 3.3 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Port Unused2""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 3.4 on end
+					end
+					chip drivers/usb/acpi
+						register "desc" = ""USB3 Port Unused3""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 3.5 on end
+					end
+				end
+			end
+		end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 off end # PMC SRAM
+		device pci 14.3 on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end # CNVi wifi
+		device pci 14.5 on  end # SDCard
+		device pci 15.0 on
+			chip drivers/i2c/max98373
+				register "vmon_slot_no" = "4"
+				register "imon_slot_no" = "5"
+				register "uid" = "0"
+				register "desc" = ""RIGHT SPEAKER AMP""
+				register "name" = ""MAXR""
+				device i2c 31 on end
+			end
+			chip drivers/i2c/max98373
+				register "vmon_slot_no" = "6"
+				register "imon_slot_no" = "7"
+				register "uid" = "1"
+				register "desc" = ""LEFT SPEAKER AMP""
+				register "name" = ""MAXL""
+				device i2c 32 on end
+			end
+			chip drivers/i2c/da7219
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H16_IRQ)"
+				register "btn_cfg" = "50"
+				register "mic_det_thr" = "500"
+				register "jack_ins_deb" = "20"
+				register "jack_det_rate" = ""32ms_64ms""
+				register "jack_rem_deb" = "1"
+				register "a_d_btn_thr" = "0xa"
+				register "d_b_btn_thr" = "0x16"
+				register "b_c_btn_thr" = "0x21"
+				register "c_mic_btn_thr" = "0x3e"
+				register "btn_avg" = "4"
+				register "adc_1bit_rpt" = "1"
+				register "micbias_lvl" = "2600"
+				register "mic_amp_in_sel" = ""diff""
+				device i2c 1a on end
+			end
+		end # I2C #0 Audio
+		device pci 15.1 off end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 off end # I2C #3
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 off end # SATA
+		device pci 19.0 on # I2C #4 Cam 0
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI2740""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM0""
+				register "chip_name" = ""Ov 2740 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+				register "has_power_resource" = "1"
+
+				register "ssdb.lanes_used" = "2"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "360000000"
+				register "remote_name" = ""IPU0""
+
+				#Controls
+				register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_3
+				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D5" #reset
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_B14" #power
+
+				#_ON
+				register "on_seq.ops_cnt" = "4"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "3"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+
+				device i2c 10 on end
+			end
+		end
+		device pci 19.1 on # I2C #5 Cam 1 and VCM
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = ""OVTI5675""
+				register "acpi_uid" = "0"
+				register "acpi_name" = ""CAM1""
+				register "chip_name" = ""Ov 5675 Camera""
+				register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
+
+				register "ssdb.lanes_used" = "2"
+				register "ssdb.link_used" = "1"
+				register "ssdb.vcm_type" = "0x0C"
+				register "vcm_name" = ""VCM0""
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
+				register "remote_name" = ""IPU0""
+
+				register "has_power_resource" = "1"
+				#Controls
+				register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_3
+				register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
+
+				register "gpio_panel.gpio[0].gpio_num" = "GPP_D4" #power_enable
+				register "gpio_panel.gpio[1].gpio_num" = "GPP_C19" #reset
+
+				#_ON
+				register "on_seq.ops_cnt" = "4"
+				register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
+				register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)"
+				register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 5)"
+				register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 5)"
+
+				#_OFF
+				register "off_seq.ops_cnt" = "3"
+				register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
+				register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
+				register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
+
+				device i2c 36 on end
+			end
+			chip drivers/intel/mipi_camera
+				register "acpi_hid" = "ACPI_DT_NAMESPACE_HID"
+				register "acpi_uid" = "3"
+				register "acpi_name" = ""VCM0""
+				register "chip_name" = ""DW AF DAC""
+				register "device_type" = "INTEL_ACPI_CAMERA_VCM"
+
+				register "pr0" = ""\_SB.PCI0.I2C5.CAM1.PRIC""
+				register "vcm_compat" = ""dongwoon,dw9714""
+
+				register "ssdb.lanes_used" = "2"
+				register "num_freq_entries" = "1"
+				register "link_freq[0]" = "DEFAULT_LINK_FREQ"
+				register "remote_name" = ""IPU0""
+				device i2c 0C on end
+			end
+		end
+
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 on  end # eMMC
+		device pci 1c.0 off end # PCI Express Port 1
+		device pci 1c.1 on  end # PCI Express Port 2 - WLAN
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 on  end # PCI Express Port 5 - NVMe
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1e.0 on  end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_H13_IRQ)"
+				device spi 0 on end
+			end
+		end # GSPI #1
+		device pci 1f.0 on  end # eSPI Interface
+		device pci 1f.1 on  end # P2SB
+		device pci 1f.2 hidden end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c
new file mode 100644
index 0000000..f01202b
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/gpio.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+	/* ToDo: Fill gpio configurations */
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* ToDo: Fill early gpio configurations */
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
+};
+
+const struct cros_gpio *variant_cros_gpios(size_t *num)
+{
+	*num = ARRAY_SIZE(cros_gpios);
+	return cros_gpios;
+}
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c
new file mode 100644
index 0000000..e764fdc
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <baseboard/gpio.h>
+#include <gpio.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+
+/* ToDo : Fill EHL related memory configs */
+
+const struct mb_cfg *variant_memcfg_config(uint8_t board_id)
+{
+	/* ToDo : Fill EHL related memory configs */
+
+	die("unsupported board id : 0x%x\n", board_id);
+}
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2cbe9f12468318680b148739edec5222582e42a0
Gerrit-Change-Number: 47707
Gerrit-PatchSet: 1
Gerrit-Owner: Lean Sheng Tan lean.sheng.tan@intel.com
Gerrit-MessageType: newchange



    