coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3473 discussions

Change in coreboot[master]: src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM)
by Brandon Breitenstein (Code Review) 14 Oct '20

14 Oct '20

Hello Divya S Sasidharan, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/42078 to review the following change. Change subject: src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM) ...................................................................... src/ec/google/chromeec: Get Type-C Mux info from EC (TCPM) EC being the TCPM decides the mux configuration after negotiating with the port partner on the Type-C port. The APIS added here will give the current essential mux state information for a given port. BUG=None BRANCH=None TEST= Tested boots from USB Type-C flash drive and Type-C to Type-A dongle on Volteer Change-Id: If994a459288ef31b0e6da8c6cdfd0ce3a0303981 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_commands.h 3 files changed, 105 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/42078/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index a97dfb3..22e57d2 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1374,7 +1374,7 @@ return ec_image_type; } -int google_chromeec_get_num_pd_ports(int *num_ports) +int google_chromeec_get_num_pd_ports(uint8_t *num_ports) { struct ec_response_charge_port_count resp = {}; struct chromeec_command cmd = { @@ -1435,6 +1435,91 @@ return (google_chromeec_get_current_image() == EC_IMAGE_RO); } +int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, uint8_t *dp_mode) +{ + struct ec_params_usb_pd_control pd_control = { + .port = port, + .role = USB_PD_CTRL_ROLE_NO_CHANGE, + .mux = USB_PD_CTRL_ROLE_NO_CHANGE, + .swap = USB_PD_CTRL_SWAP_NONE, + }; + struct ec_response_usb_pd_control_v2 resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_USB_PD_CONTROL, + .cmd_version = 2, + .cmd_data_in = &pd_control, + .cmd_size_in = sizeof(pd_control), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd) < 0) + return -1; + + *ufp = (resp.cc_state == PD_CC_DFP_ATTACHED); + *dbg_acc = (resp.cc_state == PD_CC_DFP_DEBUG_ACC); + *dp_mode = resp.dp_mode; + + return 0; +} + +/** + * Return USB2 port mapping in bit 0:3 + * USB3 port mapping in bit 4:7 + */ +int google_chromeec_pd_get_port_info(int port, uint8_t *port_map) +{ + struct ec_params_locate_chip req = { + .type = EC_CHIP_TYPE_TCPC, + .index = port, + }; + struct ec_response_locate_chip resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_LOCATE_CHIP, + .cmd_version = 0, + .cmd_data_in = &req, + .cmd_size_in = sizeof(req), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + }; + + if (google_chromeec_command(&cmd) < 0) + return -1; + + *port_map = resp.reserved; + return 0; +} + +/** + * Check for the current mux state in EC + * Flags representing mux state can be + * found in ec_commands.h + */ +int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags) +{ + if (port < 0) + return -1; + struct ec_params_usb_pd_mux_info req_mux = { + .port = port, + }; + struct ec_response_usb_pd_mux_info resp_mux = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_USB_PD_MUX_INFO, + .cmd_version = 0, + .cmd_data_in = &req_mux, + .cmd_size_in = sizeof(req_mux), + .cmd_data_out = &resp_mux, + .cmd_size_out = sizeof(resp_mux), + .cmd_dev_index = 0, + }; + if (google_chromeec_command(&cmd) < 0) + return -1; + + *flags = resp_mux.flags; + return 0; +} + /** * Check if EC/TCPM is in an alternate mode or not. * @@ -1443,22 +1528,16 @@ */ int google_chromeec_pd_get_amode(uint16_t svid) { - struct ec_response_usb_pd_ports resp; - struct chromeec_command cmd = { - .cmd_code = EC_CMD_USB_PD_PORTS, - .cmd_version = 0, - .cmd_data_in = NULL, - .cmd_size_in = 0, - .cmd_data_out = &resp, - .cmd_size_out = sizeof(resp), - .cmd_dev_index = 0, - }; + uint8_t num_ports; + int ret; + struct chromeec_command cmd; int i; - if (google_chromeec_command(&cmd) < 0) + ret = google_chromeec_get_num_pd_ports(&num_ports); + if (ret < 0) return -1; - for (i = 0; i < resp.num_ports; i++) { + for (i = 0; i < num_ports; i++) { struct ec_params_usb_pd_get_mode_request params; struct ec_params_usb_pd_get_mode_response resp2; int svid_idx = 0; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index aead5f7..3d95c16 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -27,6 +27,17 @@ enum ec_image google_chromeec_get_current_image(void); void google_chromeec_init(void); int google_chromeec_pd_get_amode(uint16_t svid); +/* Check for the current mux state in EC */ +int google_chromeec_usb_get_pd_mux_info(int port, uint8_t *flags); +/* + * USB2 and USB3 port numbers between EC and AP + * is not one to one mapping, this function will return the + * correct mapped AP port number in port_map. + */ +int google_chromeec_pd_get_port_info(int port, uint8_t *port_map); +/* Returns data role and type of device connected */ +int google_chromeec_usb_pd_control(int port, bool *ufp, bool *dbg_acc, + uint8_t *dp_mode); int google_chromeec_wait_for_displayport(long timeout); /* Device events */ @@ -306,7 +317,7 @@ * of PD-capable USB ports according to the EC. * @return 0 on success, -1 on error */ -int google_chromeec_get_num_pd_ports(int *num_ports); +int google_chromeec_get_num_pd_ports(uint8_t *num_ports); /* Structure representing the capabilities of a USB-PD port */ struct usb_pd_port_caps { diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 62761a2..b4a8ee1 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -5331,10 +5331,6 @@ /* Active Link Uni-Direction */ #define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3) -/* - * Underdevelopement : - * Please remove this tag if using _v2 outside platform/ec - */ struct ec_response_usb_pd_control_v2 { uint8_t enabled; uint8_t role; @@ -5641,7 +5637,7 @@ #define USB_PD_MUX_DOCK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED) struct ec_response_usb_pd_mux_info { - uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */ + uint8_t flags; /* USB_PD_CTRL_*-encoded USB mux state */ } __ec_align1; #define EC_CMD_PD_CHIP_INFO 0x011B -- To view, visit https://review.coreboot.org/c/coreboot/+/42078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If994a459288ef31b0e6da8c6cdfd0ce3a0303981 Gerrit-Change-Number: 42078 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Divya S Sasidharan <divya.s.sasidharan(a)intel.com> Gerrit-MessageType: newchange

6 38

Change in coreboot[master]: soc/intel/common/block: Enable PMC IPC driver
by Brandon Breitenstein (Code Review) 14 Oct '20

14 Oct '20

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42077 ) Change subject: soc/intel/common/block: Enable PMC IPC driver ...................................................................... soc/intel/common/block: Enable PMC IPC driver In order for USB Type-C devices to be detected prior to loading Kernel PMC IPC driver API is needed to send IPC commands to the PMC to update connection/disconnection states. BUG=b:141608957 BRANCH=none TEST: built coreboot image and booted to Chrome OS Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 101 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/42077/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 2b06a50..f7e2c13 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -9,6 +9,27 @@ /* Forward declare the power state struct here */ struct chipset_power_state; +/* pmc_ipc_buffer struct declaration to be used for IPC commands */ +struct pmc_ipc_buffer { + uint32_t buf0; + uint32_t buf1; + uint32_t buf2; + uint32_t buf3; +}; + +/* pmc_ipc_cmd union declaration to store cmd data for IPC commands */ +union pmc_ipc_cmd { + uint32_t cmd_reg; + struct { + uint32_t cmd:8; + uint32_t msi:1; + uint32_t res_1:3; + uint32_t subcmd:4; + uint32_t len:8; + uint32_t res_2:8; + }; +}; + /* * This is implemented as weak function in common pmc lib. * Clears all power management related registers as the boot @@ -220,4 +241,10 @@ */ void pmc_set_power_failure_state(bool target_on); +/* + * Send PMC IPC command + */ +enum cb_err pmc_send_ipc_cmd(uint32_t cmd, struct pmc_ipc_buffer *wbuf, + struct pmc_ipc_buffer *rbuf); + #endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */ diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 12eb38e..818a36b 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -5,6 +5,7 @@ #include <device/mmio.h> #include <cbmem.h> #include <console/console.h> +#include <delay.h> #include <halt.h> #include <intelblocks/pmclib.h> #include <intelblocks/gpio.h> @@ -16,6 +17,26 @@ #include <stdint.h> #include <string.h> #include <timer.h> +#include <types.h> + +/* define the offsets of all WBUFs */ +#define PMC_IPC_WBUF0 0x80 +#define PMC_IPC_WBUF1 0x84 +#define PMC_IPC_WBUF2 0x88 +#define PMC_IPC_WBUF3 0x8C + +/* define the offsets of all RBUFs */ +#define PMC_IPC_RBUF0 0x90 +#define PMC_IPC_RBUF1 0x94 +#define PMC_IPC_RBUF2 0x98 +#define PMC_IPC_RBUF3 0x9C + +#define PMC_IPC_CMD_OFFSET 0x0 +#define PMC_IPC_USBC_CMD_ID 0xA7 +#define PMC_IPC_STS_OFFSET 0x4 +#define PMC_IPC_STS_BUSY BIT(0) +#define PMC_IPC_STS_ERR BIT(1) +#define PMC_IPC_XFER_TIMEOUT_MS 1000 /* max 1s*/ static struct chipset_power_state power_state; @@ -574,3 +595,56 @@ pmc_soc_set_afterg3_en(on); } + +static enum cb_err check_ipc_sts(uintptr_t pmcbase) +{ + struct stopwatch sw; + uint32_t ipcsts; + + stopwatch_init_msecs_expire(&sw, PMC_IPC_XFER_TIMEOUT_MS); + do { + ipcsts = read32((void *)(pmcbase + PMC_IPC_STS_OFFSET)); + if (ipcsts & PMC_IPC_STS_ERR) + return CB_ERR; + + udelay(1); + + } while (!stopwatch_expired(&sw) && (ipcsts & PMC_IPC_STS_BUSY)); + + if (ipcsts & PMC_IPC_STS_BUSY) { + printk(BIOS_ERR, "IPC Timeout after %d ms\n", PMC_IPC_XFER_TIMEOUT_MS); + return CB_ERR; + } + + return CB_SUCCESS; +} + +enum cb_err pmc_send_ipc_cmd(uint32_t cmd, struct pmc_ipc_buffer *wbuf, + struct pmc_ipc_buffer *rbuf) +{ + uintptr_t pmcbase; + + pmcbase = soc_read_pmc_base(); + + /* write the entire WBUF with the new PMC CMD Buffer */ + write32((void *)(pmcbase + PMC_IPC_WBUF0), wbuf->buf0); + write32((void *)(pmcbase + PMC_IPC_WBUF1), wbuf->buf1); + write32((void *)(pmcbase + PMC_IPC_WBUF2), wbuf->buf2); + write32((void *)(pmcbase + PMC_IPC_WBUF3), wbuf->buf3); + + /* Write the command register with the new command */ + write32((void *)(pmcbase + PMC_IPC_CMD_OFFSET), cmd); + + if (check_ipc_sts(pmcbase)) { + printk(BIOS_ERR, "PMC IPC command failed\n"); + return CB_ERR; + } + + /* get the response from the pmc out buffer */ + rbuf->buf0 = read32((void *)(pmcbase + PMC_IPC_RBUF0)); + rbuf->buf1 = read32((void *)(pmcbase + PMC_IPC_RBUF1)); + rbuf->buf2 = read32((void *)(pmcbase + PMC_IPC_RBUF2)); + rbuf->buf3 = read32((void *)(pmcbase + PMC_IPC_RBUF3)); + + return CB_SUCCESS; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/42077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide3528975be23585ce305f6cc909767b96af200f Gerrit-Change-Number: 42077 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newchange

7 30

Change in coreboot[master]: mb/intel/tglrvp: Enable Pcie WWAN m.2
by Bora Guvendik (Code Review) 14 Oct '20

14 Oct '20

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45828 ) Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ...................................................................... mb/intel/tglrvp: Enable Pcie WWAN m.2 Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 4 files changed, 22 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/45828/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index ad7eabe..be3ba0f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -20,7 +20,7 @@ register "SmbusEnable" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 49946c8..b63ee98 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -94,6 +94,15 @@ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */ + + /* WWAN */ + PAD_CFG_GPO(GPP_H23, 1, PLTRST), /* WWAN_PWREN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */ + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */ + PAD_CFG_GPO(GPP_C11, 1, PLTRST), /* FULL_CARD_POWER_OFF_N */ + PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_RST_N */ + PAD_CFG_GPO(GPP_B17, 1, PLTRST), /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* WWAN_DISABLE_N */ }; const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 3e2b342..1ba6bd6 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -20,9 +20,9 @@ register "SmbusEnable" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A port1 - register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 91bbe93..eee3234 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -90,6 +90,15 @@ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */ + + /* WWAN */ + PAD_CFG_GPO(GPP_D11, 1, PLTRST), /* WWAN_PWREN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */ + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */ + PAD_CFG_GPO(GPP_C11, 1, PLTRST), /* FULL_CARD_POWER_OFF_N */ + PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_RST_N */ + PAD_CFG_GPO(GPP_B17, 1, PLTRST), /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* WWAN_DISABLE_N */ }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/45828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Gerrit-Change-Number: 45828 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: soc/intel/skylake: Rename PcieRpAspm devicetree config
by Benjamin Doron (Code Review) 14 Oct '20

14 Oct '20

Hello build bot (Jenkins), Nico Huber, Frans Hendriks, Angel Pons, Patrick Rudolph, Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45001 to look at the new patch set (#5). Change subject: soc/intel/skylake: Rename PcieRpAspm devicetree config ...................................................................... soc/intel/skylake: Rename PcieRpAspm devicetree config This configuration option shares a name with the FSP UPD, but is enumerated differently. Change its name to minimise confusion about the options. Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/mainboard/facebook/monolith/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 3 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/45001/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/45001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Gerrit-Change-Number: 45001 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports
by Benjamin Doron (Code Review) 14 Oct '20

14 Oct '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 ) Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports ...................................................................... Patch Set 27: (1 comment) https://review.coreboot.org/c/coreboot/+/39538/14/src/soc/intel/skylake/chi… File src/soc/intel/skylake/chip.h: https://review.coreboot.org/c/coreboot/+/39538/14/src/soc/intel/skylake/chi… PS14, Line 286: PcieRpAspm > Not done. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 27 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 14 Oct 2020 05:01:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/zork: Enable wake on wireless lan
by Rob Barnes (Code Review) 14 Oct '20

14 Oct '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45745 ) Change subject: mb/google/zork: Enable wake on wireless lan ...................................................................... mb/google/zork: Enable wake on wireless lan Add generic wifi ACPI entry for wake on lan event. Change configuration of GPIO 2/WIFI_PCIE_WAKE_ODL to SCI. BUG=b:162605108 TEST=$ iw phy phy0 wowlan enable disconnect $ cat /proc/acpi/wakeup | grep WF WF00 S3 *enabled pci:0000:01:00.0 $ powerd_dbus_suspend Reboot wifi router, DUT wakes up Change-Id: Idbeb2cfbc4995b8382ffc26cbe7b53764fc9252d Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 4 files changed, 18 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45745/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 42219d7..7e1c0ad 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -200,7 +200,13 @@ device pci 0.2 on end # IOMMU device pci 1.0 on end # Dummy Host Bridge, must be enabled device pci 1.1 off end # GPP Bridge 0 - device pci 1.2 on end # GPP Bridge 1 - Wifi + device pci 1.2 on # GPP Bridge 1 - Wifi + chip drivers/wifi/generic + register "wake" = "GEVENT_8" + register "maxsleep" = "3" + device pci 00.0 on end + end + end device pci 1.3 on end # GPP Bridge 2 - SD device pci 1.4 off end # GPP Bridge 3 device pci 1.5 off end # GPP Bridge 4 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 1620643..f707465 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -200,7 +200,13 @@ device pci 0.2 on end # IOMMU device pci 1.0 on end # Dummy Host Bridge, must be enabled device pci 1.1 off end # GPP Bridge 0 - device pci 1.2 on end # GPP Bridge 1 - Wifi + device pci 1.2 on # GPP Bridge 1 - Wifi + chip drivers/wifi/generic + register "wake" = "GEVENT_8" + register "maxsleep" = "3" + device pci 00.0 on end + end + end device pci 1.3 on end # GPP Bridge 2 - SD device pci 1.4 off end # GPP Bridge 3 device pci 1.5 off end # GPP Bridge 4 diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index e69b47f..ab054ff 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -14,8 +14,8 @@ PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), /* SYS_RESET_L */ PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* PCIE_WAKE_L */ - PAD_NF(GPIO_2, WAKE_L, PULL_NONE), + /* WIFI_PCIE_WAKE_ODL */ + PAD_SCI(GPIO_2, PULL_NONE, EDGE_LOW), /* H1_FCH_INT_ODL */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* PEN_DETECT_ODL */ diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index bf25da3..a941087 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -14,8 +14,8 @@ PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), /* SYS_RESET_L */ PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), - /* PCIE_WAKE_L */ - PAD_NF(GPIO_2, WAKE_L, PULL_NONE), + /* WIFI_PCIE_WAKE_ODL */ + PAD_SCI(GPIO_2, PULL_NONE, EDGE_LOW), /* H1_FCH_INT_ODL */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* PEN_DETECT_ODL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idbeb2cfbc4995b8382ffc26cbe7b53764fc9252d Gerrit-Change-Number: 45745 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disa...
by Aamir Bohra (Code Review) 14 Oct '20

14 Oct '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34563 ) Change subject: soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabled ...................................................................... soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabled Add a check to enable ACPI timer emulation only when the APCI PM timer is disabled. Change-Id: I21c0b89218d0df9336e0b0e15f1b575b8508fb96 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/cpu.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/34563/1 diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 7eb413c..1058443 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -384,8 +384,12 @@ */ static void enable_pm_timer_emulation(void) { - /* ACPI PM timer emulation */ + config_t *conf = config_of_path(SA_DEVFN_ROOT); msr_t msr; + + /* Enable PM timer emulation only if ACPI PM timer is disabled */ + if (!config->PmTimerDisabled) + return; /* * The derived frequency is calculated as follows: * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. -- To view, visit https://review.coreboot.org/c/coreboot/+/34563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21c0b89218d0df9336e0b0e15f1b575b8508fb96 Gerrit-Change-Number: 34563 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: soc/intel/skylake: Support NHLT 1ch DMIC
by Benjamin Doron (Code Review) 14 Oct '20

14 Oct '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43072 to look at the new patch set (#8). Change subject: soc/intel/skylake: Support NHLT 1ch DMIC ...................................................................... soc/intel/skylake: Support NHLT 1ch DMIC Allows advertising support for a 1ch array DMIC in the NHLT table. Boards use the NHLT if a microphone is connected to the DSP. Tested on an Acer Aspire VN7-572G (Skylake-U) on Windows 10. A custom ALSA topology will be required for Linux. Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/nhlt/Makefile.inc M src/soc/intel/skylake/nhlt/dmic.c 5 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/43072/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/43072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Gerrit-Change-Number: 43072 Gerrit-PatchSet: 8 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/alderlake: Enable TME for Alder Lake
by Subrata Banik (Code Review) 14 Oct '20

14 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46296 ) Change subject: soc/intel/alderlake: Enable TME for Alder Lake ...................................................................... soc/intel/alderlake: Enable TME for Alder Lake List of changes: 1. Select CONFIG_INTEL_TME from SoC Kconfig 2. Set TmeEnable FSP-M UPD based on Kconfig. TEST=Able to build and boot ADLRVP and verified from Chrome OS that TME is enable. Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/46296/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 3f500f3..2d21a61 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -25,6 +25,7 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC + select INTEL_TME select MRC_SETTINGS_PROTECT select PARALLEL_MP select PARALLEL_MP_AP_WORK diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 80420f0..b96222c 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -155,6 +155,9 @@ /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev); + + /* Change TmeEnable UPD value according to INTEL_TME Kconfig */ + m_cfg->TmeEnable = CONFIG(INTEL_TME); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/46296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72 Gerrit-Change-Number: 46296 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/adl: Update FSP header file version 1332.01
by Subrata Banik (Code Review) 14 Oct '20

14 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46295 ) Change subject: vendorcode/intel/fsp/fsp2_0/adl: Update FSP header file version 1332.01 ...................................................................... vendorcode/intel/fsp/fsp2_0/adl: Update FSP header file version 1332.01 List of changes: - Add FSP-M UPD 'TmeEnable' TEST=Build and boot ADLRVP platform. Change-Id: Ic5fad998e880e9302b068fc78c28074fa432f1ba Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h 1 file changed, 32 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/46295/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index a42f014..8c4582a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -586,7 +586,17 @@ /** Offset 0x037C - Reserved **/ - UINT8 Reserved20[34]; + UINT8 Reserved20[20]; + +/** Offset 0x0390 - Enable or Disable TME + Enable or Disable TME; <b>0: Disable</b>; 1: Enable. + $EN_DIS +**/ + UINT8 TmeEnable; + +/** Offset 0x0391 - Reserved +**/ + UINT8 Reserved21[13]; /** Offset 0x039E - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -600,7 +610,7 @@ /** Offset 0x03A0 - Reserved **/ - UINT8 Reserved21[4]; + UINT8 Reserved22[4]; /** Offset 0x03A4 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -614,7 +624,7 @@ /** Offset 0x03AC - Reserved **/ - UINT8 Reserved22[12]; + UINT8 Reserved23[12]; /** Offset 0x03B8 - TxtHeapMemorySize Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable @@ -628,7 +638,7 @@ /** Offset 0x03C0 - Reserved **/ - UINT8 Reserved23[614]; + UINT8 Reserved24[614]; /** Offset 0x0626 - Number of RsvdSmbusAddressTable. The number of elements in the RsvdSmbusAddressTable. @@ -637,7 +647,7 @@ /** Offset 0x0627 - Reserved **/ - UINT8 Reserved24[4]; + UINT8 Reserved25[4]; /** Offset 0x062B - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use @@ -647,7 +657,7 @@ /** Offset 0x063D - Reserved **/ - UINT8 Reserved25[14]; + UINT8 Reserved26[14]; /** Offset 0x064B - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc @@ -656,7 +666,7 @@ /** Offset 0x065D - Reserved **/ - UINT8 Reserved26[19]; + UINT8 Reserved27[19]; /** Offset 0x0670 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -666,7 +676,7 @@ /** Offset 0x0674 - Reserved **/ - UINT8 Reserved27[2]; + UINT8 Reserved28[2]; /** Offset 0x0676 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. @@ -676,7 +686,7 @@ /** Offset 0x0677 - Reserved **/ - UINT8 Reserved28[3]; + UINT8 Reserved29[3]; /** Offset 0x067A - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. @@ -701,7 +711,7 @@ /** Offset 0x068D - Reserved **/ - UINT8 Reserved29[3]; + UINT8 Reserved30[3]; /** Offset 0x0690 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* @@ -751,7 +761,7 @@ /** Offset 0x06A7 - Reserved **/ - UINT8 Reserved30[13]; + UINT8 Reserved31[13]; /** Offset 0x06B4 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. @@ -761,7 +771,7 @@ /** Offset 0x06B5 - Reserved **/ - UINT8 Reserved31[4]; + UINT8 Reserved32[4]; /** Offset 0x06B9 - MRC Safe Config Enables/Disable MRC Safe Config @@ -819,7 +829,7 @@ /** Offset 0x06C2 - Reserved **/ - UINT8 Reserved32[2]; + UINT8 Reserved33[2]; /** Offset 0x06C4 - Early Command Training Enables/Disable Early Command Training @@ -829,7 +839,7 @@ /** Offset 0x06C5 - Reserved **/ - UINT8 Reserved33[65]; + UINT8 Reserved34[65]; /** Offset 0x0706 - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to @@ -839,7 +849,7 @@ /** Offset 0x0708 - Reserved **/ - UINT8 Reserved34[64]; + UINT8 Reserved35[64]; /** Offset 0x0748 - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, @@ -852,7 +862,7 @@ /** Offset 0x0749 - Reserved **/ - UINT8 Reserved35[2]; + UINT8 Reserved36[2]; /** Offset 0x074B - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) @@ -862,7 +872,7 @@ /** Offset 0x074C - Reserved **/ - UINT8 Reserved36[2]; + UINT8 Reserved37[2]; /** Offset 0x074E - TCSS USB Port Enable Bitmap for per port enabling @@ -871,7 +881,7 @@ /** Offset 0x074F - Reserved **/ - UINT8 Reserved37[50]; + UINT8 Reserved38[50]; /** Offset 0x0781 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -882,7 +892,7 @@ /** Offset 0x0782 - Reserved **/ - UINT8 Reserved38; + UINT8 Reserved39; /** Offset 0x0783 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 @@ -892,7 +902,7 @@ /** Offset 0x0784 - Reserved **/ - UINT8 Reserved39[129]; + UINT8 Reserved40[129]; /** Offset 0x0805 - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check @@ -902,7 +912,7 @@ /** Offset 0x0806 - Reserved **/ - UINT8 Reserved40[292]; + UINT8 Reserved41[292]; /** Offset 0x092A - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode @@ -913,7 +923,7 @@ /** Offset 0x092B - Reserved **/ - UINT8 Reserved41[517]; + UINT8 Reserved42[517]; } FSP_M_CONFIG; /** Fsp M UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/46295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5fad998e880e9302b068fc78c28074fa432f1ba Gerrit-Change-Number: 46295 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 6

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020