coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sc7180: Enable bootblock compression
by Julius Werner (Code Review) 13 Oct '20

13 Oct '20

Hello Philip Chen, mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45855 to review the following change. Change subject: sc7180: Enable bootblock compression ...................................................................... sc7180: Enable bootblock compression This patch enables bootblock compression on SC7180. In my tests, that makes it boot roughly 10ms faster (which isn't much, but... might as well take it). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Ibbe06eeb05347cc77395681969e6eaf1598b4260 --- M src/arch/arm64/Makefile.inc M src/soc/qualcomm/sc7180/Kconfig M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/decompressor.c M src/soc/qualcomm/sc7180/memlayout.ld 6 files changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/45855/1 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 920ff5d..44517cb 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -31,6 +31,7 @@ $(call src-to-obj,decompressor,$(dir)/id.S): $(obj)/build.h $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h +decompressor-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c bootblock-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c bootblock-y += transition.c transition_asm.S diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index d543ef5..addb49d 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -17,6 +17,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select COMPRESS_BOOTBLOCK if SOC_QUALCOMM_SC7180 diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index a0d3bc6..7f52a9a 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -1,6 +1,10 @@ ifeq ($(CONFIG_SOC_QUALCOMM_SC7180),y) +decompressor-y += decompressor.c +decompressor-y += mmu.c +decompressor-y += timer.c + ################################################################################ bootblock-y += bootblock.c bootblock-y += mmu.c diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index 7dbaeec..cfeb6f9 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -2,13 +2,11 @@ #include <bootblock_common.h> #include <soc/clock.h> -#include <soc/mmu.h> #include <soc/qspi.h> #include <soc/qupv3_config.h> void bootblock_soc_init(void) { - sc7180_mmu_init(); clock_init(); quadspi_init(37500 * KHz); qupv3_fw_init(); diff --git a/src/soc/qualcomm/sc7180/decompressor.c b/src/soc/qualcomm/sc7180/decompressor.c new file mode 100644 index 0000000..ac55150 --- /dev/null +++ b/src/soc/qualcomm/sc7180/decompressor.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/mmu.h> + +void decompressor_soc_init(void) +{ + sc7180_mmu_init(); +} diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index 0142242..ea9a451 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -22,7 +22,7 @@ AOPSRAM_END(0x0B100000) SSRAM_START(0x14680000) - OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x14680000, 100K) REGION(qcsdi, 0x14699000, 52K, 4K) SSRAM_END(0x146AE000) -- To view, visit https://review.coreboot.org/c/coreboot/+/45855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbe06eeb05347cc77395681969e6eaf1598b4260 Gerrit-Change-Number: 45855 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers: snsn65dsi86: Fix link rate parsing
by Julius Werner (Code Review) 13 Oct '20

13 Oct '20

Hello Douglas Anderson, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46318 to review the following change. Change subject: drivers: snsn65dsi86: Fix link rate parsing ...................................................................... drivers: snsn65dsi86: Fix link rate parsing DP link rates are reported in an array of LE16 values. The current code tries to parse them as 8-bit which doesn't get very far, causing us to always drop into the fallback path. This patch should fix the issue (+minor whitespace cleanup). BUG=b:170630766 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I1e03088ee2d3517bdb5dcc4dcc4ac04f8b14a391 --- M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c 1 file changed, 5 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46318/1 diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c index 5a6eb49..44a8088 100644 --- a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c @@ -259,11 +259,11 @@ DP_BRIDGE_DPCD_REV, 1, DPCD_READ, &dpcd_val); if (dpcd_val >= DP_BRIDGE_14) { /* eDP 1.4 devices must provide a custom table */ - uint8_t sink_rates[DP_MAX_SUPPORTED_RATES * 2]; + uint16_t sink_rates[DP_MAX_SUPPORTED_RATES] = {0}; sn65dsi86_bridge_dpcd_request(bus, chip, DP_SUPPORTED_LINK_RATES, sizeof(sink_rates), - DPCD_READ, sink_rates); + DPCD_READ, (void *)sink_rates); for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { rate_per_200khz = le16_to_cpu(sink_rates[i]); @@ -288,14 +288,12 @@ } /* On older versions best we can do is use DP_MAX_LINK_RATE */ - sn65dsi86_bridge_dpcd_request(bus, chip, - DP_MAX_LINK_RATE, 1, DPCD_READ, &dpcd_val); + sn65dsi86_bridge_dpcd_request(bus, chip, DP_MAX_LINK_RATE, 1, DPCD_READ, &dpcd_val); switch (dpcd_val) { default: - printk(BIOS_ERR, - "Unexpected max rate (%#x); assuming 5.4 GHz\n", - (int)dpcd_val); + printk(BIOS_ERR, "Unexpected max rate (%#x); assuming 5.4 GHz\n", + (int)dpcd_val); /* fall through */ case DP_LINK_BW_5_4: rate_valid[7] = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/46318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e03088ee2d3517bdb5dcc4dcc4ac04f8b14a391 Gerrit-Change-Number: 46318 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: set PM ACPI timer state f...
by Michael Niewöhner (Code Review) 13 Oct '20

13 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45957 ) Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: set PM ACPI timer state from Kconfig ...................................................................... Patch Set 24: Subrata, did Intel drop EnableTcoTimer from Alderlake FSP? -- To view, visit https://review.coreboot.org/c/coreboot/+/45957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf1eee9297034b29b7250f6c752e6f7f52b4b908 Gerrit-Change-Number: 45957 Gerrit-PatchSet: 24 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 13 Oct 2020 22:31:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: rewrite and clarify the Legacy 8254 Timer Kconfig
by Michael Niewöhner (Code Review) 13 Oct '20

13 Oct '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46302 ) Change subject: soc/intel/common: rewrite and clarify the Legacy 8254 Timer Kconfig ...................................................................... soc/intel/common: rewrite and clarify the Legacy 8254 Timer Kconfig The current Kconfig help text is confusing because it talks about enabling the Kconfig for disabling a UPD for disabling power gating. Rewrite and clarify the help text. Change-Id: I9637c549db1ce29f259708f316852fc2ae9e7c38 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46302 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/common/block/timer/Kconfig 1 file changed, 8 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig index a214ef0..42613a8 100644 --- a/src/soc/intel/common/block/timer/Kconfig +++ b/src/soc/intel/common/block/timer/Kconfig @@ -8,7 +8,11 @@ default y if PAYLOAD_SEABIOS || VGA_ROM_RUN default n help - This sets the FSP UPD to enable Legacy 8254 clock gating. As per - the FSP Integration guide Legacy 8254 timer clock gating UPD needs - to be disabled in order to boot SeaBIOS or run OpRom, - but should otherwise be enabled. + Setting this makes the Legacy 8254 Timer available by disabling + clock gating. This needs to be enabled in order to boot a legacy + BIOS or OS not supporting other timers like PM timer or TSC. + + While SeaBIOS does not require this timer anymore, it is needed + when OpRoms are being used. + + Disable this setting to save power, when the timer is not needed. -- To view, visit https://review.coreboot.org/c/coreboot/+/46302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9637c549db1ce29f259708f316852fc2ae9e7c38 Gerrit-Change-Number: 46302 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: include/cpu/x86: introduce new helper for (un)setting MSRs
by Michael Niewöhner (Code Review) 13 Oct '20

13 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46354 ) Change subject: include/cpu/x86: introduce new helper for (un)setting MSRs ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/46354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfe9b66e7cfe78ec295a44a2a193f530349f7689 Gerrit-Change-Number: 46354 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 13 Oct 2020 22:17:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: MAINTAINERS: Add Felix Singer to mb/clevo
by Felix Singer (Code Review) 13 Oct '20

13 Oct '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46316 ) Change subject: MAINTAINERS: Add Felix Singer to mb/clevo ...................................................................... MAINTAINERS: Add Felix Singer to mb/clevo Change-Id: I1d4547d02cf0d27db5c3b0c0ae46b730a198c814 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M MAINTAINERS 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/46316/1 diff --git a/MAINTAINERS b/MAINTAINERS index 4020acc..8198be4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -208,6 +208,13 @@ +CLEVO MAINBOARDS +M: Felix Singer <felixsinger(a)posteo.net> +S: Supported +F: src/mainboard/clevo + + + FACEBOOK FBG1701 MAINBOARD M: Frans Hendriks <fhendriks(a)eltan.com> M: Wim Vervoorn <wvervoorn(a)eltan.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/46316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d4547d02cf0d27db5c3b0c0ae46b730a198c814 Gerrit-Change-Number: 46316 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/x86: Try to discover invariant TSC rate
by Tim Wawrzynczak (Code Review) 13 Oct '20

13 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34170 ) Change subject: libpayload/x86: Try to discover invariant TSC rate ...................................................................... Patch Set 4: (2 comments) > Patch Set 4: > > This might need checking how it behaves with Depthcharge. I was > actually wondering how CrOS devices handle it... is the PIT enabled? > do you have a different timer? I can confirm in the volteer (TGL) next to me that these two patches allow me to call `get_cpu_speed()` without hanging 😊. Without these, it hangs on the call, presumably b/c we leave the PIT disabled. We haven't used PIT for timing since some old skylake boards I see. Current boards AFAICT just use the timestamp counter https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… File payloads/libpayload/arch/x86/timer.c: https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… PS4, Line 90: ecx this seems unneeded, you could just pass nominal for ecx, and if it's 0, perform the model checks https://review.coreboot.org/c/coreboot/+/34170/4/payloads/libpayload/arch/x… PS4, Line 106: switch (cpuid_model()) { : case 0x4e: /* SKL-U/Y */ : case 0x5e: /* SKL-S/H */ : case 0x8e: /* KBL-U/Y */ : case 0x9e: /* KBL-S/H */ : nominal = 24000000; : break; : case 0x5c: /* APL */ : nominal = 19200000; : break; : default: : return -1; : } : } : : return nominal * num / denom / 1000; : } : : /** : * @brief Returns three times the bus clock in kHz : * : * The result of calculations with the returned value shall be divided by 3. : * This helps to avoid rounding errors. : */ : static int get_bus_khz_x3(void) : { : if (cpuid_family() != 6) : return -1; : : switch (cpuid_model()) { : case 0x25: /* Nehalem */ : return 400 * 1000; /* 133 MHz */ : case 0x2a: /* SandyBridge */ : case 0x3a: /* IvyBridge */ : case 0x3c: /* Haswell */ : case 0x3d: /* Broadwell */ : case 0x45: /* Haswell-ULT */ : case 0x46: /* Haswell-GT3e */ : return 300 * 1000; /* 100 MHz */ : default: : return -1; : } : } suggestion: an enum for the results of cpuid_model() would be more readable than comments -- To view, visit https://review.coreboot.org/c/coreboot/+/34170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889 Gerrit-Change-Number: 34170 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 13 Oct 2020 22:10:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: {cpu,soc}/intel: deduplicate cpu code
by Michael Niewöhner (Code Review) 13 Oct '20

13 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Paul Menzel, Subrata Banik, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46274 to look at the new patch set (#9). Change subject: {cpu,soc}/intel: deduplicate cpu code ...................................................................... {cpu,soc}/intel: deduplicate cpu code Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl, tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common. Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/cpu/intel/common/common.h M src/cpu/intel/common/common_init.c M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/include/cpu/intel/msr.h M src/soc/intel/alderlake/cpu.c M src/soc/intel/broadwell/cpu.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c 15 files changed, 57 insertions(+), 439 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46274/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/46274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab Gerrit-Change-Number: 46274 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: {cpu,soc}/intel: replace AES-NI locking by common implemenation call
by Michael Niewöhner (Code Review) 13 Oct '20

13 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, David Guckian, Paul Menzel, Tim Wawrzynczak, Vanessa Eusebio, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46278 to look at the new patch set (#4). Change subject: {cpu,soc}/intel: replace AES-NI locking by common implemenation call ...................................................................... {cpu,soc}/intel: replace AES-NI locking by common implemenation call Deduplicate code by using the new common cpu code implementation of AES-NI locking. For model_2065x and model_206ax locking was moved from SMM to core init because the MSR is core-scoped, not package-scoped. Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/cpu/intel/common/common_init.c M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/finalize.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/include/cpu/intel/msr.h M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/skylake/cpu.c 13 files changed, 17 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46278/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/46278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50 Gerrit-Change-Number: 46278 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/intel/common: rework AES-NI locking
by Michael Niewöhner (Code Review) 13 Oct '20

13 Oct '20

Hello Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46275 to look at the new patch set (#2). Change subject: cpu/intel/common: rework AES-NI locking ...................................................................... cpu/intel/common: rework AES-NI locking Simplify the AES-NI code by using msr_set_bit and correct the comment. Change-Id: Ib2cda433bbec0192277839c02a1862b8f41340cb Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/cpu/intel/common/common.h M src/cpu/intel/common/common_init.c M src/include/cpu/intel/msr.h 3 files changed, 6 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/46275/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2cda433bbec0192277839c02a1862b8f41340cb Gerrit-Change-Number: 46275 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2020