coreboot-gerrit October 2020

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Change in coreboot[master]: vc/amd/fsp/picasso: Add bitfields for PSP info in transfer block
by Martin Roth (Code Review) 01 Oct '20

01 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45804 ) Change subject: vc/amd/fsp/picasso: Add bitfields for PSP info in transfer block ...................................................................... vc/amd/fsp/picasso: Add bitfields for PSP info in transfer block BUG=b:168895748 TEST=None BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I299fdd0f007f7e4a8f597931a52f68dc98acc9ac --- M src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/45804/1 diff --git a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h index 69ada34..684929d 100644 --- a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h @@ -54,6 +54,10 @@ #define SVC_SHA 0x46 #define SVC_RSAPKCS_VERIFY 0x47 +#define PSP_INFO_PRODUCTION_MODE 0x00000001UL +#define PSP_INFO_PRODUCTION_SI 0x00000002UL +#define PSP_INFO_VALID 0x80000000UL + typedef struct _RSAPSS_VERIFY_PARAMS_T { char *pHash; // Message digest to verify the RSA signature -- To view, visit https://review.coreboot.org/c/coreboot/+/45804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I299fdd0f007f7e4a8f597931a52f68dc98acc9ac Gerrit-Change-Number: 45804 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Temporary init for backlight in the OS
by Martin Roth (Code Review) 01 Oct '20

01 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45854 ) Change subject: mb/google/zork: Temporary init for backlight in the OS ...................................................................... mb/google/zork: Temporary init for backlight in the OS This needs to go into ACPI, but that's taking me a while, so I figured I'd push this temporarily. Not for merge. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I6ecc3c9e397c9756a78e480d3f639c507879a0ea --- M src/mainboard/google/zork/smihandler.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/45854/1 diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c index 12a3b64..6fc6f92 100644 --- a/src/mainboard/google/zork/smihandler.c +++ b/src/mainboard/google/zork/smihandler.c @@ -33,5 +33,9 @@ if (CONFIG(EC_GOOGLE_CHROMEEC)) chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + /* Temporary fix - Needs to go into ACPI instead */ + /* Turn on the backlight when we go to ACPI mode */ + gpio_set(GPIO_85, 0); + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ecc3c9e397c9756a78e480d3f639c507879a0ea Gerrit-Change-Number: 45854 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Remove code that reconfigured the backlight GPIO
by Martin Roth (Code Review) 01 Oct '20

01 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45853 ) Change subject: mb/google/zork: Remove code that reconfigured the backlight GPIO ...................................................................... mb/google/zork: Remove code that reconfigured the backlight GPIO The SMU code was assuming that GPIO 85 was used for a fan, which caused interesting backlight flickering. That has now been fixed, so remove the code that reconfigured it to a GPIO on resume. BUG=b:155667589 TEST=Verify the screen does not flicker on resume from S3 BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I6d4f9d98e9df52fefab9b20d0ab0f0b67512d356 --- M src/mainboard/google/zork/mainboard.c 1 file changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/45853/1 diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c index 4206fdf..f0d9a28 100644 --- a/src/mainboard/google/zork/mainboard.c +++ b/src/mainboard/google/zork/mainboard.c @@ -188,25 +188,12 @@ dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; } -static const struct soc_amd_gpio gpio_set_bl[] = { - PAD_GPO(GPIO_85, LOW), -}; - -static void reset_backlight_gpio(void *unused) -{ - printk(BIOS_DEBUG, "Reset backlight GPIO\n"); - /* Re-Enable backlight - GPIO 85 active low */ - /* TODO: Remove this after AGESA stops enabling the fan - b/155667589 */ - program_gpios(gpio_set_bl, ARRAY_SIZE(gpio_set_bl)); /* APU_EDP_BL_DISABLE */ -} - static void mainboard_final(void *chip_info) { struct global_nvs *gnvs; gnvs = acpi_get_gnvs(); - reset_backlight_gpio(NULL); if (gnvs) { gnvs->tmps = CTL_TDP_SENSOR_ID; @@ -231,5 +218,3 @@ *size = 0; return NULL; } - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, reset_backlight_gpio, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/45853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d4f9d98e9df52fefab9b20d0ab0f0b67512d356 Gerrit-Change-Number: 45853 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: skip DRHD generation for non-PCIe stack
by Jonathan Zhang (Code Review) 01 Oct '20

01 Oct '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45223 ) Change subject: soc/intel/xeon_sp/cpx: skip DRHD generation for non-PCIe stack ...................................................................... soc/intel/xeon_sp/cpx: skip DRHD generation for non-PCIe stack Without skipping of DRHD generation for non-PCIe stack, the OS kernel detects incorrect DMRA table with following messages: [ 0.561817] Your BIOS is broken; DMAR reported at address 0! With this fix, another issue in DMAR table makes OS kernel continuously sending out following messages and OS becomes unusable: [ 123.568748] bnxt_en 0000:67:00.0 enp103s0: Resp cmpl intr err msg: 0x51 [ 123.582337] bnxt_en 0000:67:00.0 enp103s0: hwrm_ring_free type 1 failed. rc:ffffffff err:0 [ 123.600157] DMAR: DRHD: handling fault status reg 202 [ 123.610497] DMAR: [INTR-REMAP] Request device [67:00.0] fault index 2e [fault reason 34] Present field in the IRTE entry is clear It turns out the PCIe bridge device entries for PCIe ports in the DMAR table have incorrect dev/func values. Those values come from FSP IIO_UDS HOB. Hence a IPS ticket is filed, and we work around this FSP bug through hardcoding dev/func values. While at this, make some code improvements such as only find IIO_UDS HOB once while generating DMAR table. Change-Id: If31d2adf8c03bd57ef394834c03293a08dc4b21a Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> --- M src/soc/intel/xeon_sp/cpx/acpi.c 1 file changed, 28 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/45223/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 1328257..de3fcb4 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -588,17 +588,20 @@ */ static int get_stack_for_port(int p) { - if (p == 0) + if (p == PORT_0) return CSTACK; else if (p >= PORT_1A && p <= PORT_1D) return PSTACK0; else if (p >= PORT_2A && p <= PORT_2D) return PSTACK1; - else //if (p >= PORT_3A && p <= PORT_3D) + else if (p >= PORT_3A && p <= PORT_3D) return PSTACK2; + else + return -1; } -static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack) +static unsigned long acpi_create_drhd(unsigned long current, int socket, + int stack, const IIO_UDS *hob) { int IoApicID[] = { // socket 0 @@ -612,12 +615,6 @@ uint32_t enum_id; unsigned long tmp = current; - size_t hob_size; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob = fsp_find_extension_hob_by_guid( - fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - uint32_t bus = hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; uint32_t reg_base = @@ -625,6 +622,10 @@ printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", __func__, socket, stack, bus, pcie_seg, reg_base); + /* Do not generate DRHD for non-PCIe stack */ + if (reg_base == 0x0) + return current; + // Add DRHD Hardware Unit if (socket == 0 && stack == CSTACK) { printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " @@ -670,13 +671,27 @@ if (socket != 0 || stack != CSTACK) { IIO_RESOURCE_INSTANCE iio_resource = hob->PlatformData.IIO_resource[socket]; - for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + for (int p = 0; p < MAX_PORTS; ++p) { if (get_stack_for_port(p) != stack) continue; uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; + /* TODO: remove this workaround when the IPS ticket is resolved. */ + if (p == 1 || p == 5) + dev = 0x0; + else if (p == 2 || p == 6) + dev = 0x1; + else if (p == 3 || p == 7) + dev = 0x2; + else if (p == 4 || p == 8) + dev = 0x3; + else if (p == 9) + dev = 0x0; + + func = 0x0; + uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID); if (id == 0xffffffff) @@ -858,11 +873,11 @@ if (socket == 0) { for (int stack = 1; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack); - current = acpi_create_drhd(current, socket, CSTACK); + current = acpi_create_drhd(current, socket, stack, hob); + current = acpi_create_drhd(current, socket, CSTACK, hob); } else { for (int stack = 0; stack <= PSTACK2; ++stack) - current = acpi_create_drhd(current, socket, stack); + current = acpi_create_drhd(current, socket, stack, hob); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/45223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If31d2adf8c03bd57ef394834c03293a08dc4b21a Gerrit-Change-Number: 45223 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020