coreboot-gerrit October 2020

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Change in coreboot[master]: mb/google/volteer: Expand WP_RO region to 8MB in fmap
by Tim Wawrzynczak (Code Review) 01 Oct '20

01 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45889 ) Change subject: mb/google/volteer: Expand WP_RO region to 8MB in fmap ...................................................................... Patch Set 2: 4 more MiB?? oh my... is that really the lowest resolution we can get away with? -- To view, visit https://review.coreboot.org/c/coreboot/+/45889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72fe8b6a1f91390c218230c0c20825769ebd1e0b Gerrit-Change-Number: 45889 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Oct 2020 20:42:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: de-assert eMMC RST for Morphius
by Kevin Chiu (Code Review) 01 Oct '20

01 Oct '20

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45756 ) Change subject: mb/google/zork: de-assert eMMC RST for Morphius ...................................................................... mb/google/zork: de-assert eMMC RST for Morphius de-assert eMMC RST (GPIO68) to prevent eMMC abnormal. BUG=b:169211959 BRANCH=zork TEST=1. emerge-zork coreboot 2. check GPIO86 state is PU Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/morphius/gpio.c 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/45756/1 diff --git a/src/mainboard/google/zork/variants/morphius/gpio.c b/src/mainboard/google/zork/variants/morphius/gpio.c index 8da0de4..c1655fa 100644 --- a/src/mainboard/google/zork/variants/morphius/gpio.c +++ b/src/mainboard/google/zork/variants/morphius/gpio.c @@ -52,6 +52,8 @@ }; static const struct soc_amd_gpio morphius_bid3_gpio_set_stage_ram[] = { + /* EMMC_RESET */ + PAD_GPO(GPIO_68, HIGH), /* EN_DEV_BEEP_L */ PAD_GPO(GPIO_89, HIGH), /* TP */ @@ -60,6 +62,11 @@ PAD_GPO(GPIO_140, HIGH), }; +static const struct soc_amd_gpio morphius_gpio_set_stage_ram[] = { + /* EMMC_RESET */ + PAD_GPO(GPIO_68, HIGH), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version; @@ -83,6 +90,6 @@ return morphius_bid3_gpio_set_stage_ram; } - *size = 0; - return NULL; + *size = ARRAY_SIZE(morphius_gpio_set_stage_ram); + return morphius_gpio_set_stage_ram; } -- To view, visit https://review.coreboot.org/c/coreboot/+/45756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd Gerrit-Change-Number: 45756 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
by Michael Niewöhner (Code Review) 01 Oct '20

01 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45798 ) Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 ...................................................................... Patch Set 4: (1 comment) > Patch Set 4: > > Isn't that the same as in other SoCs? Can we move this to common code? https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/… File src/soc/intel/xeon_sp/cpx/romstage.c: https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/… PS4, Line 41: save_dimm_info that's a candidate for soc/intel/common, isn't it? -- To view, visit https://review.coreboot.org/c/coreboot/+/45798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb72d18027d972140828970206834ff55b72022 Gerrit-Change-Number: 45798 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 01 Oct 2020 20:03:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
by Felix Singer (Code Review) 01 Oct '20

01 Oct '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45798 ) Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 ...................................................................... Patch Set 4: Isn't that the same as in other SoCs? Can we move this to common code? -- To view, visit https://review.coreboot.org/c/coreboot/+/45798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb72d18027d972140828970206834ff55b72022 Gerrit-Change-Number: 45798 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Thu, 01 Oct 2020 20:02:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Align comment with rest of the devicetree
by 9elements QA (Code Review) 01 Oct '20

01 Oct '20

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45884 ) Change subject: mb/clevo/l140cu: Align comment with rest of the devicetree ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 5/1/6 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/21881 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/21880 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/21879 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/21878 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/21876 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/21875 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/45884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcaedd3d5b7e465644f79e5a882e42eff040fdbd Gerrit-Change-Number: 45884 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Oct 2020 19:40:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/acer: Add Acer Aspire ES1-572
by Benjamin Doron (Code Review) 01 Oct '20

01 Oct '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mb/acer: Add Acer Aspire ES1-572 ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… PS5, Line 223: register "SendVrMbxCmd" = "2" > I never verified that it was required in the first place. […] I haven't seen any information on it either. Perhaps the EDS mentions it, or maybe the full datasheet for the relevant VR. I have neither. I did, however, notice that the Skylake FSP goes gold at version 2.0.0.0 with this UPD present. The vendor firmware for my board, using the 1.9.0.0 reference code, does not mention it all in the advanced settings. It's possible that the vendor firmware does not allow the setting to be changed and configures it directly (like the HSIO UPDs), but I would find this unlikely. The rest of the power settings are configurable. So, maybe we can sometimes extrapolate from version information, etc? -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Oct 2020 19:30:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: security/intel/stm: Fix size_t printf format error
by Felix Held (Code Review) 01 Oct '20

01 Oct '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45872 ) Change subject: security/intel/stm: Fix size_t printf format error ...................................................................... security/intel/stm: Fix size_t printf format error This sort-of reverts commit 075df92298fe3bb0ef04233395effe668c4a5550 and fixes the underlying issue. The printf format string type/length specifier for a size_t type is z. Change-Id: I897380060f7ea09700f77beb81d52c18a45326ad Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/security/intel/stm/SmmStm.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/45872/1 diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c index 00490cf..e2fab0c 100644 --- a/src/security/intel/stm/SmmStm.c +++ b/src/security/intel/stm/SmmStm.c @@ -477,7 +477,7 @@ return -1; // INVALID_PARAMETER; resource_size = get_resource_size(resource_list, num_entries); - printk(BIOS_DEBUG, "STM: ResourceSize - 0x%08x\n", (int) resource_size); + printk(BIOS_DEBUG, "STM: ResourceSize - 0x%08zx\n", resource_size); if (resource_size == 0) return -1; // INVALID_PARAMETER; -- To view, visit https://review.coreboot.org/c/coreboot/+/45872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I897380060f7ea09700f77beb81d52c18a45326ad Gerrit-Change-Number: 45872 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/l140cu: Align comment with rest of the devicetree
by Michael Niewöhner (Code Review) 01 Oct '20

01 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45884 ) Change subject: mb/clevo/l140cu: Align comment with rest of the devicetree ...................................................................... Patch Set 3: landed early due to simplicity -- To view, visit https://review.coreboot.org/c/coreboot/+/45884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcaedd3d5b7e465644f79e5a882e42eff040fdbd Gerrit-Change-Number: 45884 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Oct 2020 18:54:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Align comment with rest of the devicetree
by Michael Niewöhner (Code Review) 01 Oct '20

01 Oct '20

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45884 ) Change subject: mb/clevo/l140cu: Align comment with rest of the devicetree ...................................................................... mb/clevo/l140cu: Align comment with rest of the devicetree Change-Id: Idcaedd3d5b7e465644f79e5a882e42eff040fdbd Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45884 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index e079dff..3ee20e9 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -94,7 +94,7 @@ device pci 14.3 on end end device pci 14.5 off end # SDCard - device pci 15.0 on + device pci 15.0 on # I2C #0 chip drivers/i2c/hid register "generic.hid" = ""ELAN040D"" register "generic.desc" = ""ELAN Touchpad"" @@ -103,7 +103,7 @@ register "hid_desc_reg_offset" = "0x01" device i2c 15 on end end - end # I2C #0 + end device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 -- To view, visit https://review.coreboot.org/c/coreboot/+/45884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcaedd3d5b7e465644f79e5a882e42eff040fdbd Gerrit-Change-Number: 45884 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/clevo/l140cu: Generate ACPI code with information about USB ports
by Felix Singer (Code Review) 01 Oct '20

01 Oct '20

Hello build bot (Jenkins), Paul Menzel, Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45885 to look at the new patch set (#3). Change subject: mb/clevo/l140cu: Generate ACPI code with information about USB ports ...................................................................... mb/clevo/l140cu: Generate ACPI code with information about USB ports Change-Id: I414d02cc9c16ed23ce12cba79bfd68e0e6486129 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/Kconfig M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb 2 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/45885/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/45885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I414d02cc9c16ed23ce12cba79bfd68e0e6486129 Gerrit-Change-Number: 45885 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2020