coreboot-gerrit October 2020

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Change in coreboot[master]: drivers/intel/fsp2_0: ask FSP to allocate APEI BERT memory region
by Jonathan Zhang (Code Review) 02 Oct '20

02 Oct '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45391 ) Change subject: drivers/intel/fsp2_0: ask FSP to allocate APEI BERT memory region ...................................................................... drivers/intel/fsp2_0: ask FSP to allocate APEI BERT memory region APEI (ACPI Platform Error Interface) defines BERT (Boot Error Record Table) memory region: * Bootloader (firmware) generates UEFI CPER (Common Platform Error Record) records, and populates BERT region. In case of FSP 2.x, coreboot gets BERT region raw data from FSP (PREV_BOOT_ERROR_SRC_HOB). * OS parses ACPI BERT table, finds the BERT region address, inteprets the data and processes it accordingly. When CONFIG_ACPI_BERT is defined, update FSP UPD BootLoaderTolumSize, so FSP allocates memory region for it. The APEI BERT region is placed on top of CBMEM, for the size of CONFIG_ACPI_BERT_SIZE. Change-Id: Ie72240e4c5fa01fcf937d33678c40f9ca826487a Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> --- M src/drivers/intel/fsp2_0/cbmem.c M src/drivers/intel/fsp2_0/hob_verify.c M src/drivers/intel/fsp2_0/memory_init.c 3 files changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/45391/1 diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c index 0efb462..f836b36 100644 --- a/src/drivers/intel/fsp2_0/cbmem.c +++ b/src/drivers/intel/fsp2_0/cbmem.c @@ -6,7 +6,10 @@ void *cbmem_top_chipset(void) { struct range_entry tolum; + void *tolum_base; fsp_find_bootloader_tolum(&tolum); - return (void *)(uintptr_t)range_entry_end(&tolum); + tolum_base = (void *)(uintptr_t)range_entry_base(&tolum); + + return tolum_base + cbmem_overhead_size(); } diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index ec526e8..94fc653e 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -43,9 +43,7 @@ die("Space between FSP reserved region and BIOS TOLUM!\n"); } - if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { - printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n", + if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) + printk(BIOS_DEBUG, "TOLUM end: 0x%08llx != %p: cbmem_top\n", range_entry_end(&tolum), cbmem_top()); - die("Space between cbmem_top and BIOS TOLUM!\n"); - } } diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 07c4463..1ef9324 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -276,6 +276,21 @@ /* Reserve enough memory under TOLUD to save CBMEM header */ arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); + /* + * If ACPI APEI BERT region size is defined, reserve memory for it. + * +------------------------+ range_entry_top(tolum) + * | Other reserved regions | + * | APEI BERT region | + * +------------------------+ cbmem_top() + * | CBMEM IMD ROOT | + * | CBMEM IMD SMALL | + * +------------------------+ range_entry_base(tolum), TOLUM + * | CBMEM FSP MEMORY | + * | Other CBMEM regions... | + */ + if (CONFIG(ACPI_BERT)) + arch_upd->BootLoaderTolumSize += CONFIG_ACPI_BERT_SIZE; + /* Fill common settings on behalf of chipset. */ if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, memmap) != CB_SUCCESS) -- To view, visit https://review.coreboot.org/c/coreboot/+/45391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie72240e4c5fa01fcf937d33678c40f9ca826487a Gerrit-Change-Number: 45391 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mb/acer: Add Acer Aspire ES1-572
by Michael Niewöhner (Code Review) 02 Oct '20

02 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mb/acer: Add Acer Aspire ES1-572 ...................................................................... Patch Set 9: (2 comments) https://review.coreboot.org/c/coreboot/+/38978/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38978/7//COMMIT_MSG@37 PS7, Line 37: - Touchpad. Hangs off either EC or some I2C controller and needs ACPI. > I doubt it's wired using PS/2 to the EC Well, it's connected to the EC's PS/2 port 3 (according to the kb9012 ds). It could be I2C as well, depending on the actual ec. Anyway, direct I2C/SMBus is better than <whatever> via PS/2 through ec. https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… PS5, Line 223: register "SendVrMbxCmd" = "2" > I haven't seen any information on it either. […] I don't think, there is any reason to show it as advanced setting in vendor fw, if that is for fixing an erratum. wdym with "goes gold"? -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Oct 2020 10:58:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: treewide: stop using hexdumps for SPD files
by Michael Niewöhner (Code Review) 02 Oct '20

02 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44775 ) Change subject: treewide: stop using hexdumps for SPD files ...................................................................... Patch Set 27: > Patch Set 27: > > > Patch Set 27: Code-Review-1 > > > > > Patch Set 27: Code-Review+1 > > > > > > > Patch Set 27: > > > > > > > > > I'd vote for not checking binaries into the coreboot source tree at all. Personally, I'd like to get rid of the vbt binaries and have a tool to compile them as well. My understanding was that there wasn't documentation for the VBT fields, but it seems that maybe this is no longer the case. [1] > > > > > > > > In general I agree, but it seems hard to get authoritative sources on the precise format, even for SPD dumps - that ought to be standardized but get repurposed in lots of "wonderful" ways by memory reference code. As far as we know, the "spec" to these files is the reference code, and that's not public. > > > > > > > > Some of the SPD tools we use on newer chipsets (for lp4x?) may come close to that. In which case: why ship hex dumps or binaries at all? > > > > > > > > > As far as vendors adding custom flags, I don't see how binary vs text solves any problem there. > > > > The transition here removes the hex-to-bin translation that's been fragile. Michael offers a patch that fixes things for him - that I'm relatively sure breaks building that part of the tree on other UNIX systems, since I vaguely remember having had these issues myself. My guess would be Solaris but it might be some odd BSD as well. > > > > > > > > The text files we ship are plain hex dumps. They don't add anything of value, do they? So why should we pretend that they're "source" and make our live miserable? > > > > > > > > My proposal is to get this in to remove the pain point that this is dealing with (the fragile hex-to-bin translation) and whoever is motivated to do so looks into providing a higher level description for these files and translating things to that, removing the opaque datasets we have (no matter the format) from the tree. > > > > > > spd_tools was already updated to output binary SPD files, so now spd_tools is not usable for adding parts until this change goes in. So this is a 2nd vote for getting this in as is to unblock spd_tools. > > > > > > spd_tools generates SPD binaries from a json input. This could certainly be made part of the build so the generated SPD binaries do not need to be checked in. The only blocker is golang support in the build or rewriting the tool in a supported language. > > > > Why not revert the change that made spd_tools output binaries instead? I'm not convinced using binaries would help with the issue at hand. > > So revert or patch spd_tools to support both hex and binary with a commandline flag. Michael, do you have a preference? I don't have any preference here. Let's just revert it. If we decide later that we need hex output again, this can be added with a flag. -- To view, visit https://review.coreboot.org/c/coreboot/+/44775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f24183a872924cddcfdf7587cc0c126da900f91 Gerrit-Change-Number: 44775 Gerrit-PatchSet: 27 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 02 Oct 2020 10:39:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/acer: Add Acer Aspire ES1-572
by Angel Pons (Code Review) 02 Oct '20

02 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mb/acer: Add Acer Aspire ES1-572 ...................................................................... Patch Set 9: (4 comments) https://review.coreboot.org/c/coreboot/+/38978/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38978/7//COMMIT_MSG@37 PS7, Line 37: - Touchpad. Hangs off either EC or some I2C controller and needs ACPI. > it's connected to EC via PS2 and to SoC via I2C. […] I doubt it's wired using PS/2 to the EC https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 37: register "SataTestMode" = "1" > well, do you really test that low-level or did you just enable it because it says "test" and you wan […] Yes, I do want that. https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/gpio.c: https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 7: #define PAD_CFG_NF_BUF_TRIG(a, b, c, d, e, f) PAD_CFG_NF(a, b, c, d) > just drop e and f below and used PAD_CFG_NF. […] I'd rather re-do the whole file. https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 144: _PAD_CFG_STRUCT(GPP_B3, : PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | : PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | : PAD_BUF(TX_DISABLE), : PAD_PULL(NONE)), : > PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST) for touchpad interrupt I'll re-do the whole file -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Oct 2020 08:26:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/Makefile.inc: fail build when SPD would be empty
by Angel Pons (Code Review) 02 Oct '20

02 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45131 ) Change subject: lib/Makefile.inc: fail build when SPD would be empty ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/45131/14/src/lib/Makefile.inc File src/lib/Makefile.inc: https://review.coreboot.org/c/coreboot/+/45131/14/src/lib/Makefile.inc@360 PS14, Line 360: test -n "$(SPD_SOURCES)" || \ : (echo "HAVE_SPD_BIN_IN_CBFS is set but SPD_SOURCES is empty" && exit 1) > In my opinion, we should allow a board to have empty SPD_SOURCES even when HAVE_SPD_IN_CBFS is set. […] I'd rather avoid getting such incomplete states of board variants into the tree. I expect boards that make it into master to be able to boot, even if half of the features (e.g. Wi-Fi, touchpad, touchscreen, suspend and resume...) don't work. I don't mind if the initial commit adds just a single SPD source, and the rest get added later. -- To view, visit https://review.coreboot.org/c/coreboot/+/45131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6db1dbe5fed5f242e408bcad4f36dda1b1fa1b4 Gerrit-Change-Number: 45131 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Oct 2020 08:23:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/acer: Add Acer Aspire ES1-572
by Michael Niewöhner (Code Review) 02 Oct '20

02 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mb/acer: Add Acer Aspire ES1-572 ...................................................................... Patch Set 9: (3 comments) https://review.coreboot.org/c/coreboot/+/38978/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38978/7//COMMIT_MSG@37 PS7, Line 37: - Touchpad. Hangs off either EC or some I2C controller and needs ACPI. it's connected to EC via PS2 and to SoC via I2C. ACPI is done by the cb i2c driver, when added to the devicetree. fortunately, no need to manually hack around. have a look at CB:43623 for a working example https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/gpio.c: https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 7: #define PAD_CFG_NF_BUF_TRIG(a, b, c, d, e, f) PAD_CFG_NF(a, b, c, d) just drop e and f below and used PAD_CFG_NF. they are not needed to be set for native functions, which is why the macro was removed https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 144: _PAD_CFG_STRUCT(GPP_B3, : PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | : PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | : PAD_BUF(TX_DISABLE), : PAD_PULL(NONE)), : PAD_CFG_GPI_APIC_EDGE_LOW(GPP_B3, NONE, PLTRST) for touchpad interrupt -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Oct 2020 08:18:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/acer: Add Acer Aspire ES1-572
by Michael Niewöhner (Code Review) 02 Oct '20

02 Oct '20

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Change in coreboot[master]: [WIP] mb/acer: Add Acer Aspire ES1-572
by Michael Niewöhner (Code Review) 02 Oct '20

02 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mb/acer: Add Acer Aspire ES1-572 ...................................................................... Patch Set 9: (4 comments) https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 40: register "SataPortsDevSlp[0]" = "0" : register "SataPortsDevSlp[1]" = "0" : > the latter part is exactly why I've left these here. schematics say nooooo ;) https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 42: SataSpeedLimit" = "3" speed 3 (also matches 0) is the default already https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 108: device pci 04.0 off end # CPU Thermal Subsystem > why on? […] it's not about EC ACPI and it's not only about DPTF. device 4 also gets used by linux to read/set TCC and for rapl power limits https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/romstage.c: https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 32: /* These settings are most likely useless if using a release build of FSP */ : mem_cfg->PcdDebugInterfaceFlags = 2; /* 2: Enable UART */ : mem_cfg->PcdSerialIoUartNumber = 2; /* 2: Use UART #2 */ : mem_cfg->PcdSerialDebugBaudRate = 7; /* 7: 115200 baud */ : mem_cfg->PcdSerialDebugLevel = 3; /* 3: Log <= Info */ : well, that's all fsp defaults (except the TH bit in PcdSerialIoUartNumber, which doesn't do anything with TH disabled) -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Oct 2020 08:01:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Expand WP_RO region to 8MB in fmap
by Caveh Jalali (Code Review) 02 Oct '20

02 Oct '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45889 ) Change subject: mb/google/volteer: Expand WP_RO region to 8MB in fmap ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/45889/2/src/mainboard/google/volte… File src/mainboard/google/volteer/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/45889/2/src/mainboard/google/volte… PS2, Line 9: # SPI flash only the top 16MiB actually gets memory mapped. > +1 to what Julius and Tim said. […] intel recently bumped up these regions by 2MB to allow headroom for CSE Lite in CB:43790. -- To view, visit https://review.coreboot.org/c/coreboot/+/45889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72fe8b6a1f91390c218230c0c20825769ebd1e0b Gerrit-Change-Number: 45889 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Oct 2020 07:17:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer
by Karthik Ramasubramanian (Code Review) 02 Oct '20

02 Oct '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45912 ) Change subject: mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312 Gerrit-Change-Number: 45912 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 02 Oct 2020 07:11:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2020