coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/skl: guard ACPI PM timer emulation enablement
by Michael Niewöhner (Code Review) 03 Oct '20

03 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45953 ) Change subject: soc/intel/skl: guard ACPI PM timer emulation enablement ...................................................................... Patch Set 7: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I529cdbe759e9c9270493bd3fff42ded65c74a6b4 Gerrit-Change-Number: 45953 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Oct 2020 22:38:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig
by Michael Niewöhner (Code Review) 03 Oct '20

03 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45955 ) Change subject: soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig ...................................................................... Patch Set 8: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Gerrit-Change-Number: 45955 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Oct 2020 22:38:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{skl,cnl}: drop duplicate PM ACPI timer disabling
by Michael Niewöhner (Code Review) 03 Oct '20

03 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45954 ) Change subject: soc/intel/{skl,cnl}: drop duplicate PM ACPI timer disabling ...................................................................... Patch Set 8: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If370d3acf87ae6d1d7c64bf27228877cdd92ab2d Gerrit-Change-Number: 45954 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Oct 2020 22:38:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer
by Michael Niewöhner (Code Review) 03 Oct '20

03 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45952 ) Change subject: soc/intel/common: add Kconfig to enable/disable the ACPI PM timer ...................................................................... Patch Set 7: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f607f277eb14f84a7370ffb25a13226e7ccc917 Gerrit-Change-Number: 45952 Gerrit-PatchSet: 7 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Oct 2020 22:38:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation
by Michael Niewöhner (Code Review) 03 Oct '20

03 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel/{skl,cnl,icl,tgl,jsl,elh}: deduplicate ACPI timer emulation ...................................................................... Patch Set 5: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Oct 2020 22:38:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Expand WP_RO region to 8MB in fmap
by Julius Werner (Code Review) 02 Oct '20

02 Oct '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45889 ) Change subject: mb/google/volteer: Expand WP_RO region to 8MB in fmap ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/45889/2/src/mainboard/google/volte… File src/mainboard/google/volteer/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/45889/2/src/mainboard/google/volte… PS2, Line 9: # SPI flash only the top 16MiB actually gets memory mapped. > I think it might be really difficult given the size of CSME RW binary. I mean, honestly, if you don't think you can free this space up without taking on real post-ship risks for the platform, then don't do it. Image quality is nice to have but it shouldn't lead to a situation where we can one day not ship an important RW update because it won't fit. The 1200x675 resolution is still "okay", it is readable, it won't be the prettiest Chromebook but it will serve its function. (We are working on changing the bmpblk configuration file so rather than specifying a target resolution, you'd just specify a "quality level", and then this difference wouldn't look so bad anymore. It is not realistic and was never the plan that we would ship native resolution images in flash for a ridiculously hi-res panel like yours. What matters is the optical effect to the user, and that's roughly the same when upscaling a 720p asset to a 1080p or a 4K panel, as long as both of those panels are 13".) -- To view, visit https://review.coreboot.org/c/coreboot/+/45889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72fe8b6a1f91390c218230c0c20825769ebd1e0b Gerrit-Change-Number: 45889 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Oct 2020 20:37:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Fix raminit
by Felix Singer (Code Review) 02 Oct '20

02 Oct '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45928 ) Change subject: mb/clevo/l140cu: Fix raminit ...................................................................... mb/clevo/l140cu: Fix raminit Add romstage.c to Makefile to fix raminit. Change-Id: I7afbf1574803128f7d62592eed2398c945334757 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/45928/1 diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc b/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc index 3d742d6..bd3e899 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc +++ b/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.inc @@ -1,4 +1,5 @@ bootblock-y += bootblock.c +romstage-y += romstage.c ramstage-y += ramstage.c ramstage-y += hda_verb.c SPD_SOURCES = samsung-K4AAG165WA-BCTD -- To view, visit https://review.coreboot.org/c/coreboot/+/45928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7afbf1574803128f7d62592eed2398c945334757 Gerrit-Change-Number: 45928 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: tgl/usb: disable TBT if hardware is not USB4
by Nick Vaccaro (Code Review) 02 Oct '20

02 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45832 ) Change subject: tgl/usb: disable TBT if hardware is not USB4 ...................................................................... tgl/usb: disable TBT if hardware is not USB4 TBT being enabled in FSP without USB4 hardware causes an issue powering off in depthcharge. Disable TBT for FSP if USB hardware is not USB4. BUG=b:167983038 TEST=none Change-Id: I07d5c416c79c40e9f85d721930549cf3374d327c Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/lib/fw_config.c M src/soc/intel/tigerlake/fsp_params.c M src/soc/intel/tigerlake/romstage/fsp_params.c 3 files changed, 34 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/45832/1 diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c index fdfab0a..ec32059 100644 --- a/src/lib/fw_config.c +++ b/src/lib/fw_config.c @@ -127,5 +127,5 @@ } } } -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, fw_config_init, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, fw_config_init, NULL); #endif diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 38f444b..62316c4 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -310,10 +310,15 @@ /* USB4/TBT */ for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { dev = pcidev_on_root(SA_DEV_SLOT_TBT, i); - if (dev) + if (is_dev_enabled(dev)) { + printk(BIOS_INFO, + "ITbtPcieRootPortEn%d is enabled\n", i); params->ITbtPcieRootPortEn[i] = dev->enabled; - else + } else { + printk(BIOS_INFO, + "ITbtPcieRootPortEn%d is disabled\n", i); params->ITbtPcieRootPortEn[i] = 0; + } } /* PCH FIVR settings override */ diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 3957299..569264c 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -14,6 +14,7 @@ #include <soc/romstage.h> #include <soc/soc_chip.h> #include <string.h> +#include <fw_config.h> static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_tigerlake_config *config) @@ -21,6 +22,7 @@ unsigned int i; uint32_t cpu_id, mask = 0; const struct device *dev; + bool usb4_device; /* * If IGD is enabled, set IGD stolen size to 60MB. @@ -115,19 +117,40 @@ m_cfg->TcssXhciEn = config->TcssXhciEn; m_cfg->TcssXdciEn = config->TcssXdciEn; + usb4_device = fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || + fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)); + /* TCSS DMA */ dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0); - m_cfg->TcssDma0En = is_dev_enabled(dev); + if (is_dev_enabled(dev) && usb4_device) { + printk(BIOS_INFO, "TcssDma0En is enabled by fw_config\n"); + m_cfg->TcssDma0En = 1; + } else { + printk(BIOS_INFO, "TcssDma0En is disabled by fw_config\n"); + m_cfg->TcssDma0En = 0; + } dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1); m_cfg->TcssDma1En = is_dev_enabled(dev); /* USB4/TBT */ dev = pcidev_path_on_root(SA_DEVFN_TBT0); - m_cfg->TcssItbtPcie0En = is_dev_enabled(dev); + if (is_dev_enabled(dev) && usb4_device) { + printk(BIOS_INFO, "TcssItbtPcie0En is enabled by fw_config\n"); + m_cfg->TcssItbtPcie0En = 1; + } else { + printk(BIOS_INFO, "TcssItbtPcie0En is disabled by fw_config\n"); + m_cfg->TcssItbtPcie0En = 0; + } dev = pcidev_path_on_root(SA_DEVFN_TBT1); - m_cfg->TcssItbtPcie1En = is_dev_enabled(dev); + if (is_dev_enabled(dev) && usb4_device) { + printk(BIOS_INFO, "TcssItbtPcie1En is enabled by fw_config\n"); + m_cfg->TcssItbtPcie1En = 1; + } else { + printk(BIOS_INFO, "TcssItbtPcie1En is disabled by fw_config\n"); + m_cfg->TcssItbtPcie1En = 0; + } dev = pcidev_path_on_root(SA_DEVFN_TBT2); m_cfg->TcssItbtPcie2En = is_dev_enabled(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/45832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07d5c416c79c40e9f85d721930549cf3374d327c Gerrit-Change-Number: 45832 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER
by Michael Niewöhner (Code Review) 02 Oct '20

02 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45960 ) Change subject: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ce4f5168586bf305969b2e24b6ee895c8552749 Gerrit-Change-Number: 45960 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Fri, 02 Oct 2020 18:30:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS
by Michael Niewöhner (Code Review) 02 Oct '20

02 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45959 ) Change subject: mb/clevo/l140cu: set PS/2 timeout for SeaBIOS ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2be75961035f04a7ffa6f7e1dbaabb1243b857f9 Gerrit-Change-Number: 45959 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Comment-Date: Fri, 02 Oct 2020 18:30:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2020