coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/xeon_sp/acpi: Rename pci_irq.asl
by Marc Jones (Code Review) 03 Oct '20

03 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45834 ) Change subject: soc/intel/xeon_sp/acpi: Rename pci_irq.asl ...................................................................... soc/intel/xeon_sp/acpi: Rename pci_irq.asl Rename pci_irq.asl to pci_irqs.asl to match other intel soc file names. This makes comparing differences much easier. Change-Id: I622dfef675c3df2dff7a3024ccbe14c356a5cd86 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- R src/soc/intel/xeon_sp/acpi/pci_irqs.asl M src/soc/intel/xeon_sp/acpi/uncore.asl 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/45834/1 diff --git a/src/soc/intel/xeon_sp/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/acpi/pci_irqs.asl similarity index 100% rename from src/soc/intel/xeon_sp/acpi/pci_irq.asl rename to src/soc/intel/xeon_sp/acpi/pci_irqs.asl diff --git a/src/soc/intel/xeon_sp/acpi/uncore.asl b/src/soc/intel/xeon_sp/acpi/uncore.asl index b1b5f6c..236ae75 100644 --- a/src/soc/intel/xeon_sp/acpi/uncore.asl +++ b/src/soc/intel/xeon_sp/acpi/uncore.asl @@ -26,7 +26,7 @@ Scope (\_SB) { - #include "pci_irq.asl" + #include "pci_irqs.asl" #include "uncore_irq.asl" #include "iiostack.asl" } -- To view, visit https://review.coreboot.org/c/coreboot/+/45834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I622dfef675c3df2dff7a3024ccbe14c356a5cd86 Gerrit-Change-Number: 45834 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Clean up pci_devs.h
by Marc Jones (Code Review) 03 Oct '20

03 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45833 ) Change subject: soc/intel/xeon_sp: Clean up pci_devs.h ...................................................................... soc/intel/xeon_sp: Clean up pci_devs.h Prepare for merging cpx and skx pci_devs.h. Remove duplicate defines. Move defines so the match each other. Checked TiogaPass and DeltaLake BUILD_TIMELESS. Change-Id: I146dd9e3f7eba053977d48dcf34d927dea310059 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h 2 files changed, 55 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45833/1 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 3781783..965bb66 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -71,21 +71,26 @@ #define VTD_CAP_HIGH 0x0C #define VTD_EXT_CAP_HIGH 0x14 +/* CPU Devices */ +#define CBDMA_DEV_NUM 0x04 + +#define VMD_DEV_NUM 0x05 +#define VMD_FUNC_NUM 0x05 + +#define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define VTD_DEV 0x5 +#define VTD_FUNC 0x0 + +#define APIC_DEV_NUM 0x05 +#define APIC_FUNC_NUM 0x04 + + /* PCH Device info */ #define XHCI_BUS_NUMBER 0x0 #define PCH_DEV_SLOT_XHCI 0x14 -#define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2) - #define XHCI_FUNC_NUM 0x0 - -#define HPET_BUS_NUM 0x0 -#define HPET_DEV_NUM PCH_DEV_SLOT_LPC -#define HPET0_FUNC_NUM 0x00 - -#define MMAP_VTD_CFG_REG_DEVID 0x2024 -#define VTD_DEV 5 -#define VTD_FUNC 0 +#define PCH_DEVFN_THERMAL _PCH_DEVFN(XHCI, 2) #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) @@ -97,14 +102,9 @@ #define PCH_DEV_PMC _PCH_DEV(LPC, 2) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) -#define CBDMA_DEV_NUM 0x04 -#define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function - -#define VMD_DEV_NUM 0x05 -#define VMD_FUNC_NUM 0x05 - -#define APIC_DEV_NUM 0x05 -#define APIC_FUNC_NUM 0x04 +#define HPET_BUS_NUM 0x0 +#define HPET_DEV_NUM PCH_DEV_SLOT_LPC +#define HPET0_FUNC_NUM 0x00 #define PCH_IOAPIC_BUS_NUMBER 0x00 #define PCH_IOAPIC_DEV_NUM 0x1F diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 62aa4d1..ab85378 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -31,10 +31,10 @@ #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif -#define SAD_ALL_DEV 29 -#define SAD_ALL_FUNC 0 -#define SAD_ALL_PAM0123_CSR 0x40 -#define SAD_ALL_PAM456_CSR 0x44 +#define SAD_ALL_DEV 29 +#define SAD_ALL_FUNC 0 +#define SAD_ALL_PAM0123_CSR 0x40 +#define SAD_ALL_PAM456_CSR 0x44 #define PCU_IIO_STACK 1 #define PCU_DEV 30 @@ -54,45 +54,45 @@ #define PCU_CR1_BIOS_MB_DATA_REG 0x8c #define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 -#define BIOS_MB_RUN_BUSY_MASK ((uint32_t)1 << 31) -#define BIOS_MB_CMD_MASK ((uint32_t)0xff) +#define BIOS_MB_RUN_BUSY_MASK BIT(31) +#define BIOS_MB_CMD_MASK 0xff #define BIOS_CMD_READ_PCU_MISC_CFG 0x5 #define BIOS_CMD_WRITE_PCU_MISC_CFG 0x6 #define BIOS_ERR_INVALID_CMD 0x01 #define PCU_CR1_BIOS_RESET_CPL_REG 0x94 -#define RST_CPL1_MASK ((uint32_t)1 << 1) -#define RST_CPL2_MASK ((uint32_t)1 << 2) -#define RST_CPL3_MASK ((uint32_t)1 << 3) -#define RST_CPL4_MASK ((uint32_t)1 << 4) -#define PCODE_INIT_DONE1_MASK ((uint32_t)1 << 9) -#define PCODE_INIT_DONE2_MASK ((uint32_t)1 << 10) -#define PCODE_INIT_DONE3_MASK ((uint32_t)1 << 11) -#define PCODE_INIT_DONE4_MASK ((uint32_t)1 << 12) +#define RST_CPL1_MASK BIT(1) +#define RST_CPL2_MASK BIT(2) +#define RST_CPL3_MASK BIT(3) +#define RST_CPL4_MASK BIT(4) +#define PCODE_INIT_DONE1_MASK BIT(9) +#define PCODE_INIT_DONE2_MASK BIT(10) +#define PCODE_INIT_DONE3_MASK BIT(11) +#define PCODE_INIT_DONE4_MASK BIT(12) #define PCU_CR1_DESIRED_CORES_CFG2_REG 0xa0 -#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK ((uint32_t)1 << 31) +#define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) -#define UBOX_DECS_BUS 0 -#define UBOX_DECS_DEV 8 -#define UBOX_DECS_FUNC 2 -#define UBOX_DECS_CPUBUSNO_CSR 0xcc +#define UBOX_DECS_BUS 0 +#define UBOX_DECS_DEV 8 +#define UBOX_DECS_FUNC 2 +#define UBOX_DECS_CPUBUSNO_CSR 0xcc -#define VTD_TOLM_CSR 0xd0 -#define VTD_TSEG_BASE_CSR 0xa8 -#define VTD_TSEG_LIMIT_CSR 0xac -#define VTD_EXT_CAP_LOW 0x10 -#define VTD_MMCFG_BASE_CSR 0x90 -#define VTD_MMCFG_LIMIT_CSR 0x98 -#define VTD_TOHM_CSR 0xd4 -#define VTD_MMIOL_CSR 0xdc -#define VTD_ME_BASE_CSR 0xf0 -#define VTD_ME_LIMIT_CSR 0xf8 -#define VTD_VERSION 0x00 -#define VTD_CAP 0x08 -#define VTD_CAP_LOW 0x08 -#define VTD_CAP_HIGH 0x0C -#define VTD_EXT_CAP_HIGH 0x14 +#define VTD_TOLM_CSR 0xd0 +#define VTD_TSEG_BASE_CSR 0xa8 +#define VTD_TSEG_LIMIT_CSR 0xac +#define VTD_EXT_CAP_LOW 0x10 +#define VTD_MMCFG_BASE_CSR 0x90 +#define VTD_MMCFG_LIMIT_CSR 0x98 +#define VTD_TOHM_CSR 0xd4 +#define VTD_MMIOL_CSR 0xdc +#define VTD_ME_BASE_CSR 0xf0 +#define VTD_ME_LIMIT_CSR 0xf8 +#define VTD_VERSION 0x00 +#define VTD_CAP 0x08 +#define VTD_CAP_LOW 0x08 +#define VTD_CAP_HIGH 0x0C +#define VTD_EXT_CAP_HIGH 0x14 #define PCU_CR1_C2C3TT_REG 0xdc #define PCU_CR1_PCIE_ILTR_OVRD 0xfc @@ -126,9 +126,9 @@ #define HPET_DEV_NUM PCH_DEV_SLOT_LPC #define HPET0_FUNC_NUM 0x00 -#define MMAP_VTD_CFG_REG_DEVID 0x2024 -#define VTD_DEV 5 -#define VTD_FUNC 0 +#define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define VTD_DEV 5 +#define VTD_FUNC 0 #define PCH_DEV_SLOT_LPC 0x1f #define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) @@ -140,7 +140,6 @@ #define PCH_DEV_PMC _PCH_DEV(LPC, 2) #define PCH_DEV_SPI _PCH_DEV(LPC, 5) - #define CBDMA_DEV_NUM 0x04 #define IIO_CBDMA_MMIO_SIZE 0x10000 //64kB for one CBDMA function #define IIO_CBDMA_MMIO_ALIGNMENT 14 //2^14 - 16kB -- To view, visit https://review.coreboot.org/c/coreboot/+/45833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I146dd9e3f7eba053977d48dcf34d927dea310059 Gerrit-Change-Number: 45833 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/nuvoton: Add back Nuvoton NCT6776 support
by Paul Menzel (Code Review) 03 Oct '20

03 Oct '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/16519 ) Change subject: superio/nuvoton: Add back Nuvoton NCT6776 support ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/16519/9/src/superio/nuvoton/nct677… File src/superio/nuvoton/nct6776/Kconfig: https://review.coreboot.org/c/coreboot/+/16519/9/src/superio/nuvoton/nct677… PS9, Line 23: default n It looks like this wasn’t just a revert after all. At least that Kconfig symbol did not exist back then. -- To view, visit https://review.coreboot.org/c/coreboot/+/16519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I546879285ad8336e81798d0fbdf94f72e1fa61a2 Gerrit-Change-Number: 16519 Gerrit-PatchSet: 9 Gerrit-Owner: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 03 Oct 2020 09:00:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER
by Subrata Banik (Code Review) 03 Oct '20

03 Oct '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45960 ) Change subject: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ce4f5168586bf305969b2e24b6ee895c8552749 Gerrit-Change-Number: 45960 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 03 Oct 2020 07:41:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER
by HAOUAS Elyes (Code Review) 03 Oct '20

03 Oct '20

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45960 ) Change subject: mb/clevo/l140cu: drop USE_LEGACY_8254_TIMER ...................................................................... Patch Set 1: Please, is it also true for the other platforms ? 'grep -r USE_LEGACY_8254_TIMER' -- To view, visit https://review.coreboot.org/c/coreboot/+/45960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ce4f5168586bf305969b2e24b6ee895c8552749 Gerrit-Change-Number: 45960 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 03 Oct 2020 07:37:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Make use of PMC low power program from common block
by Subrata Banik (Code Review) 03 Oct '20

03 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45796 ) Change subject: soc/intel: Make use of PMC low power program from common block ...................................................................... soc/intel: Make use of PMC low power program from common block List of changes: 1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory 2. Remove redundant PMC programming from SoC and refer to common code block 3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC function. Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/finalize.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/finalize.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/finalize.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/finalize.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/finalize.c 12 files changed, 34 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/45796/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f792e70..ae18f94 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -97,6 +97,7 @@ select PLATFORM_USES_FSP2_0 select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 315c67a..9eb9cbe 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -9,6 +9,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <spi-generic.h> @@ -44,7 +45,6 @@ uint32_t reg32; uint8_t *pmcbase; config_t *config; - uint8_t reg8; tco_lockdown(); @@ -70,17 +70,12 @@ */ config = config_of_soc(); pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer(); if (config->s0ix_enable) { /* Disable XTAL shutdown qualification for low power idle. */ - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); + pmc_ignore_xtal_shutdown(); if (config->cppmvric2_adsposcdis) { /* Enable Audio DSP OSC qualification for S0ix */ diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index ba04a4f..1a33c92 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -33,6 +33,7 @@ select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index e9b3f21..bae8bcf 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -9,6 +9,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <soc/p2sb.h> @@ -22,10 +23,7 @@ static void pch_finalize(void) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - uint8_t reg8; /* TCO Lock down */ tco_lockdown(); @@ -44,19 +42,12 @@ * returns NULL for PCH_DEV_PMC device. */ config = config_of_soc(); - pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer(); /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown(); pmc_clear_pmcon_sts(); } diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 60cb5e5..3869c95 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -31,6 +31,7 @@ select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 53e3cba..363f579 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -9,6 +9,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <spi-generic.h> @@ -40,10 +41,7 @@ static void pch_finalize(void) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - uint8_t reg8; /* TCO Lock down */ tco_lockdown(); @@ -69,19 +67,12 @@ * returns NULL for PCH_DEV_PMC device. */ config = config_of_soc(); - pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer(); /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown(); pch_handle_sideband(config); diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 2282655..9ebf3b7 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -33,6 +33,7 @@ select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 08a6bab..ef574d9 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -9,6 +9,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <spi-generic.h> @@ -40,10 +41,7 @@ static void pch_finalize(void) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - uint8_t reg8; /* TCO Lock down */ tco_lockdown(); @@ -62,19 +60,12 @@ * returns NULL for PCH_DEV_PMC device. */ config = config_of_soc(); - pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer(); /* Disable XTAL shutdown qualification for low power idle. */ if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + pmc_ignore_xtal_shutdown(); pch_handle_sideband(config); diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 155df58..c48b902 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -43,6 +43,7 @@ select REG_SCRIPT select SA_ENABLE_DPR select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 0294a72..ff32189 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -13,6 +13,7 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <spi-generic.h> @@ -44,17 +45,13 @@ static void pch_finalize_script(struct device *dev) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - u8 reg8; tco_lockdown(); /* Display me status before we hide it */ intel_me_status(); - pmcbase = pmc_mmio_regs(); config = config_of(dev); /* @@ -73,18 +70,12 @@ * Disabling ACPI PM timer also switches off TCO */ - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer(); /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown(); /* we should disable Heci1 based on the devicetree policy */ if (config->HeciEnabled == 0) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 7e143c1..7db43ca 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -34,6 +34,7 @@ select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK + select PMC_LOW_POWER_MODE_PROGRAM select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index 5bf01de..2cc9671 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -15,6 +15,7 @@ #include <device/pci.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/tco.h> #include <intelblocks/thermal.h> #include <spi-generic.h> @@ -28,10 +29,7 @@ static void pch_finalize(void) { - uint32_t reg32; - uint8_t *pmcbase; config_t *config; - uint8_t reg8; /* TCO Lock down */ tco_lockdown(); @@ -50,19 +48,12 @@ * returns NULL for PCH_DEV_PMC device. */ config = config_of_soc(); - pmcbase = pmc_mmio_regs(); - if (config->PmTimerDisabled) { - reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); - reg8 |= (1 << 1); - write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); - } + if (config->PmTimerDisabled) + pmc_disable_acpi_timer(); /* Disable XTAL shutdown qualification for low power idle. */ - if (config->s0ix_enable) { - reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; - write32(pmcbase + CPPMVRIC, reg32); - } + if (config->s0ix_enable) + pmc_ignore_xtal_shutdown(); pmc_clear_pmcon_sts(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b Gerrit-Change-Number: 45796 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: soc/intel: Make use of IA common LPC code block
by Subrata Banik (Code Review) 03 Oct '20

03 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45789 ) Change subject: soc/intel: Make use of IA common LPC code block ...................................................................... soc/intel: Make use of IA common LPC code block This patch removes redundant LPC functions from SoC directory and refer from block/lpc directory. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/cpx/chip.c 9 files changed, 20 insertions(+), 645 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/45789/1 diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 50af9ee..c7f7a29 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -90,115 +90,13 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { const config_t *config = dev->chip_info; /* Legacy initialization */ isa_dma_init(); - pch_misc_init(); + lpc_pch_misc_init(); /* Enable CLKRUN_EN for power gating LPC */ lpc_enable_pci_clk_cntl(); @@ -207,8 +105,8 @@ lpc_set_serirq_mode(config->serirq_mode); /* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + lpc_pch_enable_ioapic(); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 538a81e..4de54e3 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -282,7 +282,7 @@ lpc_set_gen_decode_range(gen_io_dec); soc_setup_dmi_pcr_io_dec(gen_io_dec); if (ENV_PAYLOAD_LOADER) - soc_pch_pirq_init(dev); + lpc_pch_pirq_init(); } void lpc_enable_pci_clk_cntl(void) diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index 7133997..92782a08 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -64,113 +64,11 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_enable_ioapic(const struct device *dev) -{ - uint32_t reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - uint8_t int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(NMI_STS_CNT) & 0xf0); - outb((reg8 | (1 << 2)), NMI_STS_CNT); - - /* Disable NMI sources */ - outb((1 << 7), NMI_EN); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ isa_dma_init(); - pch_misc_init(); + lpc_pch_misc_init(); /* Enable CLKRUN_EN for power gating ESPI */ lpc_enable_pci_clk_cntl(); @@ -182,8 +80,8 @@ lpc_set_serirq_mode(SERIRQ_QUIET); /* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + lpc_pch_enable_ioapic(); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 1497c8d..71cbbe3 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -83,113 +83,11 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ isa_dma_init(); - pch_misc_init(); + lpc_pch_misc_init(); /* Enable CLKRUN_EN for power gating ESPI */ lpc_enable_pci_clk_cntl(); @@ -201,8 +99,8 @@ lpc_set_serirq_mode(SERIRQ_QUIET); /* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + lpc_pch_enable_ioapic(); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index bf82067..2061a29 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -65,113 +65,11 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ isa_dma_init(); - pch_misc_init(); + lpc_pch_misc_init(); /* Enable CLKRUN_EN for power gating ESPI */ lpc_enable_pci_clk_cntl(); @@ -183,8 +81,8 @@ lpc_set_serirq_mode(SERIRQ_QUIET); /* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + lpc_pch_enable_ioapic(); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index 62050c9..ad75f02 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -215,71 +215,3 @@ /* TCO Irq enable/disable */ params->TcoIrqEnable = config->TcoIrqEnable; } - -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - struct device *irq_dev; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 7dc90f0..ecea3e2 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -29,29 +29,6 @@ return skl_lpc_fixed_mmio_ranges; } -static void pch_enable_ioapic(struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} - void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) { const config_t *config = config_of(dev); @@ -72,10 +49,6 @@ } static const struct reg_script pch_misc_init_script[] = { - /* Setup NMI on errors, disable SERR */ - REG_IO_RMW8(0x61, ~0xf0, (1 << 2)), - /* Disable NMI sources */ - REG_IO_OR8(0x70, (1 << 7)), /* Enable BIOS updates outside of SMM */ REG_PCI_RMW8(0xdc, ~(1 << 5), 0), REG_SCRIPT_END @@ -87,6 +60,7 @@ /* Legacy initialization */ isa_dma_init(); + lpc_pch_misc_init(); reg_script_run_on_dev(PCH_DEV_LPC, pch_misc_init_script); /* Enable CLKRUN_EN for power gating LPC */ @@ -96,8 +70,8 @@ lpc_set_serirq_mode(config->serirq_mode); /* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + lpc_pch_enable_ioapic(); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); } diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 513da5a..2ae8679 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -71,113 +71,11 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -static void pch_enable_ioapic(const struct device *dev) -{ - u32 reg32; - /* PCH-LP has 120 redirection entries */ - const int redir_entries = 120; - - set_ioapic_id((void *)IO_APIC_ADDR, 0x02); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - - reg32 &= ~0x00ff0000; - reg32 |= (redir_entries - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); -} -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - -static void pch_misc_init(void) -{ - uint8_t reg8; - - /* Setup NMI on errors, disable SERR */ - reg8 = (inb(0x61)) & 0xf0; - outb((reg8 | (1 << 2)), 0x61); - - /* Disable NMI sources */ - outb((1 << 7), 0x70); -}; - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ isa_dma_init(); - pch_misc_init(); + lpc_pch_misc_init(); /* Enable CLKRUN_EN for power gating ESPI */ lpc_enable_pci_clk_cntl(); @@ -189,8 +87,8 @@ lpc_set_serirq_mode(SERIRQ_QUIET); /* Interrupt configuration */ - pch_enable_ioapic(dev); - soc_pch_pirq_init(dev); + lpc_pch_enable_ioapic(); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 2c445f9..2fcc192 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -545,27 +545,6 @@ DEV_FUNC_EXIT(dev); } -static void pch_enable_ioapic(const struct device *dev) -{ - uint32_t reg32; - - set_ioapic_id((void *)IO_APIC_ADDR, 2); - - /* affirm full set of redirection table entries ("write once") */ - reg32 = io_apic_read((void *)IO_APIC_ADDR, 1); - - reg32 &= ~0x00ff0000; - reg32 |= (C620_IOAPIC_REDIR_ENTRIES - 1) << 16; - - io_apic_write((void *)IO_APIC_ADDR, 1, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 3, 1); -} - struct pci_operations soc_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; @@ -592,7 +571,7 @@ { printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(false); - pch_enable_ioapic(NULL); + lpc_pch_enable_ioapic(); setup_lapic(); p2sb_unhide(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Gerrit-Change-Number: 45789 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 18

Change in coreboot[master]: soc/intel: Move soc_pch_pirq_init() to common code
by Subrata Banik (Code Review) 03 Oct '20

03 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45809 ) Change subject: soc/intel: Move soc_pch_pirq_init() to common code ...................................................................... soc/intel: Move soc_pch_pirq_init() to common code List of changes: 1. Rename soc_pch_pirq_init() as lpc_pch_pirq_init() and move into common block code. 2. Removes redundant LPC functions from SoC directory and refer from block/lpc directory. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: I856b5ca024e58fd14b4d1721f23d9516a283ebf8 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c 9 files changed, 78 insertions(+), 415 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/45809/1 diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 67c5936..59a3e0f 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -90,74 +90,6 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - static void pch_misc_init(void) { uint8_t reg8; @@ -186,7 +118,7 @@ /* Interrupt configuration */ lpc_pch_enable_ioapic(); - soc_pch_pirq_init(dev); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 18ef87e..bae646f 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -109,5 +109,7 @@ uintptr_t base, size_t size, unsigned long flags); /* Enable PCH IOAPIC */ void lpc_pch_enable_ioapic(void); +/* Retrieve and setup PCH LPC interrupt routing. */ +void lpc_pch_pirq_init(void); #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 8d0c683..268736e 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -7,9 +7,11 @@ #include <console/console.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> #include <lib.h> #include "lpc_def.h" +#include <soc/irq.h> #include <soc/pci_devs.h> uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables) @@ -280,7 +282,7 @@ lpc_set_gen_decode_range(gen_io_dec); soc_setup_dmi_pcr_io_dec(gen_io_dec); if (ENV_PAYLOAD_LOADER) - soc_pch_pirq_init(dev); + lpc_pch_pirq_init(); } void lpc_enable_pci_clk_cntl(void) @@ -317,3 +319,70 @@ */ io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); } + +/* + * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control + * 0x00 - 0000 = Reserved + * 0x01 - 0001 = Reserved + * 0x02 - 0010 = Reserved + * 0x03 - 0011 = IRQ3 + * 0x04 - 0100 = IRQ4 + * 0x05 - 0101 = IRQ5 + * 0x06 - 0110 = IRQ6 + * 0x07 - 0111 = IRQ7 + * 0x08 - 1000 = Reserved + * 0x09 - 1001 = IRQ9 + * 0x0A - 1010 = IRQ10 + * 0x0B - 1011 = IRQ11 + * 0x0C - 1100 = IRQ12 + * 0x0D - 1101 = Reserved + * 0x0E - 1110 = IRQ14 + * 0x0F - 1111 = IRQ15 + * PIRQ[n]_ROUT[7] - PIRQ Routing Control + * 0x80 - The PIRQ is not routed. + */ +void lpc_pch_pirq_init(void) +{ + const struct device *irq_dev; + uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; + + pch_interrupt_routing[0] = PCH_IRQ11; + pch_interrupt_routing[1] = PCH_IRQ10; + pch_interrupt_routing[2] = PCH_IRQ11; + pch_interrupt_routing[3] = PCH_IRQ11; + pch_interrupt_routing[4] = PCH_IRQ11; + pch_interrupt_routing[5] = PCH_IRQ11; + pch_interrupt_routing[6] = PCH_IRQ11; + pch_interrupt_routing[7] = PCH_IRQ11; + + itss_irq_init(pch_interrupt_routing); + + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + uint8_t int_pin = 0, int_line = 0; + + if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + continue; + + int_pin = pci_read_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_PIN); + + switch (int_pin) { + case 1: /* INTA# */ + int_line = PCH_IRQ11; + break; + case 2: /* INTB# */ + int_line = PCH_IRQ10; + break; + case 3: /* INTC# */ + int_line = PCH_IRQ11; + break; + case 4: /* INTD# */ + int_line = PCH_IRQ11; + break; + } + + if (!int_line) + continue; + + pci_write_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_LINE, int_line); + } +} diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index 79399c3..32fa6a4 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -64,74 +64,6 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - uint8_t int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - static void pch_misc_init(void) { uint8_t reg8; @@ -161,7 +93,7 @@ /* Interrupt configuration */ lpc_pch_enable_ioapic(); - soc_pch_pirq_init(dev); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 2092224..e51e6a2 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -83,74 +83,6 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - static void pch_misc_init(void) { uint8_t reg8; @@ -180,7 +112,7 @@ /* Interrupt configuration */ lpc_pch_enable_ioapic(); - soc_pch_pirq_init(dev); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index 4f4ade2..ae8697a 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -65,74 +65,6 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - static void pch_misc_init(void) { uint8_t reg8; @@ -162,7 +94,7 @@ /* Interrupt configuration */ lpc_pch_enable_ioapic(); - soc_pch_pirq_init(dev); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index 62050c9..ad75f02 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -215,71 +215,3 @@ /* TCO Irq enable/disable */ params->TcoIrqEnable = config->TcoIrqEnable; } - -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - struct device *irq_dev; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 7ae282b..6f04fe3 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -74,7 +74,7 @@ /* Interrupt configuration */ lpc_pch_enable_ioapic(); - soc_pch_pirq_init(dev); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); } diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index 2e9d6d9..68deea6 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -71,74 +71,6 @@ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); } -/* - * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control - * 0x00 - 0000 = Reserved - * 0x01 - 0001 = Reserved - * 0x02 - 0010 = Reserved - * 0x03 - 0011 = IRQ3 - * 0x04 - 0100 = IRQ4 - * 0x05 - 0101 = IRQ5 - * 0x06 - 0110 = IRQ6 - * 0x07 - 0111 = IRQ7 - * 0x08 - 1000 = Reserved - * 0x09 - 1001 = IRQ9 - * 0x0A - 1010 = IRQ10 - * 0x0B - 1011 = IRQ11 - * 0x0C - 1100 = IRQ12 - * 0x0D - 1101 = Reserved - * 0x0E - 1110 = IRQ14 - * 0x0F - 1111 = IRQ15 - * PIRQ[n]_ROUT[7] - PIRQ Routing Control - * 0x80 - The PIRQ is not routed. - */ - -void soc_pch_pirq_init(const struct device *dev) -{ - struct device *irq_dev; - uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; - - pch_interrupt_routing[0] = PCH_IRQ11; - pch_interrupt_routing[1] = PCH_IRQ10; - pch_interrupt_routing[2] = PCH_IRQ11; - pch_interrupt_routing[3] = PCH_IRQ11; - pch_interrupt_routing[4] = PCH_IRQ11; - pch_interrupt_routing[5] = PCH_IRQ11; - pch_interrupt_routing[6] = PCH_IRQ11; - pch_interrupt_routing[7] = PCH_IRQ11; - - itss_irq_init(pch_interrupt_routing); - - for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin = 0, int_line = 0; - - if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) - continue; - - int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); - - switch (int_pin) { - case 1: /* INTA# */ - int_line = PCH_IRQ11; - break; - case 2: /* INTB# */ - int_line = PCH_IRQ10; - break; - case 3: /* INTC# */ - int_line = PCH_IRQ11; - break; - case 4: /* INTD# */ - int_line = PCH_IRQ11; - break; - } - - if (!int_line) - continue; - - pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); - } -} - static void pch_misc_init(void) { uint8_t reg8; @@ -168,7 +100,7 @@ /* Interrupt configuration */ lpc_pch_enable_ioapic(); - soc_pch_pirq_init(dev); + lpc_pch_pirq_init(); setup_i8259(); i8259_configure_irq_trigger(9, 1); soc_mirror_dmi_pcr_io_dec(); -- To view, visit https://review.coreboot.org/c/coreboot/+/45809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I856b5ca024e58fd14b4d1721f23d9516a283ebf8 Gerrit-Change-Number: 45809 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: soc/intel/common/block/lpc: Move common LPC function into block/lpc
by Subrata Banik (Code Review) 03 Oct '20

03 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45787 ) Change subject: soc/intel/common/block/lpc: Move common LPC function into block/lpc ...................................................................... soc/intel/common/block/lpc: Move common LPC function into block/lpc This patch moves 3 common LPC functions into common block code. Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_lib.c 2 files changed, 117 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/45787/1 diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index ff4ba1a..65e2c0a 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -107,5 +107,15 @@ /* Add resource into LPC PCI device space */ void pch_lpc_add_new_resource(struct device *dev, uint8_t offset, uintptr_t base, size_t size, unsigned long flags); +/* Enable PCH IOAPIC */ +void lpc_pch_enable_ioapic(void); +/* Retrieve and setup PCH LPC interrupt routing. */ +void lpc_pch_pirq_init(void); +/* + * LPC MISC programming + * 1. Setup NMI on errors, disable SERR + * 2. Disable NMI sources + */ +void lpc_pch_misc_init(void); #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index ff44cc1..538a81e 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -2,13 +2,16 @@ #define __SIMPLE_DEVICE__ +#include <arch/ioapic.h> #include <assert.h> #include <console/console.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> #include <lib.h> #include "lpc_def.h" +#include <soc/irq.h> #include <soc/pci_devs.h> uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables) @@ -292,3 +295,107 @@ const uint8_t pcctl = pci_read_config8(PCH_DEV_LPC, LPC_PCCTL); pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN); } + +/* Enable PCH IOAPIC */ +void lpc_pch_enable_ioapic(void) +{ + uint32_t reg32; + /* PCH-LP has 120 redirection entries */ + const int redir_entries = 120; + + set_ioapic_id((void *)IO_APIC_ADDR, 0x02); + + /* affirm full set of redirection table entries ("write once") */ + reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); + + reg32 &= ~0x00ff0000; + reg32 |= (redir_entries - 1) << 16; + + io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); + + /* + * Select Boot Configuration register (0x03) and + * use Processor System Bus (0x01) to deliver interrupts. + */ + io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); +} + +/* + * PIRQ[n]_ROUT[3:0] - PIRQ Routing Control + * 0x00 - 0000 = Reserved + * 0x01 - 0001 = Reserved + * 0x02 - 0010 = Reserved + * 0x03 - 0011 = IRQ3 + * 0x04 - 0100 = IRQ4 + * 0x05 - 0101 = IRQ5 + * 0x06 - 0110 = IRQ6 + * 0x07 - 0111 = IRQ7 + * 0x08 - 1000 = Reserved + * 0x09 - 1001 = IRQ9 + * 0x0A - 1010 = IRQ10 + * 0x0B - 1011 = IRQ11 + * 0x0C - 1100 = IRQ12 + * 0x0D - 1101 = Reserved + * 0x0E - 1110 = IRQ14 + * 0x0F - 1111 = IRQ15 + * PIRQ[n]_ROUT[7] - PIRQ Routing Control + * 0x80 - The PIRQ is not routed. + */ +void lpc_pch_pirq_init(void) +{ + const struct device *irq_dev; + uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG]; + + pch_interrupt_routing[0] = PCH_IRQ11; + pch_interrupt_routing[1] = PCH_IRQ10; + pch_interrupt_routing[2] = PCH_IRQ11; + pch_interrupt_routing[3] = PCH_IRQ11; + pch_interrupt_routing[4] = PCH_IRQ11; + pch_interrupt_routing[5] = PCH_IRQ11; + pch_interrupt_routing[6] = PCH_IRQ11; + pch_interrupt_routing[7] = PCH_IRQ11; + + itss_irq_init(pch_interrupt_routing); + + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + uint8_t int_pin = 0, int_line = 0; + + if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) + continue; + + int_pin = pci_read_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_PIN); + + switch (int_pin) { + case 1: /* INTA# */ + int_line = PCH_IRQ11; + break; + case 2: /* INTB# */ + int_line = PCH_IRQ10; + break; + case 3: /* INTC# */ + int_line = PCH_IRQ11; + break; + case 4: /* INTD# */ + int_line = PCH_IRQ11; + break; + } + + if (!int_line) + continue; + + pci_write_config8(PCI_BDF(irq_dev), PCI_INTERRUPT_LINE, int_line); + } +} + +/* LPC MISC programming */ +void lpc_pch_misc_init(void) +{ + uint8_t reg8; + + /* Setup NMI on errors, disable SERR */ + reg8 = (inb(0x61)) & 0xf0; + outb((reg8 | (1 << 2)), 0x61); + + /* Disable NMI sources */ + outb((1 << 7), 0x70); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Gerrit-Change-Number: 45787 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 28

Change in coreboot[master]: xeon_sp: De-duplicate .h files
by Marc Jones (Code Review) 03 Oct '20

03 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45221 ) Change subject: xeon_sp: De-duplicate .h files ...................................................................... xeon_sp: De-duplicate .h files Move duplicate .h files to top level xeon_sp/include/soc from silicon specific cpx/include/soc and skx/include/soc. Change-Id: I11d8a95a4b2f9451615b236798b3bd030c724858 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- R src/soc/intel/xeon_sp/include/soc/acpi.h R src/soc/intel/xeon_sp/include/soc/irq.h R src/soc/intel/xeon_sp/include/soc/msr.h R src/soc/intel/xeon_sp/include/soc/nvs.h D src/soc/intel/xeon_sp/skx/include/soc/acpi.h D src/soc/intel/xeon_sp/skx/include/soc/irq.h D src/soc/intel/xeon_sp/skx/include/soc/msr.h D src/soc/intel/xeon_sp/skx/include/soc/nvs.h 8 files changed, 0 insertions(+), 154 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/45221/1 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h similarity index 100% rename from src/soc/intel/xeon_sp/cpx/include/soc/acpi.h rename to src/soc/intel/xeon_sp/include/soc/acpi.h diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/irq.h b/src/soc/intel/xeon_sp/include/soc/irq.h similarity index 100% rename from src/soc/intel/xeon_sp/cpx/include/soc/irq.h rename to src/soc/intel/xeon_sp/include/soc/irq.h diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/msr.h b/src/soc/intel/xeon_sp/include/soc/msr.h similarity index 100% rename from src/soc/intel/xeon_sp/cpx/include/soc/msr.h rename to src/soc/intel/xeon_sp/include/soc/msr.h diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h b/src/soc/intel/xeon_sp/include/soc/nvs.h similarity index 100% rename from src/soc/intel/xeon_sp/cpx/include/soc/nvs.h rename to src/soc/intel/xeon_sp/include/soc/nvs.h diff --git a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h deleted file mode 100644 index 354ffb4..0000000 --- a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - - -#ifndef _SOC_ACPI_H_ -#define _SOC_ACPI_H_ - -#include <acpi/acpi.h> -#include <soc/nvs.h> - -#define MEM_BLK_COUNT 0x140 -typedef struct { - uint8_t buf[32]; -} MEM_BLK; - -unsigned long northbridge_write_acpi_tables(const struct device *device, - unsigned long current, struct acpi_rsdp *rsdp); - -void motherboard_fill_fadt(acpi_fadt_t *fadt); - -#endif /* _SOC_ACPI_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/irq.h b/src/soc/intel/xeon_sp/skx/include/soc/irq.h deleted file mode 100644 index 2517fb8..0000000 --- a/src/soc/intel/xeon_sp/skx/include/soc/irq.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _SOC_IRQ_H_ -#define _SOC_IRQ_H_ - -#define PCH_IRQ10 10 -#define PCH_IRQ11 11 - -#endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/msr.h b/src/soc/intel/xeon_sp/skx/include/soc/msr.h deleted file mode 100644 index dd05adc..0000000 --- a/src/soc/intel/xeon_sp/skx/include/soc/msr.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef _SOC_MSR_H_ -#define _SOC_MSR_H_ - -#include <intelblocks/msr.h> - -#define IA32_MCG_CAP 0x179 -#define IA32_MCG_CAP_COUNT_MASK 0xff -#define IA32_MCG_CAP_CTL_P_BIT 8 -#define IA32_MCG_CAP_CTL_P_MASK (1 << IA32_MCG_CAP_CTL_P_BIT) - -#define IA32_MCG_CTL 0x17b - -/* IA32_MISC_ENABLE bits */ -#define FAST_STRINGS_ENABLE_BIT (1 << 0) -#define SPEED_STEP_ENABLE_BIT (1 << 16) -#define MONIOR_ENABLE_BIT (1 << 18) - -#define MSR_IA32_ENERGY_PERF_BIAS 0x1b0 - -/* MSR_PKG_CST_CONFIG_CONTROL bits */ -#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 -#define PKG_CSTATE_LIMIT_SHIFT 0 /* 0:3 */ -/* No package C-state limit. All C-States supported by the processor are available. */ -#define PKG_CSTATE_LIMIT_MASK (0xf << PKG_CSTATE_LIMIT_SHIFT) -#define PKG_CSTATE_NO_LIMIT (0x7 << PKG_CSTATE_LIMIT_SHIFT) -#define IO_MWAIT_REDIRECTION_SHIFT 10 -#define IO_MWAIT_REDIRECTION_ENABLE (1 << IO_MWAIT_REDIRECTION_SHIFT) -#define CFG_LOCK_SHIFT 15 -#define CFG_LOCK_ENABLE (1 << CFG_LOCK_SHIFT) - -/* MSR_PMG_IO_CAPTURE_BASE bits */ -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 -#define LVL_2_BASE_ADDRESS_SHIFT 0 /* 15:0 bits */ -#define LVL_2_BASE_ADDRESS (0x0514 << LVL_2_BASE_ADDRESS_SHIFT) -#define CST_RANGE_SHIFT 16 /* 18:16 bits */ -#define CST_RANGE_MAX_C6 (0x1 << CST_RANGE_SHIFT) - -/* MSR_POWER_CTL bits */ -#define MSR_POWER_CTL 0x1fc -#define BIDIR_PROCHOT_ENABLE_SHIFT 0 -#define BIDIR_PROCHOT_ENABLE (1 << BIDIR_PROCHOT_ENABLE_SHIFT) -#define FAST_BRK_SNP_ENABLE_SHIFT 3 -#define FAST_BRK_SNP_ENABLE (1 << FAST_BRK_SNP_ENABLE_SHIFT) -#define FAST_BRK_INT_ENABLE_SHIFT 4 -#define FAST_BRK_INT_ENABLE (1 << FAST_BRK_INT_ENABLE_SHIFT) -#define PHOLD_CST_PREVENTION_INIT_SHIFT 6 -#define PHOLD_CST_PREVENTION_INIT_VALUE (1 << PHOLD_CST_PREVENTION_INIT_SHIFT) -#define ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT 18 -#define ENERGY_PERF_BIAS_ACCESS_ENABLE (1 << ENERGY_PERF_BIAS_ACCESS_ENABLE_SHIFT) -#define PROCHOT_OUTPUT_DISABLE_SHIFT 21 -#define PROCHOT_OUTPUT_DISABLE (1 << PROCHOT_OUTPUT_DISABLE_SHIFT) -#define PWR_PERF_TUNING_DYN_SWITCHING_SHIFT 24 -#define PWR_PERF_TUNING_DYN_SWITCHING_ENABLE (1 << PWR_PERF_TUNING_DYN_SWITCHING_SHIFT) -#define PROCHOT_LOCK_SHIFT 27 -#define PROCHOT_LOCK_ENABLE (1 << PROCHOT_LOCK_SHIFT) -#define LTR_IIO_DISABLE_SHIFT 29 -#define LTR_IIO_DISABLE (1 << LTR_IIO_DISABLE_SHIFT) - -/* MSR_IA32_PERF_CTRL (0x199) bits */ -#define MSR_IA32_PERF_CTRL 0x199 -#define PSTATE_REQ_SHIFT 8 /* 8:14 bits */ -#define PSTATE_REQ_MASK (0x7f << PSTATE_REQ_SHIFT) -#define PSTATE_REQ_RATIO (0xa << PSTATE_REQ_SHIFT) - -/* MSR_MISC_PWR_MGMT bits */ -#define MSR_MISC_PWR_MGMT 0x1aa -#define HWP_ENUM_SHIFT 6 -#define HWP_ENUM_ENABLE (1 << HWP_ENUM_SHIFT) -#define HWP_EPP_SHIFT 12 -#define HWP_EPP_ENUM_ENABLE (1 << HWP_EPP_SHIFT) -#define LOCK_MISC_PWR_MGMT_MSR_SHIFT 13 -#define LOCK_MISC_PWR_MGMT_MSR (1 << LOCK_MISC_PWR_MGMT_MSR_SHIFT) -#define LOCK_THERM_INT_SHIFT 22 -#define LOCK_THERM_INT (1 << LOCK_THERM_INT_SHIFT) - -/* MSR_TURBO_RATIO_LIMIT bits */ -#define MSR_TURBO_RATIO_LIMIT 0x1ad - -/* MSR_TURBO_RATIO_LIMIT_CORES (0x1ae) */ -#define MSR_TURBO_RATIO_LIMIT_CORES 0x1ae - -/* MSR_VR_CURRENT_CONFIG bits */ -#define MSR_VR_CURRENT_CONFIG 0x601 -#define CURRENT_LIMIT_LOCK_SHIFT 31 -#define CURRENT_LIMIT_LOCK (0x1 << CURRENT_LIMIT_LOCK_SHIFT) - -/* MSR_TURBO_ACTIVATION_RATIO bits */ -#define MSR_TURBO_ACTIVATION_RATIO 0x64c -#define MAX_NON_TURBO_RATIO_SHIFT 0 -#define MAX_NON_TURBO_RATIO (0xff << MAX_NON_TURBO_RATIO_SHIFT) - -/* MSR_ENERGY_PERF_BIAS_CONFIG bits */ -#define MSR_ENERGY_PERF_BIAS_CONFIG 0xa01 -#define EPB_ENERGY_POLICY_SHIFT 3 -#define EPB_ENERGY_POLICY_MASK (0xf << EPB_ENERGY_POLICY_SHIFT) - -/* MSR Protected Processor Inventory Number */ -#define MSR_PPIN_CTL 0x04e -#define MSR_PPIN_CTL_LOCK 0x1 -#define MSR_PPIN_CTL_ENABLE_SHIFT 1 -#define MSR_PPIN_CTL_ENABLE (0x1 << MSR_PPIN_CTL_ENABLE_SHIFT) -#define MSR_PPIN 0x04f -#define MSR_PPIN_CAP_SHIFT 23 -#define MSR_PPIN_CAP (0x1 << MSR_PPIN_CAP_SHIFT) - -#endif /* _SOC_MSR_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/include/soc/nvs.h b/src/soc/intel/xeon_sp/skx/include/soc/nvs.h deleted file mode 100644 index becdd76..0000000 --- a/src/soc/intel/xeon_sp/skx/include/soc/nvs.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SOC_NVS_H_ -#define _SOC_NVS_H_ - -#include <stdint.h> - -/* TODO - this requires xeon sp, server board support */ -/* NOTE: We do not use intelblocks/nvs.h since it includes - mostly client specific attributes */ -struct __packed global_nvs { - uint8_t pcnt; /* 0x00 - Processor Count */ - uint32_t cbmc; /* 0x01 - coreboot memconsole */ - uint8_t rsvd3[251]; -}; - -#endif /* _SOC_NVS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11d8a95a4b2f9451615b236798b3bd030c724858 Gerrit-Change-Number: 45221 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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