coreboot-gerrit October 2020

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Change in coreboot[master]: src/arch/x86/acpi: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Oct '20

04 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45988 ) Change subject: src/arch/x86/acpi: Convert to ASL 2.0 syntax ...................................................................... src/arch/x86/acpi: Convert to ASL 2.0 syntax Change-Id: I36eb4174fe7e47c01b16cd502fd9a2cf5ea48df7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/acpi/debug.asl M src/arch/x86/acpi/globutil.asl 2 files changed, 70 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/45988/1 diff --git a/src/arch/x86/acpi/debug.asl b/src/arch/x86/acpi/debug.asl index fd071f8..74c5843 100644 --- a/src/arch/x86/acpi/debug.asl +++ b/src/arch/x86/acpi/debug.asl @@ -36,12 +36,12 @@ */ Method(DINI) { - store(0x83, DLCR) - store(0x01, CDAT) /* 115200 baud (low) */ - store(0x00, CDLM) /* 115200 baud (high) */ - store(0x03, DLCR) /* word=8 stop=1 parity=none */ - store(0x03, CMCR) /* DTR=1 RTS=1 Out2=Off Loop=Off */ - store(0x00, CDLM) /* turn off interrupts */ + DLCR = 0x83 + CDAT = 0x01 /* 115200 baud (low) */ + CDLM = 0x00 /* 115200 baud (high) */ + DLCR = 0x03 /* word=8 stop=1 parity=none */ + CMCR = 0x03 /* DTR=1 RTS=1 Out2=Off Loop=Off */ + CDLM = 0x00 /* turn off interrupts */ } /* @@ -50,9 +50,9 @@ */ Method(THRE) { - and(CLSR, 0x20, local0) - while (Lequal(local0, Zero)) { - and(CLSR, 0x20, local0) + local0 = CLSR & 0x20 + while (local0 == 0) { + local0 = CLSR & 0x20 } } @@ -63,7 +63,7 @@ Method(OUTX, 1) { THRE() - store(Arg0, CDAT) + CDAT = Arg0 } /* @@ -72,7 +72,7 @@ */ Method(OUTC, 1) { - if (LEqual(Arg0, 0x0a)) { + if (Arg0 == 0x0a) { OUTX(0x0d) } OUTX(Arg0) @@ -84,11 +84,11 @@ */ Method(DBGN, 1) { - and(Arg0, 0x0f, Local0) - if (LLess(Local0, 10)) { - add(Local0, 0x30, Local0) + Local0 = Arg0 & 0x0f + if (Local0 < 10) { + Local0 += 0x30 } else { - add(Local0, 0x37, Local0) + Local0 += 0x37 } OUTC(Local0) } @@ -99,7 +99,7 @@ */ Method(DBGB, 1) { - ShiftRight(Arg0, 4, Local0) + Local0 = Arg0 >> 4 DBGN(Local0) DBGN(Arg0) } @@ -110,7 +110,7 @@ */ Method(DBGW, 1) { - ShiftRight(Arg0, 8, Local0) + Local0 = Arg0 >> 8 DBGB(Local0) DBGB(Arg0) } @@ -121,7 +121,7 @@ */ Method(DBGD, 1) { - ShiftRight(Arg0, 16, Local0) + Local0 = Arg0 >> 16 DBGW(Local0) DBGW(Arg0) } @@ -133,11 +133,11 @@ Method(DBGO, 1) { /* DINI() */ - if (LEqual(ObjectType(Arg0), 1)) { - if (LGreater(Arg0, 0xffff)) { + if (ObjectType(Arg0) == 1) { + if (Arg0 > 0xffff) { DBGD(Arg0) } else { - if (LGreater(Arg0, 0xff)) { + if (Arg0 > 0xff) { DBGW(Arg0) } else { DBGB(Arg0) @@ -145,15 +145,15 @@ } } else { Name(BDBG, Buffer(80) {}) - store(Arg0, BDBG) - store(0, Local1) - while (One) { - store(GETC(BDBG, Local1), Local0) - if (LEqual(Local0, 0)) { + BDBG = Arg0 + Local1 = 0 + while (1) { + Local0 = GETC(BDBG, Local1) + if (Local0 == 0) { return (0) } OUTC(Local0) - Increment(Local1) + Local1++ } } return (0) diff --git a/src/arch/x86/acpi/globutil.asl b/src/arch/x86/acpi/globutil.asl index 2600d0b..6fad02d 100644 --- a/src/arch/x86/acpi/globutil.asl +++ b/src/arch/x86/acpi/globutil.asl @@ -9,56 +9,56 @@ /* string compare functions */ Method(MIN, 2) { - if (LLess(Arg0, Arg1)) { - Return(Arg0) + if (Arg0 < Arg1) { + Return (Arg0) } else { - Return(Arg1) + Return (Arg1) } } Method(SLEN, 1) { - Store(Arg0, Local0) - Return(Sizeof(Local0)) + Local0 = Arg0 + Return (Sizeof(Local0)) } Method(S2BF, 1, Serialized) { - Add(SLEN(Arg0), One, Local0) + Local0 = SLEN(Arg0) + 1 Name(BUFF, Buffer(Local0) {}) - Store(Arg0, BUFF) - Return(BUFF) + BUFF = Arg0 + Return (BUFF) } /* Strong string compare. Checks both length and content */ Method(SCMP, 2) { - Store(S2BF(Arg0), Local0) - Store(S2BF(Arg1), Local1) - Store(Zero, Local4) - Store(SLEN(Arg0), Local5) - Store(SLEN(Arg1), Local6) - Store(MIN(Local5, Local6), Local7) + Local0 = S2BF(Arg0) + Local1 = S2BF(Arg1) + Local4 = 0 + Local5 = SLEN(Arg0) + Local6 = SLEN(Arg1) + Local7 = MIN(Local5, Local6) - While(LLess(Local4, Local7)) { - Store(Derefof(Index(Local0, Local4)), Local2) - Store(Derefof(Index(Local1, Local4)), Local3) - if (LGreater(Local2, Local3)) { - Return(One) + While(Local4 < Local7) { + Local2 = Derefof (Local0 [Local4]) + Local3 = Derefof (Local1 [Local4]) + if (Local2 > Local3) { + Return (1) } else { - if (LLess(Local2, Local3)) { - Return(Ones) + if (Local2 < Local3) { + Return (Ones) } } - Increment(Local4) + Local4++ } - if (LLess(Local4, Local5)) { - Return(One) + if (Local4 < Local5) { + Return (1) } else { - if (LLess(Local4, Local6)) { - Return(Ones) + if (Local4 < Local6) { + Return (Ones) } else { - Return(Zero) + Return (0) } } } @@ -69,22 +69,21 @@ */ Method(WCMP, 2) { - Store(S2BF(Arg0), Local0) - Store(S2BF(Arg1), Local1) - if (LLess(SLEN(Arg0), SLEN(Arg1))) { - Return(0) + Local0 = S2BF(Arg0) + Local1 = S2BF(Arg1) + if (SLEN(Arg0) < SLEN(Arg1)) { + Return (0) } - Store(Zero, Local2) - Store(SLEN(Arg1), Local3) + Local2 = 0 + Local3 = SLEN(Arg1) - While(LLess(Local2, Local3)) { - if (LNotEqual(Derefof(Index(Local0, Local2)), - Derefof(Index(Local1, Local2)))) { - Return(0) + While (Local2 < Local3) { + if (Derefof (Local0 [Local2]) != Derefof (Local1 [Local2])) { + Return (0) } - Increment(Local2) + Local2++ } - Return(One) + Return (1) } /* ARG0 = IRQ Number(0-15) @@ -92,10 +91,10 @@ */ Method(I2BM, 1) { - Store(0, Local0) - if (LNotEqual(ARG0, 0)) { - Store(1, Local1) - ShiftLeft(Local1, ARG0, Local0) + Local0 = 0 + if (ARG0 != 0) { + Local1 = 1 + Local0 = Local1 << ARG0 } - Return(Local0) + Return (Local0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/45988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36eb4174fe7e47c01b16cd502fd9a2cf5ea48df7 Gerrit-Change-Number: 45988 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block: Add emmc dll tuning
by Bora Guvendik (Code Review) 04 Oct '20

04 Oct '20

Hello build bot (Jenkins), Selma Bensaid, Bora Guvendik, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44497 to look at the new patch set (#11). Change subject: soc/intel/common/block: Add emmc dll tuning ...................................................................... soc/intel/common/block: Add emmc dll tuning For 3 different operations (CMD, Tx Data, Rx Data) use mmc driver in coreboot to switch speed modes (DS, HS, DDR, HS200, HS400). 1) For each speed mode / operation combination, start writing delay values (each step 125pSec delay) from 0 to max for the corresponding register field. As an example, register "Tx Delay Control 1" 0x824h, bit field [8:14] is for HS400 speed and write operation (Tx Data). Max is 78 for this field. 2) After writing a delay value to the register field, try to send a CMD13 "send status" for CMD operation. For write (Tx Data), send CMD24 "Write Block". For read (Rx Data), send CMD17 "Read Single Block". 3) Mark that delay value as FAIL if there are crc errors, timeouts, bits set in Error Interrupt Status register or read/write failures. PASS if there are no errors. 4) Choose the middle of largest passing window and program register field with this optimal delay value. BUG=b:140124451 TEST=Ran tuning on Waddledee and booted to OS via emmc. Change-Id: I7c8f8c4da9d887db0f96e23d58847784c824b879 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/mmc.h M src/soc/intel/common/block/scs/Kconfig M src/soc/intel/common/block/scs/dll_tuning.c 3 files changed, 383 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/44497/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/44497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c8f8c4da9d887db0f96e23d58847784c824b879 Gerrit-Change-Number: 44497 Gerrit-PatchSet: 11 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP]soc/intel/common/block: Add EMMC dll caching infrastructure
by Bora Guvendik (Code Review) 04 Oct '20

04 Oct '20

Bora Guvendik has uploaded a new patch set (#10) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/38256 ) Change subject: [WIP]soc/intel/common/block: Add EMMC dll caching infrastructure ...................................................................... [WIP]soc/intel/common/block: Add EMMC dll caching infrastructure Provide support needed to save EMMC dll tuned data to SPI and registers boot after flash and in subsequent boots, read emmc data from SPI flash and copy to the registers. In case tuning fails, setting a flag in header to skip tuning next boot and use FSP default values. TEST: Tested if data is written to SPI EMMC_CACHE and if the readback data is valid. Also verified if the flag is setting right when tuning fails. Change-Id: I0ca1452cbdcbadd3fca644dcc2dfb7b721e02fb7 Signed-off-by: Thejaswani Putta <thejaswani.putta(a)intel.com> --- M src/mainboard/google/drallion/chromeos.fmd M src/soc/intel/common/block/scs/Kconfig M src/soc/intel/common/block/scs/Makefile.inc A src/soc/intel/common/block/scs/emmc_cache.c 4 files changed, 475 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/38256/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/38256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca1452cbdcbadd3fca644dcc2dfb7b721e02fb7 Gerrit-Change-Number: 38256 Gerrit-PatchSet: 10 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block: Add emmc dll tuning
by Bora Guvendik (Code Review) 04 Oct '20

04 Oct '20

Hello build bot (Jenkins), Selma Bensaid, Bora Guvendik, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44497 to look at the new patch set (#10). Change subject: soc/intel/common/block: Add emmc dll tuning ...................................................................... soc/intel/common/block: Add emmc dll tuning For 3 different operations (CMD, Tx Data, Rx Data) use mmc driver in coreboot to switch speed modes (DS, HS, DDR, HS200, HS400). 1) For each speed mode / operation combination, start writing delay values (each step 125pSec delay) from 0 to max for the corresponding register field. As an example, register "Tx Delay Control 1" 0x824h, bit field [8:14] is for HS400 speed and write operation (Tx Data). Max is 78 for this field. 2) After writing a delay value to the register field, try to send a CMD13 (send status) for CMD operation. For write (Tx Data), send CMD24 (Write Block). For read (Rx Data), send CMD17 (Read Single Block). 3) Mark that delay value as FAIL if there are crc errors, timeouts, bits set in Error Interrupt Status register or read/write failures. PASS if there are no errors. 4) Choose the middle of largest passing window and program register field with this optimal delay value. BUG=b:140124451 TEST=Ran tuning on Waddledee and booted to OS via emmc. Change-Id: I7c8f8c4da9d887db0f96e23d58847784c824b879 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/mmc.h M src/soc/intel/common/block/scs/Kconfig M src/soc/intel/common/block/scs/dll_tuning.c 3 files changed, 383 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/44497/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/44497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c8f8c4da9d887db0f96e23d58847784c824b879 Gerrit-Change-Number: 44497 Gerrit-PatchSet: 10 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP]soc/intel/common/block: Add EMMC dll caching infrastructure
by build bot (Jenkins) (Code Review) 04 Oct '20

04 Oct '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38256 ) Change subject: [WIP]soc/intel/common/block: Add EMMC dll caching infrastructure ...................................................................... Patch Set 9: (11 comments) https://review.coreboot.org/c/coreboot/+/38256/9/src/soc/intel/common/block… File src/soc/intel/common/block/scs/emmc_cache.c: https://review.coreboot.org/c/coreboot/+/38256/9/src/soc/intel/common/block… PS9, Line 45: bool is_tuning_success; please, no space before tabs https://review.coreboot.org/c/coreboot/+/38256/9/src/soc/intel/common/block… PS9, Line 196: stored_emmc_data = (struct mmc_dll_params*) data; "(foo*)" should be "(foo *)" https://review.coreboot.org/c/coreboot/+/38256/9/src/soc/intel/common/block… PS9, Line 276: return (void*)md; "(foo*)" should be "(foo *)" https://review.coreboot.org/c/coreboot/+/38256/9/src/soc/intel/common/block… PS9, Line 300: // stuct emmc_tuned_values emmc_data; 'stuct' may be misspelled - perhaps 'struct'? https://review.coreboot.org/c/coreboot/+/38256/9/src/soc/intel/common/block… PS9, Line 302: void* data_file; "foo* bar" should be "foo *bar" https://review.coreboot.org/c/coreboot/+/38256/9/src/soc/intel/common/block… PS9, Line 351: if ((tuning_succeed == true)|| (tuning_succeed == -1)) { spaces required around that '||' (ctx:VxW) https://review.coreboot.org/c/coreboot/+/38256/9/src/soc/intel/common/block… PS9, Line 352: printk(BIOS_ERR, "EMMC: calling tuning algo \n"); unnecessary whitespace before a quoted newline https://review.coreboot.org/c/coreboot/+/38256/9/src/soc/intel/common/block… PS9, Line 355: else { else should follow close brace '}' https://review.coreboot.org/c/coreboot/+/38256/9/src/soc/intel/common/block… PS9, Line 370: if (region_file_update_data(&cache_file, data_file,size) < 0) space required after that ',' (ctx:VxV) https://review.coreboot.org/c/coreboot/+/38256/9/src/soc/intel/common/block… PS9, Line 376: else { else should follow close brace '}' https://review.coreboot.org/c/coreboot/+/38256/9/src/soc/intel/common/block… PS9, Line 384: } void function return statements are not generally useful -- To view, visit https://review.coreboot.org/c/coreboot/+/38256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca1452cbdcbadd3fca644dcc2dfb7b721e02fb7 Gerrit-Change-Number: 38256 Gerrit-PatchSet: 9 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Oct 2020 01:39:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]soc/intel/common/block: Add EMMC dll caching infrastructure
by Bora Guvendik (Code Review) 04 Oct '20

04 Oct '20

Bora Guvendik has uploaded a new patch set (#9) to the change originally created by Thejaswani Putta. ( https://review.coreboot.org/c/coreboot/+/38256 ) Change subject: [WIP]soc/intel/common/block: Add EMMC dll caching infrastructure ...................................................................... [WIP]soc/intel/common/block: Add EMMC dll caching infrastructure Provide support needed to save EMMC dll tuned data to SPI and registers boot after flash and in subsequent boots, read emmc data from SPI flash and copy to the registers. Incase tuning fails, setting a flag in header to skip tuning next boot and use FSP default values. TEST: Tested if data is written to SPI EMMC_CACHE and if the readback data is valid. Also verified if the flag is setting right when tuning fails. Change-Id: I0ca1452cbdcbadd3fca644dcc2dfb7b721e02fb7 Signed-off-by: Thejaswani Putta <thejaswani.putta(a)intel.com> --- M src/mainboard/google/drallion/chromeos.fmd M src/soc/intel/common/block/scs/Kconfig M src/soc/intel/common/block/scs/Makefile.inc A src/soc/intel/common/block/scs/emmc_cache.c 4 files changed, 504 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/38256/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/38256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca1452cbdcbadd3fca644dcc2dfb7b721e02fb7 Gerrit-Change-Number: 38256 Gerrit-PatchSet: 9 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block: Add emmc dll tuning
by Bora Guvendik (Code Review) 04 Oct '20

04 Oct '20

Hello build bot (Jenkins), Selma Bensaid, Bora Guvendik, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44497 to look at the new patch set (#9). Change subject: soc/intel/common/block: Add emmc dll tuning ...................................................................... soc/intel/common/block: Add emmc dll tuning For 3 different operations (CMD, Tx Data, Rx Data) use mmc driver in coreboot to switch speed modes (DS, HS, DDR, HS200, HS400). 1) For each speed mode / operation combination, start writing delay values (each step 125pSec delay) from 0 to max for the corresponding register field. As an example, register "Tx Delay Control 1" 0x824h, bit field [8:14] is for HS400 speed and write operation (Tx Data). Max is 78 for this field. 2) After writing a delay value to the register field, try to send a CMD13 "send status" for CMD operation. For write (Tx Data), send CMD24 "Write Block". For read (Rx Data), send CMD17 "Read Single Block". 3) Mark that delay value as FAIL if there are crc errors, timeouts, bits set in Error Interrupt Status register or read/write failures. PASS if there are no errors. 4) Choose the middle of largest passing window and program register field with this optimal delay value. BUG=b:140124451 TEST=Ran tuning on Waddledee and booted to OS via emmc. Change-Id: I7c8f8c4da9d887db0f96e23d58847784c824b879 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/mmc.h M src/soc/intel/common/block/scs/Kconfig M src/soc/intel/common/block/scs/dll_tuning.c 3 files changed, 383 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/44497/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/44497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c8f8c4da9d887db0f96e23d58847784c824b879 Gerrit-Change-Number: 44497 Gerrit-PatchSet: 9 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP]soc/intel/common/block: Add EMMC dll caching infrastructure
by build bot (Jenkins) (Code Review) 04 Oct '20

04 Oct '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38256 ) Change subject: [WIP]soc/intel/common/block: Add EMMC dll caching infrastructure ...................................................................... Patch Set 8: (11 comments) https://review.coreboot.org/c/coreboot/+/38256/8/src/soc/intel/common/block… File src/soc/intel/common/block/scs/emmc_cache.c: https://review.coreboot.org/c/coreboot/+/38256/8/src/soc/intel/common/block… PS8, Line 45: bool is_tuning_success; please, no space before tabs https://review.coreboot.org/c/coreboot/+/38256/8/src/soc/intel/common/block… PS8, Line 196: stored_emmc_data = (struct mmc_dll_params*) data; "(foo*)" should be "(foo *)" https://review.coreboot.org/c/coreboot/+/38256/8/src/soc/intel/common/block… PS8, Line 276: return (void*)md; "(foo*)" should be "(foo *)" https://review.coreboot.org/c/coreboot/+/38256/8/src/soc/intel/common/block… PS8, Line 300: // stuct emmc_tuned_values emmc_data; 'stuct' may be misspelled - perhaps 'struct'? https://review.coreboot.org/c/coreboot/+/38256/8/src/soc/intel/common/block… PS8, Line 302: void* data_file; "foo* bar" should be "foo *bar" https://review.coreboot.org/c/coreboot/+/38256/8/src/soc/intel/common/block… PS8, Line 351: if ((tuning_succeed == true)|| (tuning_succeed == -1)) { spaces required around that '||' (ctx:VxW) https://review.coreboot.org/c/coreboot/+/38256/8/src/soc/intel/common/block… PS8, Line 352: printk(BIOS_ERR, "EMMC: calling tuning algo \n"); unnecessary whitespace before a quoted newline https://review.coreboot.org/c/coreboot/+/38256/8/src/soc/intel/common/block… PS8, Line 355: else { else should follow close brace '}' https://review.coreboot.org/c/coreboot/+/38256/8/src/soc/intel/common/block… PS8, Line 370: if (region_file_update_data(&cache_file, data_file,size) < 0) space required after that ',' (ctx:VxV) https://review.coreboot.org/c/coreboot/+/38256/8/src/soc/intel/common/block… PS8, Line 376: else { else should follow close brace '}' https://review.coreboot.org/c/coreboot/+/38256/8/src/soc/intel/common/block… PS8, Line 384: } void function return statements are not generally useful -- To view, visit https://review.coreboot.org/c/coreboot/+/38256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ca1452cbdcbadd3fca644dcc2dfb7b721e02fb7 Gerrit-Change-Number: 38256 Gerrit-PatchSet: 8 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 04 Oct 2020 01:19:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block: Add emmc dll tuning
by Bora Guvendik (Code Review) 04 Oct '20

04 Oct '20

Hello build bot (Jenkins), Selma Bensaid, Bora Guvendik, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44497 to look at the new patch set (#8). Change subject: soc/intel/common/block: Add emmc dll tuning ...................................................................... soc/intel/common/block: Add emmc dll tuning For 3 different operations (CMD, Tx Data, Rx Data) use mmc driver in coreboot to switch speed modes (DS, HS, DDR, HS200, HS400). 1) For each speed mode / operation combination, start writing delay values (each step 125pSec delay) from 0 to max for the corresponding register field. As an example, register "Tx Delay Control 1" 0x824h, bit field [8:14] is for HS400 speed and write operation (Tx Data). Max is 78 for this field. 2) After writing a delay value to the register field, try to send a CMD13 “send status” for CMD operation. For write (Tx Data), send CMD24 "Write Block”. For read (Rx Data), send CMD17 "Read Single Block". 3) Mark that delay value as FAIL if there are crc errors, timeouts, bits set in Error Interrupt Status register or read/write failures. PASS if there are no errors. 4) Choose the middle of largest passing window and program register field with this optimal delay value. BUG=b:140124451 TEST=Ran tuning on Waddledee and booted to OS via emmc. Change-Id: I7c8f8c4da9d887db0f96e23d58847784c824b879 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/mmc.h M src/soc/intel/common/block/scs/Kconfig M src/soc/intel/common/block/scs/dll_tuning.c 3 files changed, 383 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/44497/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/44497 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c8f8c4da9d887db0f96e23d58847784c824b879 Gerrit-Change-Number: 44497 Gerrit-PatchSet: 8 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: commonlib/storage/mmc: Add DS and DDR50 speed modes
by Bora Guvendik (Code Review) 04 Oct '20

04 Oct '20

Hello build bot (Jenkins), Selma Bensaid, Bora Guvendik, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44493 to look at the new patch set (#2). Change subject: commonlib/storage/mmc: Add DS and DDR50 speed modes ...................................................................... commonlib/storage/mmc: Add DS and DDR50 speed modes Add two new functions to switch speed to "High Speed DDR" and "Backwards Compatibility with legacy MMC card" mentioned in section 5.3.2 of JESD84_B51 spec. BUG=b:140124451 TEST=Change mmc speed to DDR50 and DS Change-Id: Ic75a3815a47e99e054d2cea2e82757740caffd1a Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/commonlib/storage/mmc.c 1 file changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/44493/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic75a3815a47e99e054d2cea2e82757740caffd1a Gerrit-Change-Number: 44493 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit October 2020