coreboot-gerrit October 2020

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Change in coreboot[master]: xeon_sp/skx: prepare acpi.* for merging
by Marc Jones (Code Review) 03 Oct '20

03 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45218 ) Change subject: xeon_sp/skx: prepare acpi.* for merging ...................................................................... xeon_sp/skx: prepare acpi.* for merging Cleanup acpi.h in preparation for merging with cpx/ acpi.* files Change-Id: I2a0dc964eeb7f8da53676eb94c4385ff8668f6af Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/skx/acpi.c M src/soc/intel/xeon_sp/skx/include/soc/acpi.h 2 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/45218/1 diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index d984d9f..4797d90 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -82,7 +82,7 @@ return current; } -unsigned long acpi_madt_irq_overrides(unsigned long current) +static unsigned long acpi_madt_irq_overrides(unsigned long current) { int sci = acpi_sci_irq(); uint16_t flags = MP_IRQ_TRIGGER_LEVEL; @@ -747,7 +747,7 @@ return current; } -void uncore_inject_dsdt(void) +static void uncore_inject_dsdt(void) { size_t hob_size; const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; diff --git a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h index 0e00c2b..354ffb4 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h @@ -12,10 +12,9 @@ uint8_t buf[32]; } MEM_BLK; -void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -unsigned long acpi_madt_irq_overrides(unsigned long current); unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void uncore_inject_dsdt(void); + +void motherboard_fill_fadt(acpi_fadt_t *fadt); #endif /* _SOC_ACPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a0dc964eeb7f8da53676eb94c4385ff8668f6af Gerrit-Change-Number: 45218 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: xeon_sp: Move common acpi code to xeon_sp/
by Marc Jones (Code Review) 03 Oct '20

03 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45217 ) Change subject: xeon_sp: Move common acpi code to xeon_sp/ ...................................................................... xeon_sp: Move common acpi code to xeon_sp/ Use the common xeon_sp/cpx/acpi asl for skx/. There were only minor whitespace differences between the directories. Update the mainboards to build the moved files. Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/mainboard/ocp/deltalake/dsdt.asl M src/mainboard/ocp/tiogapass/dsdt.asl R src/soc/intel/xeon_sp/acpi/globalnvs.asl R src/soc/intel/xeon_sp/acpi/iiostack.asl R src/soc/intel/xeon_sp/acpi/pci_irq.asl R src/soc/intel/xeon_sp/acpi/southcluster.asl R src/soc/intel/xeon_sp/acpi/uncore.asl R src/soc/intel/xeon_sp/acpi/uncore_irq.asl D src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl D src/soc/intel/xeon_sp/skx/acpi/iiostack.asl D src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl D src/soc/intel/xeon_sp/skx/acpi/uncore.asl D src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl 13 files changed, 4 insertions(+), 828 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/45217/1 diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl index c74b5fe..d2c41a1 100644 --- a/src/mainboard/ocp/deltalake/dsdt.asl +++ b/src/mainboard/ocp/deltalake/dsdt.asl @@ -14,10 +14,10 @@ #include "acpi/platform.asl" // global NVS and variables - #include <soc/intel/xeon_sp/cpx/acpi/globalnvs.asl> + #include <soc/intel/xeon_sp/acpi/globalnvs.asl> #include <cpu/intel/common/acpi/cpu.asl> // CPX-SP ACPI tables - #include <soc/intel/xeon_sp/cpx/acpi/uncore.asl> + #include <soc/intel/xeon_sp/acpi/uncore.asl> } diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index bd31251..769396f 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -15,12 +15,12 @@ #include "acpi/platform.asl" // global NVS and variables - #include <soc/intel/xeon_sp/skx/acpi/globalnvs.asl> + #include <soc/intel/xeon_sp/acpi/globalnvs.asl> #include <cpu/intel/common/acpi/cpu.asl> // Xeon-SP ACPI tables Scope (\_SB) { - #include <soc/intel/xeon_sp/skx/acpi/uncore.asl> + #include <soc/intel/xeon_sp/acpi/uncore.asl> } } diff --git a/src/soc/intel/xeon_sp/cpx/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/xeon_sp/cpx/acpi/globalnvs.asl rename to src/soc/intel/xeon_sp/acpi/globalnvs.asl diff --git a/src/soc/intel/xeon_sp/cpx/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl similarity index 100% rename from src/soc/intel/xeon_sp/cpx/acpi/iiostack.asl rename to src/soc/intel/xeon_sp/acpi/iiostack.asl diff --git a/src/soc/intel/xeon_sp/cpx/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/acpi/pci_irq.asl similarity index 100% rename from src/soc/intel/xeon_sp/cpx/acpi/pci_irq.asl rename to src/soc/intel/xeon_sp/acpi/pci_irq.asl diff --git a/src/soc/intel/xeon_sp/cpx/acpi/southcluster.asl b/src/soc/intel/xeon_sp/acpi/southcluster.asl similarity index 100% rename from src/soc/intel/xeon_sp/cpx/acpi/southcluster.asl rename to src/soc/intel/xeon_sp/acpi/southcluster.asl diff --git a/src/soc/intel/xeon_sp/cpx/acpi/uncore.asl b/src/soc/intel/xeon_sp/acpi/uncore.asl similarity index 100% rename from src/soc/intel/xeon_sp/cpx/acpi/uncore.asl rename to src/soc/intel/xeon_sp/acpi/uncore.asl diff --git a/src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/acpi/uncore_irq.asl similarity index 100% rename from src/soc/intel/xeon_sp/cpx/acpi/uncore_irq.asl rename to src/soc/intel/xeon_sp/acpi/uncore_irq.asl diff --git a/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl b/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl deleted file mode 100644 index 8e4456f..0000000 --- a/src/soc/intel/xeon_sp/skx/acpi/globalnvs.asl +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - - -/* Global Variables */ - -Name(\PICM, 0) // IOAPIC/8259 - -/* - * Global ACPI memory region. This region is used for passing information - * between coreboot (aka "the system bios"), ACPI, and the SMI handler. - * Since we don't know where this will end up in memory at ACPI compile time, - * we have to fix it up in coreboot's ACPI creation phase. - */ - - -External(NVSA) -OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) -Field (GNVS, ByteAcc, NoLock, Preserve) -{ - /* Miscellaneous */ - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PRM0, 8, // 0x03 - SMI function parameter - PRM1, 8, // 0x04 - SMI function parameter - SCIF, 8, // 0x05 - SCI function - PRM2, 8, // 0x06 - SCI function parameter - PRM3, 8, // 0x07 - SCI function parameter - LCKF, 8, // 0x08 - Global Lock function for EC - PRM4, 8, // 0x09 - Lock function parameter - PRM5, 8, // 0x0a - Lock function parameter - P80D, 32, // 0x0b - Debug port (IO 0x80) value - LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) - PCNT, 8, // 0x11 - Processor count - TPMP, 8, // 0x12 - TPM Present and Enabled - TLVL, 8, // 0x13 - Throttle Level - PPCM, 8, // 0x14 - Maximum P-state usable by OS - PM1I, 64, // 0x15 - PM1 wake status bit - GPEI, 64, // 0x1D - GPE wake status bit - U2WE, 16, // 0x25 - USB2 Wake Enable Bitmap - U3WE, 8, // 0x27 - USB3 Wake Enable Bitmap - - - /* Device Config */ - Offset (0x30), - S5U0, 8, // 0x30 - Enable USB0 in S5 - S5U1, 8, // 0x31 - Enable USB1 in S5 - S3U0, 8, // 0x32 - Enable USB0 in S3 - S3U1, 8, // 0x33 - Enable USB1 in S3 - TACT, 8, // 0x34 - Thermal Active trip point - TPSV, 8, // 0x35 - Thermal Passive trip point - TCRT, 8, // 0x36 - Thermal Critical trip point - DPTE, 8, // 0x37 - Enable DPTF - - /* Base addresses */ - Offset (0x50), - CMEM, 32, // 0x50 - CBMEM TOC - TOLM, 32, // 0x54 - Top of Low Memory - CBMC, 32, // 0x58 - coreboot mem console pointer - MMOB, 32, // 0x5C - MMIO Base Low Base - MMOL, 32, // 0x60 - MMIO Base Low Limit - MMHB, 64, // 0x64 - MMIO Base High Base - MMHL, 64, // 0x6C - MMIO Base High Limit - TSGB, 32, // 0x74 - TSEG Base - TSSZ, 32, // 0x78 - TSEG Size -} diff --git a/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl b/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl deleted file mode 100644 index 964be3c..0000000 --- a/src/soc/intel/xeon_sp/skx/acpi/iiostack.asl +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#define MAKE_IIO_DEV(id,rt) \ - Device (PC##id) \ - { \ - Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) \ - Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) \ - Name (_UID, 0x##id) \ - Method (_PRT, 0, NotSerialized) \ - { \ - If (PICM) \ - { \ - Return (\_SB_.AR##rt) \ - } \ - Return (\_SB_.PR##rt) \ - } \ - External(\_SB.RT##id) \ - Method (_CRS, 0, NotSerialized) \ - { \ - Return (\_SB.RT##id) \ - } \ - Name (SUPP, 0x00) \ - Name (CTRL, 0x00) \ - Name (_PXM, 0x00) /* _PXM: Device Proximity */ \ - Method (_OSC, 4, NotSerialized) \ - { \ - CreateDWordField (Arg3, 0x00, CDW1) \ - If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) \ - { \ - CreateDWordField (Arg3, 0x04, CDW2) \ - If ((Arg2 > 0x02)) \ - { \ - CreateDWordField (Arg3, 0x08, CDW3) \ - } \ - SUPP = CDW2 \ - CTRL = CDW3 \ - If ((AHPE || ((SUPP & 0x16) != 0x16))) \ - { \ - CTRL &= 0x1E \ - Sleep (0x03E8) \ - } \ - /* Never allow SHPC (no SHPC controller in system) */ \ - CTRL &= 0x1D \ - /* Disable Native PCIe AER handling from OS */ \ - CTRL &= 0x17 \ - If ((Arg1 != One)) /* unknown revision */ \ - { \ - CDW1 |= 0x08 \ - } \ - If ((CDW3 != CTRL)) /* capabilities bits were masked */ \ - { \ - CDW1 |= 0x10 \ - } \ - CDW3 = CTRL \ - Return (Arg3) \ - } \ - Else \ - { \ - /* indicate unrecognized UUID */ \ - CDW1 |= 0x04 \ - IO80 = 0xEE \ - Return (Arg3) \ - } \ - } \ - } - -MAKE_IIO_DEV(00, 00) -MAKE_IIO_DEV(01, 10) -MAKE_IIO_DEV(02, 20) -MAKE_IIO_DEV(03, 28) - -#if MAX_SOCKET > 1 -MAKE_IIO_DEV(06, 40) -MAKE_IIO_DEV(07, 50) -MAKE_IIO_DEV(08, 60) -MAKE_IIO_DEV(09, 68) -#endif diff --git a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl deleted file mode 100644 index dcb6fe2..0000000 --- a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Refer to Intel® C620 Series Chipset Platform Controller Hub EDS section 20.11 - * CONFIG_PCR_BASE_ADDRESS 0xfd000000 0x3100 - * (0xfd000000 | ((uint8_t)(0xC4) << 16) | (uint16_t)(0x3100) = 0xFDC43100 - * - * PIRQ routing control is in PCR ITSS region. - */ - -OperationRegion (ITSS, SystemMemory, - Add (PCR_ITSS_PIRQA_ROUT, - Add (CONFIG_PCR_BASE_ADDRESS, - ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8) -Field (ITSS, ByteAcc, NoLock, Preserve) -{ - PIRA, 8, /* PIRQA Routing Control */ - PIRB, 8, /* PIRQB Routing Control */ - PIRC, 8, /* PIRQC Routing Control */ - PIRD, 8, /* PIRQD Routing Control */ - PIRE, 8, /* PIRQE Routing Control */ - PIRF, 8, /* PIRQF Routing Control */ - PIRG, 8, /* PIRQG Routing Control */ - PIRH, 8, /* PIRQH Routing Control */ -} - -Name (IREN, 0x80) /* Interrupt Routing Enable */ -Name (IREM, 0x0f) /* Interrupt Routing Mask */ - -Name (PRSA, ResourceTemplate () -{ - IRQ (Level, ActiveLow, Shared, ) - {3,4,5,6,7,10,11,12,14,15} -}) -Alias (PRSA, PRSB) -Name (PRSC, ResourceTemplate () -{ - IRQ (Level, ActiveLow, Shared, ) - {3,4,5,6,10,11,12,14,15} -}) -Alias (PRSC, PRSD) -Alias (PRSA, PRSE) -Alias (PRSA, PRSF) -Alias (PRSA, PRSG) -Alias (PRSA, PRSH) - -#define MAKE_LINK_DEV(id,uid) \ - Device (LNK##id) \ - { \ - Name (_HID, EISAID ("PNP0C0F")) \ - Name (_UID, ##uid) \ - Method (_PRS, 0, NotSerialized) \ - { \ - Return (PRS##id) \ - } \ - Method (_CRS, 0, Serialized) \ - { \ - Name (RTLA, ResourceTemplate () \ - { \ - IRQ (Level, ActiveLow, Shared) {} \ - }) \ - CreateWordField (RTLA, 1, IRQ0) \ - Store (Zero, IRQ0) \ - \ - /* Set the bit from PIRQ Routing Register */ \ - ShiftLeft (1, And (^^PIR##id, ^^IREM), IRQ0) \ - Return (RTLA) \ - } \ - Method (_SRS, 1, Serialized) \ - { \ - CreateWordField (Arg0, 1, IRQ0) \ - FindSetRightBit (IRQ0, Local0) \ - Decrement (Local0) \ - Store (Local0, ^^PIR##id) \ - } \ - Method (_STA, 0, Serialized) \ - { \ - If (And (^^PIR##id, ^^IREN)) { \ - Return (0x9) \ - } Else { \ - Return (0xb) \ - } \ - } \ - Method (_DIS, 0, Serialized) \ - { \ - Or (^^PIR##id, ^^IREN, ^^PIR##id) \ - } \ - } - -MAKE_LINK_DEV(A,1) -MAKE_LINK_DEV(B,2) -MAKE_LINK_DEV(C,3) -MAKE_LINK_DEV(D,4) -MAKE_LINK_DEV(E,5) -MAKE_LINK_DEV(F,6) -MAKE_LINK_DEV(G,7) -MAKE_LINK_DEV(H,8) diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore.asl deleted file mode 100644 index 498a997..0000000 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore.asl +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - - -#include <intelblocks/itss.h> -#include <intelblocks/pcr.h> -#include <soc/iomap.h> -#include <soc/irq.h> -#include <soc/pcr_ids.h> - -Scope(\) -{ - // Private Chipset Register(PCR). Memory Mapped through ILB - OperationRegion(PCRR, SystemMemory, P2SB_BAR, 0x01000000) - Field(PCRR, DWordAcc, Lock, Preserve) - { - Offset (0xD03100), // Interrupt Routing Registers - PRTA, 8, - PRTB, 8, - PRTC, 8, - PRTD, 8, - PRTE, 8, - PRTF, 8, - PRTG, 8, - PRTH, 8, - } -} - -Scope (_SB) -{ - #include "pci_irq.asl" - #include "uncore_irq.asl" - #include "iiostack.asl" -} diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl deleted file mode 100644 index 9926367..0000000 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl +++ /dev/null @@ -1,551 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * Uncore devices PCI interrupt routing packages. - * See ACPI spec 6.2.13 _PRT (PCI routing table) for details. - * The mapping fields ae Address, Pin, Source, Source Index. - */ - -#define GEN_PCIE_LEGACY_IRQ() \ - Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ - Package () { 0x0001FFFF, 0x00, LNKA, 0x00 }, \ - Package () { 0x0002FFFF, 0x00, LNKA, 0x00 }, \ - Package () { 0x0003FFFF, 0x00, LNKA, 0x00 } - -#define GEN_UNCORE_LEGACY_IRQ(dev) \ - Package () { ##dev, 0x00, LNKA, 0x00 }, \ - Package () { ##dev, 0x01, LNKB, 0x00 }, \ - Package () { ##dev, 0x02, LNKC, 0x00 }, \ - Package () { ##dev, 0x03, LNKD, 0x00 } - -#define GEN_PCIE_IOAPIC_IRQ(irq) \ - Package () { 0x0000FFFF, 0x00, 0x00, ##irq }, \ - Package () { 0x0001FFFF, 0x00, 0x00, ##irq }, \ - Package () { 0x0002FFFF, 0x00, 0x00, ##irq }, \ - Package () { 0x0003FFFF, 0x00, 0x00, ##irq } - -#define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \ - Package () { ##dev, 0x00, 0x00, ##irq1 }, \ - Package () { ##dev, 0x01, 0x00, ##irq2 }, \ - Package () { ##dev, 0x02, 0x00, ##irq3 }, \ - Package () { ##dev, 0x03, 0x00, ##irq4 } - -// Socket 0, IIOStack 0 device legacy interrupt routing -Name (PR00, Package (0x28) -{ - // [DMI0]: Legacy PCI Express Port 0 - Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, - // [CB0A]: CBDMA - // [CB0E]: CBDMA - Package () { 0x0004FFFF, 0x00, LNKA, 0x00 }, - // [CB0B]: CBDMA - // [CB0F]: CBDMA - Package () { 0x0004FFFF, 0x01, LNKB, 0x00 }, - // [CB0C]: CBDMA - // [CB0G]: CBDMA - Package () { 0x0004FFFF, 0x02, LNKC, 0x00 }, - // [CB0D]: CBDMA - // [CB0H]: CBDMA - Package () { 0x0004FFFF, 0x03, LNKD, 0x00 }, - // Uncore 0 UBOX Device - Package () { 0x0008FFFF, 0x00, LNKA, 0x00 }, - Package () { 0x0008FFFF, 0x01, LNKB, 0x00 }, - Package () { 0x0008FFFF, 0x02, LNKC, 0x00 }, - Package () { 0x0008FFFF, 0x03, LNKD, 0x00 }, - // [DISP]: Display Controller - Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, - // [IHC1]: HECI #1 - // [IHC3]: HECI #3 - Package () { 0x0010FFFF, 0x00, LNKA, 0x00 }, - // [IHC2]: HECI #2 - Package () { 0x0010FFFF, 0x01, LNKB, 0x00 }, - // [IIDR]: IDE-Redirection (IDE-R) - Package () { 0x0010FFFF, 0x02, LNKC, 0x00 }, - // [IMKT]: Keyboard and Text (KT) Redirection - Package () { 0x0010FFFF, 0x03, LNKD, 0x00 }, - // [SAT2]: sSATA Host controller 2 on PCH - Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, - // // [XHCI]: xHCI controller 1 on PCH - Package () { 0x0014FFFF, 0x00, LNKA, 0x00 }, - // [OTG0]: USB Device Controller (OTG) on PCH - Package () { 0x0014FFFF, 0x01, LNKB, 0x00 }, - // [TERM]: Thermal Subsystem on PCH - Package () { 0x0014FFFF, 0x02, LNKC, 0x00 }, - // [CAMR]: Camera IO Host Controller on PCH - Package () { 0x0014FFFF, 0x03, LNKD, 0x00 }, - // [HEC1]: HECI #1 on PCH - // [HEC3]: HECI #3 on PCH - Package () { 0x0016FFFF, 0x00, LNKA, 0x00 }, - // [HEC2]: HECI #2 on PCH - Package () { 0x0016FFFF, 0x01, LNKB, 0x00 }, - // [IDER]: ME IDE redirect on PCH - Package () { 0x0016FFFF, 0x02, LNKC, 0x00 }, - // [MEKT]: MEKT on PCH - Package () { 0x0016FFFF, 0x03, LNKD, 0x00 }, - // [SAT1]: SATA controller 1 on PCH - Package () { 0x0017FFFF, 0x00, LNKA, 0x00 }, - // [NAN1]: NAND Cycle Router on PCH - Package () { 0x0018FFFF, 0x00, LNKA, 0x00 }, - // [RP17]: PCIE PCH Root Port #17 - Package () { 0x001BFFFF, 0x00, LNKA, 0x00 }, - // [RP18]: PCIE PCH Root Port #18 - Package () { 0x001BFFFF, 0x01, LNKB, 0x00 }, - // [RP19]: PCIE PCH Root Port #19 - Package () { 0x001BFFFF, 0x02, LNKC, 0x00 }, - // [RP20]: PCIE PCH Root Port #20 - Package () { 0x001BFFFF, 0x03, LNKD, 0x00 }, - // [RP01]: PCIE PCH Root Port #1 - // [RP05]: PCIE PCH Root Port #5 - Package () { 0x001CFFFF, 0x00, LNKA, 0x00 }, - // [RP02]: PCIE PCH Root Port #2 - // [RP06]: PCIE PCH Root Port #6 - Package () { 0x001CFFFF, 0x01, LNKB, 0x00 }, - // [RP03]: PCIE PCH Root Port #3 - // [RP07]: PCIE PCH Root Port #7 - Package () { 0x001CFFFF, 0x02, LNKC, 0x00 }, - // [RP04]: PCIE PCH Root Port #4 - // [RP08]: PCIE PCH Root Port #8 - Package () { 0x001CFFFF, 0x03, LNKD, 0x00 }, - // [RP09]: PCIE PCH Root Port #9 - // [RP13]: PCIE PCH Root Port #13 - Package () { 0x001DFFFF, 0x00, LNKA, 0x00 }, - // [RP10]: PCIE PCH Root Port #10 - // [RP14]: PCIE PCH Root Port #14 - Package () { 0x001DFFFF, 0x01, LNKB, 0x00 }, - // [RP11]: PCIE PCH Root Port #11 - // [RP15]: PCIE PCH Root Port #15 - Package () { 0x001DFFFF, 0x02, LNKC, 0x00 }, - // [RP12]: PCIE PCH Root Port #12 - // [RP16]: PCIE PCH Root Port #16 - Package () { 0x001DFFFF, 0x03, LNKD, 0x00 }, - // [UAR0]: UART #0 on PCH - Package () { 0x001EFFFF, 0x02, LNKC, 0x00 }, - // [UAR1]: UART #1 on PCH - Package () { 0x001EFFFF, 0x03, LNKD, 0x00 }, - // [CAVS]: HD Audio Subsystem Controller on PCH - // [SMBS]: SMBus controller on PCH - // [GBE1]: GbE Controller on PCH - // [NTPK]: Northpeak Controller on PCH - Package () { 0x001FFFFF, 0x00, LNKA, 0x00 }, -}) - -// Socket 0, IIOStack 0 device IOAPIC interrupt routing -Name (AR00, Package (0x28) -{ - // [DMI0]: Legacy PCI Express Port 0 - Package () { 0x0000FFFF, 0x00, 0x00, 0x1F }, - // [CB0A]: CB3DMA - // [CB0E]: CB3DMA - Package () { 0x0004FFFF, 0x00, 0x00, 0x1A }, - // [CB0B]: CB3DMA - // [CB0F]: CB3DMA - Package () { 0x0004FFFF, 0x01, 0x00, 0x1B }, - // [CB0C]: CB3DMA - // [CB0G]: CB3DMA - Package () { 0x0004FFFF, 0x02, 0x00, 0x1A }, - // [CB0D]: CB3DMA - // [CB0H]: CB3DMA - Package () { 0x0004FFFF, 0x03, 0x00, 0x1B }, - // [UBX0]: Uncore 0 UBOX Device - Package () { 0x0008FFFF, 0x00, 0x00, 0x18 }, - Package () { 0x0008FFFF, 0x01, 0x00, 0x1C }, - Package () { 0x0008FFFF, 0x02, 0x00, 0x1D }, - Package () { 0x0008FFFF, 0x03, 0x00, 0x1E }, - // [DISP]: Display Controller - Package () { 0x000FFFFF, 0x00, 0x00, 0x10 }, - // [IHC1]: HECI #1 - // [IHC3]: HECI #3 - Package () { 0x0010FFFF, 0x00, 0x00, 0x10 }, - // [IHC2]: HECI #2 - Package () { 0x0010FFFF, 0x01, 0x00, 0x11 }, - // [IIDR]: IDE-Redirection (IDE-R) - Package () { 0x0010FFFF, 0x02, 0x00, 0x12 }, - // [IMKT]: Keyboard and Text (KT) Redirection - Package () { 0x0010FFFF, 0x03, 0x00, 0x13 }, - // [SAT2]: sSATA Host controller 2 on PCH - Package () { 0x0011FFFF, 0x00, 0x00, 0x10 }, - // [XHCI]: xHCI controller 1 on PCH - Package () { 0x0014FFFF, 0x00, 0x00, 0x10 }, - // [OTG0]: USB Device Controller (OTG) on PCH - Package () { 0x0014FFFF, 0x01, 0x00, 0x11 }, - // [TERM]: Thermal Subsystem on PCH - Package () { 0x0014FFFF, 0x02, 0x00, 0x12 }, - // [CAMR]: Camera IO Host Controller on PCH - Package () { 0x0014FFFF, 0x03, 0x00, 0x13 }, - // [HEC1]: HECI #1 on PCH - // [HEC3]: HECI #3 on PCH - Package () { 0x0016FFFF, 0x00, 0x00, 0x10 }, - // [HEC2]: HECI #2 on PCH - Package () { 0x0016FFFF, 0x01, 0x00, 0x11 }, - // [IDER]: ME IDE redirect on PCH - Package () { 0x0016FFFF, 0x02, 0x00, 0x12 }, - // [MEKT]: MEKT on PCH - Package () { 0x0016FFFF, 0x03, 0x00, 0x13 }, - // [SAT1]: SATA controller 1 on PCH - Package () { 0x0017FFFF, 0x00, 0x00, 0x10 }, - // [NAN1]: NAND Cycle Router on PCH - Package () { 0x0018FFFF, 0x00, 0x00, 0x10 }, - // [RP17]: PCIE PCH Root Port #17 - Package () { 0x001BFFFF, 0x00, 0x00, 0x10 }, - // [RP18]: PCIE PCH Root Port #18 - Package () { 0x001BFFFF, 0x01, 0x00, 0x11 }, - // [RP19]: PCIE PCH Root Port #19 - Package () { 0x001BFFFF, 0x02, 0x00, 0x12 }, - // [RP20]: PCIE PCH Root Port #20 - Package () { 0x001BFFFF, 0x03, 0x00, 0x13 }, - // [RP01]: PCIE PCH Root Port #1 - // [RP05]: PCIE PCH Root Port #5 - Package () { 0x001CFFFF, 0x00, 0x00, 0x10 }, - // [RP02]: PCIE PCH Root Port #2 - // [RP06]: PCIE PCH Root Port #6 - Package () { 0x001CFFFF, 0x01, 0x00, 0x11 }, - // [RP03]: PCIE PCH Root Port #3 - // [RP07]: PCIE PCH Root Port #7 - Package () { 0x001CFFFF, 0x02, 0x00, 0x12 }, - // [RP04]: PCIE PCH Root Port #4 - // [RP08]: PCIE PCH Root Port #8 - Package () { 0x001CFFFF, 0x03, 0x00, 0x13 }, - // [RP09]: PCIE PCH Root Port #9 - // [RP13]: PCIE PCH Root Port #13 - Package () { 0x001DFFFF, 0x00, 0x00, 0x10 }, - // [RP10]: PCIE PCH Root Port #10 - // [RP14]: PCIE PCH Root Port #14 - Package () { 0x001DFFFF, 0x01, 0x00, 0x11 }, - // [RP11]: PCIE PCH Root Port #11 - // [RP15]: PCIE PCH Root Port #15 - Package () { 0x001DFFFF, 0x02, 0x00, 0x12 }, - // [RP12]: PCIE PCH Root Port #12 - // [RP16]: PCIE PCH Root Port #16 - Package () { 0x001DFFFF, 0x03, 0x00, 0x13 }, - // [UAR0]: UART #0 on PCH - Package () { 0x001EFFFF, 0x02, 0x00, 0x16 }, - // [UAR1]: UART #1 on PCH - Package () { 0x001EFFFF, 0x03, 0x00, 0x17 }, - // [CAVS]: HD Audio Subsystem Controller on PCH - // [SMBS]: SMBus controller on PCH - // [GBE1]: GbE Controller on PCH - // [NTPK]: Northpeak Controller on PCH - Package () { 0x001FFFFF, 0x00, 0x00, 0x10 }, -}) - -// Socket 0, IIOStack 1 device legacy interrupt routing -Name (PR10, Package (0x40) -{ - // PCI Express Port 1A-1D - GEN_PCIE_LEGACY_IRQ(), - - // Uncore CHAUTIL Devices - GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), - GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), - - // Uncore CHASAD Devices - GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), - GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0011FFFF), - - // Uncore CMSCHA Devices - GEN_UNCORE_LEGACY_IRQ(0x0014FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF), - - // Uncore CHASADALL Device - GEN_UNCORE_LEGACY_IRQ(0x001DFFFF), - - // Uncore PCUCR Device - GEN_UNCORE_LEGACY_IRQ(0x001EFFFF), - - // Uncore VCUCR Device - GEN_UNCORE_LEGACY_IRQ(0x001FFFFF) -}) - -// Socket 0, IIOStack 1 device IOAPIC interrupt routing -Name (AR10, Package (0x40) -{ - // PCI Express Port 1A-1D - GEN_PCIE_IOAPIC_IRQ(0x27), - - // Uncore CHAUTIL Devices - GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x20, 0x24, 0x25, 0x26), - - // Uncore CHASAD Devices - GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0011FFFF, 0x20, 0x24, 0x25, 0x26), - - // Uncore CMSCHA Devices - GEN_UNCORE_IOAPIC_IRQ(0x0014FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x20, 0x24, 0x25, 0x26), - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x20, 0x24, 0x25, 0x26), - - // Uncore CHASADALL Device - GEN_UNCORE_IOAPIC_IRQ(0x001DFFFF, 0x20, 0x24, 0x25, 0x26), - - // Uncore PCUCR Device - GEN_UNCORE_IOAPIC_IRQ(0x001EFFFF, 0x20, 0x24, 0x25, 0x26), - - // Uncore VCUCR Device - GEN_UNCORE_IOAPIC_IRQ(0x001FFFFF, 0x20, 0x24, 0x25, 0x26) -}) - -// Socket 0, IIOStack 2 device legacy interrupt routing -Name (PR20, Package (0x24) -{ - // PCI Express Port 2 on PC02 - GEN_PCIE_LEGACY_IRQ(), - - // Uncore M2MEM Devices - GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), - - // Uncore MCMAIN Device - GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), - - // Uncore MCDECS2 Device - GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), - - // Uncore MCMAIN Device - GEN_UNCORE_LEGACY_IRQ(0x000CFFFF), - - // Uncore MCDECS Device - GEN_UNCORE_LEGACY_IRQ(0x000DFFFF), - - // Uncore Unicast MC0 DDRIO0 Device - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - - // Uncore Unicast MC1 DDRIO0 Device - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) -}) - -// Socket 0, IIOStack 2 device IOAPIC interrupt routing -Name (AR20, Package (0x24) -{ - // PCI Express Port 2 on PC02 - GEN_PCIE_IOAPIC_IRQ(0x2F), - - // Uncore M2MEM Devices - GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x28, 0x2C, 0x2D, 0x2E), - GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore MCMAIN Device - GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore MCDECS2 Device - GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore MCMAIN Device - GEN_UNCORE_IOAPIC_IRQ(0x000CFFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore MCDECS Device - GEN_UNCORE_IOAPIC_IRQ(0x000DFFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore Unicast MC0 DDRIO0 Device - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x28, 0x2C, 0x2D, 0x2E), - - // Uncore Unicast MC1 DDRIO0 Device - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x28, 0x2C, 0x2D, 0x2E) -}) - -// Socket 0, IIOStack 3 device legacy interrupt routing -Name (PR28, Package (0x20) -{ - // PCI Express Port 3 on PC03 - GEN_PCIE_LEGACY_IRQ(), - - // KTI Devices - GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), - GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), - - // M3K Device - GEN_UNCORE_LEGACY_IRQ(0x0012FFFF), - - // M2U Device - GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), - - // M2D Device - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - - // M20 Device - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) -}) - -// Socket 0, IIOStack 3 device IOAPIC interrupt routing -Name (AR28, Package (0x20) -{ - // PCI Express Port 3 on PC03 - GEN_PCIE_IOAPIC_IRQ(0x37), - - // KTI Devices - GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x30, 0x34, 0x35, 0x36), - GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x30, 0x34, 0x35, 0x36), - GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x30, 0x34, 0x35, 0x36), - - // M3K Device - GEN_UNCORE_IOAPIC_IRQ(0x0012FFFF, 0x30, 0x34, 0x35, 0x36), - - // M2U Device - GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x30, 0x34, 0x35, 0x36), - - // M2D Device - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x30, 0x34, 0x35, 0x36), - - // M20 Device - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x30, 0x34, 0x35, 0x36) -}) - -// Socket 1, IIOStack 0 device legacy interrupt routing -Name (PR40, Package (0x09) -{ - // DMI - Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, - - // CBDMA - GEN_UNCORE_LEGACY_IRQ(0x0004FFFF), - - // Ubox - GEN_UNCORE_LEGACY_IRQ(0x0008FFFF) -}) - -// Socket 1, IIOStack 0 device IOAPIC interrupt routing -Name (AR40, Package (0x09) -{ - // DMI - Package () { 0x0000FFFF, 0x00, 0x00, 0x4F }, - - // CBDMA - GEN_UNCORE_IOAPIC_IRQ(0x0004FFFF, 0x4A, 0x4B, 0x4A, 0x4B), - - // Ubox - GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x48, 0x4C, 0x4D, 0x4E), -}) - -// Socket 1, IIOStack 1 device legacy interrupt routing -Name (PR50, Package (0x40) -{ - // PCI Express Port - GEN_PCIE_LEGACY_IRQ(), - - // CHA Devices - GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), - GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), - GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0011FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0014FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF), - GEN_UNCORE_LEGACY_IRQ(0x001DFFFF), - - // PCU Devices - GEN_UNCORE_LEGACY_IRQ(0x001EFFFF), - GEN_UNCORE_LEGACY_IRQ(0x001FFFFF) -}) - -// Socket 1, IIOStack 1 device IOAPIC interrupt routing -Name (AR50, Package (0x40) -{ - // PCI Express Port - GEN_PCIE_IOAPIC_IRQ(0x57), - - // CHA Devices - GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0011FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0014FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x001DFFFF, 0x50, 0x54, 0x55, 0x56), - - // PCU Devices - GEN_UNCORE_IOAPIC_IRQ(0x001EFFFF, 0x50, 0x54, 0x55, 0x56), - GEN_UNCORE_IOAPIC_IRQ(0x001FFFFF, 0x50, 0x54, 0x55, 0x56) -}) - -// Socket 1, IIOStack 2 device legacy interrupt routing -Name (PR60, Package (0x24) -{ - // PCI Express Port - GEN_PCIE_LEGACY_IRQ(), - - // Integrated Memory Controller - GEN_UNCORE_LEGACY_IRQ(0x0008FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0009FFFF), - - // Uncore Devices - GEN_UNCORE_LEGACY_IRQ(0x000AFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000BFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000CFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000DFFFF), - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) -}) - -// Socket 1, IIOStack 2 device IOAPIC interrupt routing -Name (AR60, Package (0x24) -{ - // PCI Express Port - GEN_PCIE_IOAPIC_IRQ(0x5F), - - // Integrated Memory Controller - GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x0009FFFF, 0x58, 0x5C, 0x5D, 0x5E), - - // Uncore Devices - GEN_UNCORE_IOAPIC_IRQ(0x000AFFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x000BFFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x000CFFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x000DFFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x58, 0x5C, 0x5D, 0x5E), - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x58, 0x5C, 0x5D, 0x5E) -}) - -// Socket 1, IIOStack 3 device legacy interrupt routing -Name (PR68, Package (0x20) -{ - // PCI Express Port - GEN_PCIE_LEGACY_IRQ(), - - // Uncore Devices - GEN_UNCORE_LEGACY_IRQ(0x000EFFFF), - GEN_UNCORE_LEGACY_IRQ(0x000FFFFF), - GEN_UNCORE_LEGACY_IRQ(0x0010FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0012FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0015FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0016FFFF), - GEN_UNCORE_LEGACY_IRQ(0x0017FFFF) -}) - -// Socket 1, IIOStack 3 device legacy interrupt routing -Name (AR68, Package (0x20) -{ - // PCI Express Port - GEN_PCIE_IOAPIC_IRQ(0x67), - - // Uncore Devices - GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x000FFFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x0010FFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x0012FFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x0015FFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x0016FFFF, 0x60, 0x64, 0x65, 0x66), - GEN_UNCORE_IOAPIC_IRQ(0x0017FFFF, 0x60, 0x64, 0x65, 0x66) -}) -- To view, visit https://review.coreboot.org/c/coreboot/+/45217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b Gerrit-Change-Number: 45217 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: xeon_sp: Fix skx uncore.asl \_SB namespace issue
by Marc Jones (Code Review) 03 Oct '20

03 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45269 ) Change subject: xeon_sp: Fix skx uncore.asl \_SB namespace issue ...................................................................... xeon_sp: Fix skx uncore.asl \_SB namespace issue The skx uncore acpi scope was missing the \ on \_SB causing the uncore IRQs to not be in the namespace. This addresses ACPI uncore IRQ routing issues. This was found preparing skx acpi to match cpx acpi for merging in the future. Change-Id: I799042babbe60287e5e4ec60b21c08d57ccda04b Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/skx/acpi/uncore.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/45269/1 diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore.asl index 498a997..c6c6576 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/uncore.asl @@ -25,7 +25,7 @@ } } -Scope (_SB) +Scope (\_SB) { #include "pci_irq.asl" #include "uncore_irq.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/45269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I799042babbe60287e5e4ec60b21c08d57ccda04b Gerrit-Change-Number: 45269 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 13

Change in coreboot[master]: xeon_sp: Update skx pci_irq.asl for ACPI2.0 notation
by Marc Jones (Code Review) 03 Oct '20

03 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45270 ) Change subject: xeon_sp: Update skx pci_irq.asl for ACPI2.0 notation ...................................................................... xeon_sp: Update skx pci_irq.asl for ACPI2.0 notation Use the C style operators instead of the ACPI1.x polish notation. This is much easier to read. It also matches the cpx code for easier merging later. This generates the same ASL code. Checked with BUILD_TIMLESS. Change-Id: Id44138894d2ffed4c93afe5d4bbb4d59b538b577 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/45270/1 diff --git a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl index dcb6fe2..b2a2ebf 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl @@ -8,10 +8,8 @@ * PIRQ routing control is in PCR ITSS region. */ -OperationRegion (ITSS, SystemMemory, - Add (PCR_ITSS_PIRQA_ROUT, - Add (CONFIG_PCR_BASE_ADDRESS, - ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8) +OperationRegion (ITSS, SystemMemory, PCR_ITSS_PIRQA_ROUT + + CONFIG_PCR_BASE_ADDRESS + (PID_ITSS << PCR_PORTID_SHIFT), 8) Field (ITSS, ByteAcc, NoLock, Preserve) { PIRA, 8, /* PIRQA Routing Control */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id44138894d2ffed4c93afe5d4bbb4d59b538b577 Gerrit-Change-Number: 45270 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: xeon_sp: Update skx uncore irq routing acpi tables
by Marc Jones (Code Review) 03 Oct '20

03 Oct '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45271 ) Change subject: xeon_sp: Update skx uncore irq routing acpi tables ...................................................................... xeon_sp: Update skx uncore irq routing acpi tables Update the skx uncore acpi routing tables to match cpx. This adds the irq routing for B-D for legacy and IOAPIC modes. Change-Id: Iac0ffdb467a78b9befe7402c074835ea602d43c8 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl 1 file changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45271/1 diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl index 9926367..3395e7d 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl @@ -8,9 +8,9 @@ #define GEN_PCIE_LEGACY_IRQ() \ Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ - Package () { 0x0001FFFF, 0x00, LNKA, 0x00 }, \ - Package () { 0x0002FFFF, 0x00, LNKA, 0x00 }, \ - Package () { 0x0003FFFF, 0x00, LNKA, 0x00 } + Package () { 0x0001FFFF, 0x01, LNKB, 0x00 }, \ + Package () { 0x0002FFFF, 0x02, LNKC, 0x00 }, \ + Package () { 0x0003FFFF, 0x03, LNKD, 0x00 } #define GEN_UNCORE_LEGACY_IRQ(dev) \ Package () { ##dev, 0x00, LNKA, 0x00 }, \ @@ -18,11 +18,11 @@ Package () { ##dev, 0x02, LNKC, 0x00 }, \ Package () { ##dev, 0x03, LNKD, 0x00 } -#define GEN_PCIE_IOAPIC_IRQ(irq) \ - Package () { 0x0000FFFF, 0x00, 0x00, ##irq }, \ - Package () { 0x0001FFFF, 0x00, 0x00, ##irq }, \ - Package () { 0x0002FFFF, 0x00, 0x00, ##irq }, \ - Package () { 0x0003FFFF, 0x00, 0x00, ##irq } +#define GEN_PCIE_IOAPIC_IRQ(irq1, irq2, irq3, irq4) \ + Package () { 0x0000FFFF, 0x00, 0x00, ##irq1 }, \ + Package () { 0x0001FFFF, 0x01, 0x00, ##irq2 }, \ + Package () { 0x0002FFFF, 0x02, 0x00, ##irq3 }, \ + Package () { 0x0003FFFF, 0x03, 0x00, ##irq4 } #define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \ Package () { ##dev, 0x00, 0x00, ##irq1 }, \ @@ -265,8 +265,8 @@ // Socket 0, IIOStack 1 device IOAPIC interrupt routing Name (AR10, Package (0x40) { - // PCI Express Port 1A-1D - GEN_PCIE_IOAPIC_IRQ(0x27), + // PCI Express Port A-D + GEN_PCIE_IOAPIC_IRQ(0x27,0x21,0x22,0x23), // Uncore CHAUTIL Devices GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x20, 0x24, 0x25, 0x26), @@ -299,7 +299,7 @@ // Socket 0, IIOStack 2 device legacy interrupt routing Name (PR20, Package (0x24) { - // PCI Express Port 2 on PC02 + // PCI Express Port A-D on PC02 GEN_PCIE_LEGACY_IRQ(), // Uncore M2MEM Devices @@ -328,8 +328,8 @@ // Socket 0, IIOStack 2 device IOAPIC interrupt routing Name (AR20, Package (0x24) { - // PCI Express Port 2 on PC02 - GEN_PCIE_IOAPIC_IRQ(0x2F), + // PCI Express Port A-D on PC02 + GEN_PCIE_IOAPIC_IRQ(0x2F,0x29,0x2A,0x2B), // Uncore M2MEM Devices GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x28, 0x2C, 0x2D, 0x2E), @@ -381,8 +381,8 @@ // Socket 0, IIOStack 3 device IOAPIC interrupt routing Name (AR28, Package (0x20) { - // PCI Express Port 3 on PC03 - GEN_PCIE_IOAPIC_IRQ(0x37), + // PCI Express Port 3 A-D on PC03 + GEN_PCIE_IOAPIC_IRQ(0x37,0x31,0x32,0x33), // KTI Devices GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x30, 0x34, 0x35, 0x36), @@ -457,8 +457,8 @@ // Socket 1, IIOStack 1 device IOAPIC interrupt routing Name (AR50, Package (0x40) { - // PCI Express Port - GEN_PCIE_IOAPIC_IRQ(0x57), + // PCI Express Port A-D + GEN_PCIE_IOAPIC_IRQ(0x57,0x51,0x52,0x53), // CHA Devices GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x50, 0x54, 0x55, 0x56), @@ -502,8 +502,8 @@ // Socket 1, IIOStack 2 device IOAPIC interrupt routing Name (AR60, Package (0x24) { - // PCI Express Port - GEN_PCIE_IOAPIC_IRQ(0x5F), + // PCI Express Port A-D + GEN_PCIE_IOAPIC_IRQ(0x5F,0x59,0x5A,0x5B), // Integrated Memory Controller GEN_UNCORE_IOAPIC_IRQ(0x0008FFFF, 0x58, 0x5C, 0x5D, 0x5E), @@ -537,8 +537,8 @@ // Socket 1, IIOStack 3 device legacy interrupt routing Name (AR68, Package (0x20) { - // PCI Express Port - GEN_PCIE_IOAPIC_IRQ(0x67), + // PCI Express Port A-D + GEN_PCIE_IOAPIC_IRQ(0x67,0x61,0x62,0x63), // Uncore Devices GEN_UNCORE_IOAPIC_IRQ(0x000EFFFF, 0x60, 0x64, 0x65, 0x66), -- To view, visit https://review.coreboot.org/c/coreboot/+/45271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac0ffdb467a78b9befe7402c074835ea602d43c8 Gerrit-Change-Number: 45271 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config
by Shelley Chen (Code Review) 03 Oct '20

03 Oct '20

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45740 ) Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ...................................................................... drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't do mmapping but still want to use the cbmem to store the mrc_cache data in order to write the mrc_cache data back at a later time. We are maintaining the use of cbmem for these older platforms because we have no way of validating the earlier write back to mrc_cache at this time. BUG=b:150502246 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/drivers/spi/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 20 files changed, 15 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45740/1 diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index fe0b9a7..acca7fe 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -10,6 +10,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 78cac30..84cfbf0 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -9,6 +9,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 1918428..e5a119b 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -9,6 +9,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select MMX select SSE2 select UDELAY_TSC diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 42068f4..644c211 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -42,8 +42,16 @@ Provide common implementation of the RW boot device that doesn't provide mmap() operations. +config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES + bool + default n + depends on BOOT_DEVICE_SPI_FLASH_RW_NOMMAP + help + For x86 platforms who do not include the boot_device_rw_nommap libraries in romstage + config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY bool + default y if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP && !BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES default n depends on BOOT_DEVICE_SPI_FLASH_RW_NOMMAP help diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 27754c8..00e9a3a 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -12,6 +12,7 @@ select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select PARALLEL_MP + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config CBFS_SIZE hex diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 29ebc6d..fe43a72 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -44,7 +44,6 @@ select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index b29bd99..6737c02 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -41,7 +41,6 @@ select SOC_AMD_COMMON_BLOCK_S3 select SOC_AMD_COMMON_BLOCK_SMBUS select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 33acf43..d35ae62 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -10,7 +10,6 @@ select ARCH_BOOTBLOCK_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a30333b..71a17ff 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -25,7 +25,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES # CPU specific options select CPU_INTEL_COMMON diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index b23f56d..90b4e1d 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -12,6 +12,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index bf067da..5c9988c 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -12,6 +12,7 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 156d58a..c59e0ca 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -12,6 +12,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 596de41..f043955 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -78,7 +78,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 91b45dc..ce2e0b4 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -13,7 +13,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select DEBUG_GPIO select SOC_INTEL_COMMON diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 166bda0..920f231 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -12,7 +12,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 1e66e97..6af8fd2 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -12,7 +12,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 15dc1b3..e851fbe 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -12,7 +12,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index db0f688..1c8a7c0 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -23,7 +23,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index d92d496..6917ab9 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -12,7 +12,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 31d12fc..8d87628 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -29,7 +29,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CPU_INTEL_COMMON select SOC_INTEL_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/45740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Gerrit-Change-Number: 45740 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: mrc_cache: Update mrc_cache data in romstage
by Shelley Chen (Code Review) 02 Oct '20

02 Oct '20

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44196 ) Change subject: mrc_cache: Update mrc_cache data in romstage ...................................................................... mrc_cache: Update mrc_cache data in romstage Previously, we were writing to cbmem after memory training and then writing the training data from cbmem to mrc_cache in ramstage. We were doing this because we were unable to read/write to SPI simultaneously on older SIP chips. Now that newer chips allow for simultaneously reads and writes, we can move the mrc_cache update into romstage. BUG=b:150502246 BRANCH=None TEST=reboot from ec console. Make sure memory training happens. reboot from ec console. Make sure that we don't do training again. Signed-off-by: Shelley Chen <shchen(a)google.com> Change-Id: I3430bda45484cb8c2b01ab9614508039dfaac9a3 --- M src/drivers/elog/Makefile.inc M src/drivers/mrc_cache/mrc_cache.c M src/include/region_file.h M src/lib/region_file.c 4 files changed, 137 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/44196/1 diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc index cce1c3d..a1c14ff 100644 --- a/src/drivers/elog/Makefile.inc +++ b/src/drivers/elog/Makefile.inc @@ -1,6 +1,7 @@ bootblock-$(CONFIG_ELOG_PRERAM) += elog.c verstage-$(CONFIG_ELOG_PRERAM) += elog.c romstage-$(CONFIG_ELOG_PRERAM) += elog.c +romstage-$(CONFIG_ELOG) += elog.c postcar-$(CONFIG_ELOG_PRERAM) += elog.c ramstage-$(CONFIG_ELOG) += elog.c diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 0e42120..2dc6ee8 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -311,18 +311,26 @@ } static bool mrc_cache_needs_update(const struct region_device *rdev, - const struct cbmem_entry *to_be_updated) + struct mrc_metadata *new_md, + const void *new_data, size_t new_data_size) { - void *mapping; + void *mapping, *data_mapping; size_t size = region_device_sz(rdev); bool need_update = false; - if (cbmem_entry_size(to_be_updated) != size) + if (new_data_size != size) return true; mapping = rdev_mmap_full(rdev); + data_mapping = mapping + sizeof(struct mrc_metadata); - if (memcmp(cbmem_entry_start(to_be_updated), mapping, size)) + // we need to compare the md and the data separately + // check the mrc_metadata + if (memcmp(new_md, mapping, sizeof(struct mrc_metadata))) + need_update = true; + + // check the data + if (memcmp(new_data, data_mapping, new_data_size)) need_update = true; rdev_munmap(rdev, mapping); @@ -357,7 +365,10 @@ * read and write. The read assumes a memory-mapped boot device that can be used * to quickly locate and compare the up-to-date data. However, when an update * is required it uses the writeable region access to perform the update. */ -static void update_mrc_cache_by_type(int type) +static void update_mrc_cache_by_type(int type, + struct mrc_metadata *new_md, + const void *new_data, + size_t new_data_size) { const struct cache_region *cr; struct region region; @@ -365,7 +376,6 @@ struct region_device write_rdev; struct region_file cache_file; struct mrc_metadata md; - const struct cbmem_entry *to_be_updated; struct incoherent_rdev backing_irdev; const struct region_device *backing_rdev; struct region_device latest_rdev; @@ -376,13 +386,6 @@ if (cr == NULL) return; - to_be_updated = cbmem_entry_find(cr->cbmem_id); - if (to_be_updated == NULL) { - printk(BIOS_ERR, "MRC: No data in cbmem for '%s'.\n", - cr->name); - return; - } - printk(BIOS_DEBUG, "MRC: Checking cached data update for '%s'.\n", cr->name); @@ -411,8 +414,9 @@ return; - if (!mrc_cache_needs_update(&latest_rdev, to_be_updated)) { - printk(BIOS_DEBUG, "MRC: '%s' does not need update.\n", cr->name); + if (!mrc_cache_needs_update(&latest_rdev, + new_md, + new_data, new_data_size)) { log_event_cache_update(cr->elog_slot, ALREADY_UPTODATE); return; } @@ -420,9 +424,10 @@ printk(BIOS_DEBUG, "MRC: cache data '%s' needs update.\n", cr->name); if (region_file_update_data(&cache_file, - cbmem_entry_start(to_be_updated), - cbmem_entry_size(to_be_updated)) < 0) { - printk(BIOS_DEBUG, "MRC: failed to update '%s'.\n", cr->name); + new_md, + sizeof(struct mrc_metadata), + new_data, + new_data_size) < 0) { log_event_cache_update(cr->elog_slot, UPDATE_FAILURE); } else { printk(BIOS_DEBUG, "MRC: updated '%s'.\n", cr->name); @@ -544,16 +549,59 @@ /* Push an update that consists of 4 bytes that is smaller than the * MRC metadata as well as an invalid signature. */ - if (region_file_update_data(&cache_file, &invalid, sizeof(invalid)) < 0) + if (region_file_update_data(&cache_file, NULL, 0, + &invalid, sizeof(invalid)) < 0) printk(BIOS_ERR, "MRC: invalidation failed for '%s'.\n", name); } -static void update_mrc_cache(void *unused) +static void update_mrc_cache(struct mrc_metadata *md, + const void *data, + size_t size) { - update_mrc_cache_by_type(MRC_TRAINING_DATA); + update_mrc_cache_by_type(MRC_TRAINING_DATA, md, data, size); if (CONFIG(MRC_SETTINGS_VARIABLE_DATA)) - update_mrc_cache_by_type(MRC_VARIABLE_DATA); + update_mrc_cache_by_type(MRC_VARIABLE_DATA, + md, data, size); + + if (CONFIG(MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN)) + invalidate_normal_cache(); + + protect_mrc_region(); +} + +static void update_mrc_cache_from_cbmem(int type) +{ + const struct cache_region *cr; + struct region region; + struct mrc_metadata md; + const struct cbmem_entry *to_be_updated; + + cr = lookup_region(&region, type); + + if (cr == NULL) + return; + + to_be_updated = cbmem_entry_find(cr->cbmem_id); + + if (to_be_updated == NULL) { + printk(BIOS_ERR, "MRC: No data in cbmem for '%s'.\n", + cr->name); + return; + } + + update_mrc_cache(&md, + cbmem_entry_start(to_be_updated), + cbmem_entry_size(to_be_updated)); +} + +static void finalize_mrc_cache(void *unused) +{ + if (CONFIG(MRC_WRITE_NV_LATE)) + update_mrc_cache_from_cbmem(MRC_TRAINING_DATA); + + if (CONFIG(MRC_SETTINGS_VARIABLE_DATA)) + update_mrc_cache_from_cbmem(MRC_VARIABLE_DATA); if (CONFIG(MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN)) invalidate_normal_cache(); @@ -562,11 +610,9 @@ } int mrc_cache_stash_data(int type, uint32_t version, const void *data, - size_t size) + size_t size) { const struct cache_region *cr; - size_t cbmem_size; - struct mrc_metadata *md; cr = lookup_region_type(type); if (cr == NULL) { @@ -575,24 +621,41 @@ return -1; } - cbmem_size = sizeof(*md) + size; + if (CONFIG(MRC_WRITE_NV_LATE)) { + /* Store data in cbmem for use in ramstage */ + struct mrc_metadata *md; + size_t cbmem_size; + cbmem_size = sizeof(*md) + size; - md = cbmem_add(cr->cbmem_id, cbmem_size); + md = cbmem_add(cr->cbmem_id, cbmem_size); - if (md == NULL) { - printk(BIOS_ERR, "MRC: failed to add '%s' to cbmem.\n", - cr->name); - return -1; + if (md == NULL) { + printk(BIOS_ERR, "MRC: failed to add '%s' to cbmem.\n", + cr->name); + return -1; + } + + memset(md, 0, sizeof(*md)); + md->signature = MRC_DATA_SIGNATURE; + md->data_size = size; + md->version = version; + md->data_checksum = compute_ip_checksum(data, size); + md->header_checksum = compute_ip_checksum(md, sizeof(*md)); + memcpy(&md[1], data, size); + } else { + /* Otherwise store to mrc_cache right away */ + struct mrc_metadata md; + + memset(&md, 0, sizeof(struct mrc_metadata)); + md.signature = MRC_DATA_SIGNATURE; + md.data_size = size; + md.version = version; + md.data_checksum = compute_ip_checksum(data, size); + md.header_checksum = + compute_ip_checksum(&md, sizeof(struct mrc_metadata)); + + update_mrc_cache(&md, data, size); } - - memset(md, 0, sizeof(*md)); - md->signature = MRC_DATA_SIGNATURE; - md->data_size = size; - md->version = version; - md->data_checksum = compute_ip_checksum(data, size); - md->header_checksum = compute_ip_checksum(md, sizeof(*md)); - memcpy(&md[1], data, size); - return 0; } @@ -602,7 +665,7 @@ */ #if CONFIG(MRC_WRITE_NV_LATE) -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_ENTRY, update_mrc_cache, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_ENTRY, finalize_mrc_cache, NULL); #else -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, update_mrc_cache, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, finalize_mrc_cache, NULL); #endif diff --git a/src/include/region_file.h b/src/include/region_file.h index 063e0e0..068e147 100644 --- a/src/include/region_file.h +++ b/src/include/region_file.h @@ -32,8 +32,11 @@ int region_file_data(const struct region_file *f, struct region_device *rdev); /* Update region file with latest data. Returns < 0 on error, 0 on success. */ -int region_file_update_data(struct region_file *f, const void *buf, - size_t size); +int region_file_update_data(struct region_file *f, + const void *metadata, + size_t metadata_size, + const void *data, + size_t data_size); /* Declared here for easy object allocation. */ struct region_file { diff --git a/src/lib/region_file.c b/src/lib/region_file.c index ce2ed30..3f47b28 100644 --- a/src/lib/region_file.c +++ b/src/lib/region_file.c @@ -365,11 +365,17 @@ return 0; } -static int commit_data(const struct region_file *f, const void *buf, - size_t size) +static int commit_data(const struct region_file *f, + const void *metadata, + size_t metadata_size, + const void *data_buf, + size_t data_size) { size_t offset = block_to_bytes(region_file_data_begin(f)); - if (rdev_writeat(&f->rdev, buf, offset, size) < 0) + if (rdev_writeat(&f->rdev, metadata, offset, metadata_size) < 0) + return -1; + offset += metadata_size; + if (rdev_writeat(&f->rdev, data_buf, offset, data_size) < 0) return -1; return 0; } @@ -399,8 +405,12 @@ return 0; } -static int handle_update(struct region_file *f, size_t blocks, const void *buf, - size_t size) +static int handle_update(struct region_file *f, + size_t blocks, + const void *metadata, + size_t metadata_size, + const void *data, + size_t data_size) { if (!update_can_fit(f, blocks)) { printk(BIOS_INFO, "REGF update can't fit. Will empty.\n"); @@ -413,7 +423,7 @@ return -1; } - if (commit_data(f, buf, size)) { + if (commit_data(f, metadata, metadata_size, data, data_size)) { printk(BIOS_ERR, "REGF failed to commit data.\n"); return -1; } @@ -421,12 +431,18 @@ return 0; } -int region_file_update_data(struct region_file *f, const void *buf, size_t size) +int region_file_update_data(struct region_file *f, + const void *metadata, + size_t metadata_size, + const void *data, + size_t data_size) { int ret; size_t blocks; - blocks = bytes_to_block(ALIGN_UP(size, REGF_BLOCK_GRANULARITY)); + blocks = bytes_to_block(ALIGN_UP(data_size + + metadata_size, + REGF_BLOCK_GRANULARITY)); while (1) { int prev_slot = f->slot; @@ -442,7 +458,8 @@ ret = -1; break; default: - ret = handle_update(f, blocks, buf, size); + ret = handle_update(f, blocks, metadata, + metadata_size, data, data_size); break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3430bda45484cb8c2b01ab9614508039dfaac9a3 Gerrit-Change-Number: 44196 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

7 43

Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,elh}: PM ACPI timer state from Kconfig
by Michael Niewöhner (Code Review) 02 Oct '20

02 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45957 ) Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,elh}: PM ACPI timer state from Kconfig ...................................................................... Patch Set 9: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf1eee9297034b29b7250f6c752e6f7f52b4b908 Gerrit-Change-Number: 45957 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Oct 2020 22:45:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,elh}: drop duplicate PM ACPI timer ...
by Michael Niewöhner (Code Review) 02 Oct '20

02 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45958 ) Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,elh}: drop duplicate PM ACPI timer disabling ...................................................................... Patch Set 9: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5594ac423d6dff4c3212d657c242137492dc5d2a Gerrit-Change-Number: 45958 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Oct 2020 22:39:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,elh}: guard ACPI timer emulation en...
by Michael Niewöhner (Code Review) 02 Oct '20

02 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45956 ) Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,elh}: guard ACPI timer emulation enablement ...................................................................... Patch Set 9: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3e2eaf37b3e6f1dc3360331d343db9aa178adcc Gerrit-Change-Number: 45956 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Oct 2020 22:38:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2020