coreboot-gerrit October 2020

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Change in coreboot[master]: mb/google/volteer: Expand WP_RO region to 8MB in fmap
by Furquan Shaikh (Code Review) 02 Oct '20

02 Oct '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45889 ) Change subject: mb/google/volteer: Expand WP_RO region to 8MB in fmap ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/45889/2/src/mainboard/google/volte… File src/mainboard/google/volteer/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/45889/2/src/mainboard/google/volte… PS2, Line 9: # SPI flash only the top 16MiB actually gets memory mapped. > That is correct, x86 only memory maps the top 16 MiB of SPI flash, so in this case RW_SECTION_A ends […] +1 to what Julius and Tim said. The RW_SECTIONs need to stay above 16MiB so that they are memory mapped. About reducing the RW sizes by 2MiB each - I think it might be really difficult given the size of CSME RW binary. Has any one actually performed an analysis of how much we are actually using in each of these sections and what the worst case sizes would be? Karthik put together a nice worksheet for JSL(dedede): https://docs.google.com/spreadsheets/d/1FtivbWNQ78ozU5b5Ds10q-jZ09jRfa8Qb5G…. We need something similar for TGL(volteer) as well to understand the actual usage. -- To view, visit https://review.coreboot.org/c/coreboot/+/45889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72fe8b6a1f91390c218230c0c20825769ebd1e0b Gerrit-Change-Number: 45889 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 02 Oct 2020 07:05:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/opencellular/elgon/mainboard.c: Use PRIu64 type to print u64
by HAOUAS Elyes (Code Review) 02 Oct '20

02 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45910 ) Change subject: mb/opencellular/elgon/mainboard.c: Use PRIu64 type to print u64 ...................................................................... mb/opencellular/elgon/mainboard.c: Use PRIu64 type to print u64 Change-Id: I96d3f01094cc281d76ffbc9bc4bae1bbf37ffa70 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/opencellular/elgon/mainboard.c 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45910/1 diff --git a/src/mainboard/opencellular/elgon/mainboard.c b/src/mainboard/opencellular/elgon/mainboard.c index f9dc03c..6e9bba3 100644 --- a/src/mainboard/opencellular/elgon/mainboard.c +++ b/src/mainboard/opencellular/elgon/mainboard.c @@ -17,6 +17,7 @@ #include <soc/spi.h> #include <spi_flash.h> #include <fmap.h> +#include <inttypes.h> static void mainboard_print_info(void) { @@ -61,13 +62,13 @@ printk(BIOS_INFO, "unknown\n"); } - printk(BIOS_INFO, "MB: REFclk : %llu MHz\n", + printk(BIOS_INFO, "MB: REFclk : %"PRIu64 " MHz\n", thunderx_get_ref_clock() / 1000000ULL); - printk(BIOS_INFO, "MB: IOclk : %llu MHz\n", + printk(BIOS_INFO, "MB: IOclk : %"PRIu64 " MHz\n", thunderx_get_io_clock() / 1000000ULL); - printk(BIOS_INFO, "MB: COREclk : %llu MHz\n", + printk(BIOS_INFO, "MB: COREclk : %"PRIu64 " MHz\n", thunderx_get_core_clock() / 1000000ULL); printk(BIOS_INFO, "MB: #CPU cores : %zu\n", @@ -76,7 +77,7 @@ printk(BIOS_INFO, "MB: RAM : %zu MiB\n", sdram_size_mb()); - printk(BIOS_INFO, "MB: SPIclk : %llu kHz\n", + printk(BIOS_INFO, "MB: SPIclk : %"PRIu64 " kHz\n", spi_get_clock(0) >> 10); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96d3f01094cc281d76ffbc9bc4bae1bbf37ffa70 Gerrit-Change-Number: 45910 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/cavium/cn81xx/timer.c: Use PRIu64 type to print u64
by HAOUAS Elyes (Code Review) 02 Oct '20

02 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45948 ) Change subject: soc/cavium/cn81xx/timer.c: Use PRIu64 type to print u64 ...................................................................... soc/cavium/cn81xx/timer.c: Use PRIu64 type to print u64 Change-Id: I792c2c69d4798979b37beae767087b67d7f5b2d1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/cavium/cn81xx/timer.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/45948/1 diff --git a/src/soc/cavium/cn81xx/timer.c b/src/soc/cavium/cn81xx/timer.c index d9879ba..32c9b2b 100644 --- a/src/soc/cavium/cn81xx/timer.c +++ b/src/soc/cavium/cn81xx/timer.c @@ -14,6 +14,7 @@ #include <timer.h> #include <soc/addressmap.h> #include <assert.h> +#include <inttypes.h> /* Global System Timers Unit (GTI) registers */ struct cn81xx_timer { @@ -157,7 +158,7 @@ if (timeout_wdog >= 0x10000) timeout_wdog = 0xffff; - printk(BIOS_DEBUG, "Watchdog: Set to expire %llu SCLK cycles\n", + printk(BIOS_DEBUG, "Watchdog: Set to expire %" PRIu64 "SCLK cycles\n", timeout_wdog << 18); clrsetbits64(&timer->cwd_wdog[index], (GTI_CWD_WDOG_LEN_MASK << GTI_CWD_WDOG_LEN_SHIFT) | -- To view, visit https://review.coreboot.org/c/coreboot/+/45948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I792c2c69d4798979b37beae767087b67d7f5b2d1 Gerrit-Change-Number: 45948 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/timestamp.c: Use PRIu64 type to print u64
by HAOUAS Elyes (Code Review) 02 Oct '20

02 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45947 ) Change subject: lib/timestamp.c: Use PRIu64 type to print u64 ...................................................................... lib/timestamp.c: Use PRIu64 type to print u64 Change-Id: I6834e66d6f23cd12be196fbba0ea3895d65643cc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/lib/timestamp.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/45947/1 diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 7347d07..3f71786 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -8,6 +8,7 @@ #include <timer.h> #include <timestamp.h> #include <smp/node.h> +#include <inttypes.h> #define MAX_TIMESTAMPS 192 @@ -135,7 +136,7 @@ timestamp_add_table_entry(ts_table, id, ts_time); if (CONFIG(TIMESTAMPS_ON_CONSOLE)) - printk(BIOS_INFO, "Timestamp - %s: %llu\n", timestamp_name(id), ts_time); + printk(BIOS_INFO, "Timestamp - %s: %" PRIu64 "\n", timestamp_name(id), ts_time); } void timestamp_add_now(enum timestamp_id id) -- To view, visit https://review.coreboot.org/c/coreboot/+/45947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6834e66d6f23cd12be196fbba0ea3895d65643cc Gerrit-Change-Number: 45947 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/cavium/cn8100_sff_evb/mainboard.c: Use PRIu64 type to print u64
by HAOUAS Elyes (Code Review) 02 Oct '20

02 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45909 ) Change subject: mb/cavium/cn8100_sff_evb/mainboard.c: Use PRIu64 type to print u64 ...................................................................... mb/cavium/cn8100_sff_evb/mainboard.c: Use PRIu64 type to print u64 Change-Id: Ic0cf15c2d5bb29d039513ce8cdef4e5b1f229fda Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/cavium/cn8100_sff_evb/mainboard.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/45909/1 diff --git a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c index 3b26722..fc702ce 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c +++ b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c @@ -16,6 +16,7 @@ #include <soc/timer.h> #include <soc/cpu.h> #include <soc/sdram.h> +#include <inttypes.h> static void mainboard_print_info(void) { @@ -48,13 +49,13 @@ printk(BIOS_INFO, "unknown\n"); } - printk(BIOS_INFO, "MB: REFclk : %llu MHz\n", + printk(BIOS_INFO, "MB: REFclk : %"PRIu64 " MHz\n", thunderx_get_ref_clock() / 1000000ULL); - printk(BIOS_INFO, "MB: IOclk : %llu MHz\n", + printk(BIOS_INFO, "MB: IOclk : %"PRIu64 " MHz\n", thunderx_get_io_clock() / 1000000ULL); - printk(BIOS_INFO, "MB: COREclk : %llu MHz\n", + printk(BIOS_INFO, "MB: COREclk : %"PRIu64 " MHz\n", thunderx_get_core_clock() / 1000000ULL); printk(BIOS_INFO, "MB: #CPU cores : %zu\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/45909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0cf15c2d5bb29d039513ce8cdef4e5b1f229fda Gerrit-Change-Number: 45909 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/ifdtool: Include ADL dynamic check as per Gen12 SPI flash guide
by Subrata Banik (Code Review) 02 Oct '20

02 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45808 ) Change subject: util/ifdtool: Include ADL dynamic check as per Gen12 SPI flash guide ...................................................................... util/ifdtool: Include ADL dynamic check as per Gen12 SPI flash guide BUG=b:153888802 TEST=Able to list correct PCH revision, SPI/eSPI frequency as per ADL SPI flash guide. Without this CL : PCH Revision: 500 series Tiger Point With this CL : PCH Revision: 500 series Tiger Point/ 600 series Alder Point Change-Id: I0faf0f0fdb625ff82eb0033b5b77e6470971bc23 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/45808/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index fab034a..220c140 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -72,7 +72,7 @@ "Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx", "100/200 series Sunrise Point", "300 series Cannon Point/ 400 series Ice Point", - "500 series Tiger Point", + "500 series Tiger Point/ 600 series Alder Point", "C620 series Lewisburg", NULL }; @@ -181,7 +181,7 @@ /* Offset 0x58 bit [2:0] is reserved 0x4 and 0x5a bit [7:0] is reserved 0x58 */ if (((pchstrp_22 & 0x07) == 0x4) && ((pchstrp_22 & 0xFF0000) >> 16 == 0x58)) - return CHIPSET_500_SERIES_TIGER_POINT; + return CHIPSET_500_600_SERIES_TIGER_ALDER_POINT; return CHIPSET_PCH_UNKNOWN; } @@ -503,7 +503,7 @@ static void decode_spi_frequency(unsigned int freq) { - if (chipset == CHIPSET_500_SERIES_TIGER_POINT) + if (chipset == CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) _decode_spi_frequency_500_series(freq); else _decode_spi_frequency(freq); @@ -560,7 +560,7 @@ static void decode_espi_frequency(unsigned int freq) { - if (chipset == CHIPSET_500_SERIES_TIGER_POINT) + if (chipset == CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) _decode_espi_frequency_500_series(freq); else _decode_espi_frequency(freq); @@ -613,7 +613,7 @@ static int is_platform_with_100x_series_pch(void) { if (chipset >= CHIPSET_100_200_SERIES_SUNRISE_POINT && - chipset <= CHIPSET_500_SERIES_TIGER_POINT) + chipset <= CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) return 1; return 0; @@ -638,7 +638,7 @@ if (is_platform_with_100x_series_pch() && chipset != CHIPSET_100_200_SERIES_SUNRISE_POINT) { printf("\n Read eSPI/EC Bus Frequency: "); - if (chipset == CHIPSET_500_SERIES_TIGER_POINT) + if (chipset == CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) freq = (fpsba->pchstrp[22] & 0x38) >> 3; else freq = (fcba->flcomp >> 17) & 7; @@ -911,7 +911,7 @@ printf(" FMSBA: 0x%x\n", ((fdb->flmap2) & 0xff) << 4); } - if (chipset == CHIPSET_500_SERIES_TIGER_POINT) { + if (chipset == CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) { printf("FLMAP3: 0x%08x\n", fdb->flmap3); printf(" Minor Revision ID: 0x%04x\n", (fdb->flmap3 >> 14) & 0x7f); printf(" Major Revision ID: 0x%04x\n", (fdb->flmap3 >> 21) & 0x7ff); diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index b725823..3444d9f 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -38,7 +38,9 @@ CHIPSET_N_J_SERIES, /* Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx */ CHIPSET_100_200_SERIES_SUNRISE_POINT, /* 6th-7th gen Core i/o (LP) variants */ CHIPSET_300_400_SERIES_CANNON_ICE_POINT, /* 8th-10th gen Core i/o (LP) variants */ - CHIPSET_500_SERIES_TIGER_POINT, /* 11th gen Core i/o (LP) variants onwards */ + CHIPSET_500_600_SERIES_TIGER_ALDER_POINT, /* 11th-12th gen Core i/o (LP) + * variants onwards + */ CHIPSET_C620_SERIES_LEWISBURG, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/45808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0faf0f0fdb625ff82eb0033b5b77e6470971bc23 Gerrit-Change-Number: 45808 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: tgl/usb: disable TBT if hardware is not USB4
by Nick Vaccaro (Code Review) 02 Oct '20

02 Oct '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45945 ) Change subject: tgl/usb: disable TBT if hardware is not USB4 ...................................................................... tgl/usb: disable TBT if hardware is not USB4 TBT being enabled in FSP without USB4 hardware causes an issue powering off in depthcharge. Disable TBT for FSP if USB hardware is not USB4. BUG=b:167983038 TEST=none Change-Id: Icbe743f917bf0a6899fe4587db8a2ddd60715c88 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/fsp_params.c A src/soc/intel/tigerlake/include/soc/mainboard_support.h A src/soc/intel/tigerlake/mainboard_weak_support.c M src/soc/intel/tigerlake/romstage/fsp_params.c 5 files changed, 29 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/45945/1 diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index c4f71c7..4a68e68 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -24,8 +24,9 @@ bootblock-y += p2sb.c romstage-y += espi.c -romstage-y += meminit.c romstage-y += gpio.c +ramstage-y += mainboard_weak_support.c +romstage-y += meminit.c romstage-y += reset.c ramstage-y += acpi.c @@ -37,6 +38,7 @@ ramstage-y += fsp_params.c ramstage-y += gpio.c ramstage-y += lockdown.c +ramstage-y += mainboard_weak_support.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += reset.c diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 38f444b..551aef11 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -16,6 +16,7 @@ #include <security/vboot/vboot_common.h> #include <soc/gpio_soc_defs.h> #include <soc/intel/common/vbt.h> +#include <soc/mainboard_support.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> @@ -310,10 +311,13 @@ /* USB4/TBT */ for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) { dev = pcidev_on_root(SA_DEV_SLOT_TBT, i); - if (dev) + if (is_dev_enabled(dev) && mainboard_supports_usb4()) { + printk(BIOS_INFO, + "ITbtPcieRootPortEn%d is enabled\n", i); params->ITbtPcieRootPortEn[i] = dev->enabled; - else + } else { params->ITbtPcieRootPortEn[i] = 0; + } } /* PCH FIVR settings override */ diff --git a/src/soc/intel/tigerlake/include/soc/mainboard_support.h b/src/soc/intel/tigerlake/include/soc/mainboard_support.h new file mode 100644 index 0000000..a43fa33 --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/mainboard_support.h @@ -0,0 +1,10 @@ +#ifndef _SOC_MAINBOARD_SUPPORT_H_ +#define _SOC_MAINBOARD_SUPPORT_H_ + +#include <fsp/util.h> + +bool mainboard_supports_usb4(void); + +#endif + + diff --git a/src/soc/intel/tigerlake/mainboard_weak_support.c b/src/soc/intel/tigerlake/mainboard_weak_support.c new file mode 100644 index 0000000..ecf22c34 --- /dev/null +++ b/src/soc/intel/tigerlake/mainboard_weak_support.c @@ -0,0 +1,9 @@ +#include <console/console.h> +#include <soc/mainboard_support.h> + +bool __weak mainboard_supports_usb4(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return false; +} + diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index dc9caee..f2b9649 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -9,6 +9,7 @@ #include <intelblocks/mp_init.h> #include <soc/gpio_soc_defs.h> #include <soc/iomap.h> +#include <soc/mainboard_support.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/romstage.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbe743f917bf0a6899fe4587db8a2ddd60715c88 Gerrit-Change-Number: 45945 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/Makefile.inc: fail build when SPD would be empty
by Furquan Shaikh (Code Review) 02 Oct '20

02 Oct '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45131 ) Change subject: lib/Makefile.inc: fail build when SPD would be empty ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/45131/14/src/lib/Makefile.inc File src/lib/Makefile.inc: https://review.coreboot.org/c/coreboot/+/45131/14/src/lib/Makefile.inc@360 PS14, Line 360: test -n "$(SPD_SOURCES)" || \ : (echo "HAVE_SPD_BIN_IN_CBFS is set but SPD_SOURCES is empty" && exit 1) In my opinion, we should allow a board to have empty SPD_SOURCES even when HAVE_SPD_IN_CBFS is set. This is very useful for variants of a board which start out with minimal changes (or use templates to add the initial support) and follow up with more variant-specific changes to enable other bits. What we really want to ensure here is that we don't accidentally drop SPD ROM data if SPD_SOURCES is not empty. Thus it should be left upto the mainboard/variant to control when it is ready to add the SPD files. Thoughts? -- To view, visit https://review.coreboot.org/c/coreboot/+/45131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6db1dbe5fed5f242e408bcad4f36dda1b1fa1b4 Gerrit-Change-Number: 45131 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Oct 2020 01:14:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: /mainboard/intel/tglrvp/variants/tglrvp_up4 - Enable onboard HDMI and...
by Jason V Le (Code Review) 01 Oct '20

01 Oct '20

Jason V Le has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45016 ) Change subject: /mainboard/intel/tglrvp/variants/tglrvp_up4 - Enable onboard HDMI and type-C displays for UP4 ...................................................................... /mainboard/intel/tglrvp/variants/tglrvp_up4 - Enable onboard HDMI and type-C displays for UP4 - Enable DDC pins for DDI-B - Enable HPD pins for DDI-1/DDI-2 - Update MPHY/USB2 Mapping to match with the TGL-Y RVP schematic Test: tested hot-plug/unplug HDMI displays with onboard micro-hdmi connector and type-C connectors to make sure the displays get detected and enabled Change-Id: I08a1b16a8fa45cf0f366661395b9f2aa25c44935 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 1 file changed, 14 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/45016/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 928ae36..c2c6902 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -18,13 +18,13 @@ register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A port1 - register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 - register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 - register "usb3_ports[6]" = "USB3_PORT_EMPTY" # Not used - register "usb3_ports[7]" = "USB3_PORT_EMPTY" # Not used - register "usb3_ports[8]" = "USB3_PORT_EMPTY" # Not used + register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 / MECC + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not used + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Not used + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Not used register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 @@ -66,9 +66,16 @@ # enabling EDP in PortA register "DdiPortAConfig" = "1" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "0" register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + register "DdiPortCHpd" = "0" + register "DdiPortCDdc" = "0" register "DdiPort1Hpd" = "1" - register "DdiPort1Ddc" = "1" + register "DdiPort1Ddc" = "0" + register "DdiPort2Hpd" = "1" + register "DdiPort2Ddc" = "0" register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/45016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08a1b16a8fa45cf0f366661395b9f2aa25c44935 Gerrit-Change-Number: 45016 Gerrit-PatchSet: 1 Gerrit-Owner: Jason V Le <jason.v.le(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/cpx_sp: Add DIMM present field and max memory spe...
by Angel Pons (Code Review) 01 Oct '20

01 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45797 ) Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Add DIMM present field and max memory speed function ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/45797/4/src/vendorcode/intel/fsp/f… File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/memory.h: https://review.coreboot.org/c/coreboot/+/45797/4/src/vendorcode/intel/fsp/f… PS4, Line 47: uint16_t get_max_memory_speed(uint32_t commonTck) > It is a simple function, so it is defined inside a header file. It is large, though. I'd move it into its own .c file to avoid having multiple copies in the same binary -- To view, visit https://review.coreboot.org/c/coreboot/+/45797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928 Gerrit-Change-Number: 45797 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Isaac W Oram <isaac.w.oram(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 01 Oct 2020 22:18:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit October 2020