coreboot-gerrit October 2020

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Change in coreboot[master]: [WIP] mb/acer: Add Acer Aspire ES1-572
by Angel Pons (Code Review) 01 Oct '20

01 Oct '20

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Change in coreboot[master]: [WIP] mb/acer: Add Acer Aspire ES1-572
by Michael Niewöhner (Code Review) 01 Oct '20

01 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mb/acer: Add Acer Aspire ES1-572 ...................................................................... Patch Set 7: (6 comments) https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… PS5, Line 223: register "SendVrMbxCmd" = "2" I never found documentation on that PS4 exit issue; how did you verify this isn't required here? https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 37: register "SataTestMode" = "1" huh? why is test mode on? https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 40: register "SataPortsDevSlp[0]" = "0" : register "SataPortsDevSlp[1]" = "0" : drop disabled options - or enable devsleep cap if the board supports it (haven't checked the schematics, yet) https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 86: register "usb2_ports[3]" = "USB2_PORT_EMPTY" # N/C not required anymore; drop; see CB:45106 https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 93: register "usb3_ports[1]" = "USB3_PORT_EMPTY" # N/C : register "usb3_ports[2]" = "USB3_PORT_EMPTY" # N/C : register "usb3_ports[3]" = "USB3_PORT_EMPTY" # N/C : not required anymore; drop them; see CB:45106 https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572… PS7, Line 108: device pci 04.0 off end # CPU Thermal Subsystem why off? -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Oct 2020 17:42:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: Fill SSDT table with information about USB ports
by Felix Singer (Code Review) 01 Oct '20

01 Oct '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45885 ) Change subject: mb/clevo/l140cu: Fill SSDT table with information about USB ports ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I414d02cc9c16ed23ce12cba79bfd68e0e6486129 Gerrit-Change-Number: 45885 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Oct 2020 17:35:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/acer: Add Acer Aspire ES1-572
by Angel Pons (Code Review) 01 Oct '20

01 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mb/acer: Add Acer Aspire ES1-572 ...................................................................... Patch Set 6: (18 comments) This change is ready for review. https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@12 PS5, Line 12: Tested and working: > that's the USB on M. […] Ack. Will test again alongside Wi-Fi. https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@19 PS5, Line 19: - Loading Linux with SeaBIOS and tianocore > booting linux with grub2 works fine, too Ack https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@20 PS5, Line 20: - Power button soldered onto the board's debug pads. > -> maybe add that to Documentation/mb/... Ack https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@21 PS5, Line 21: - UART 2 to get yelled at > -> maybe add info on how to access that + resistor names to Documentation/mb/... Ack https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@24 PS5, Line 24: Not working or need testing: > Might be due to something weird w.r.t. […] I had problems at some point. No idea why. https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@25 PS5, Line 25: - Wi-Fi card. Probably fixed with correct PCIe settings. > working perfectly with iwlwifi and firmware-iwlwifi installed on debian Ack. I had problems so I'll re-test it when I find the M.2 card. https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@29 PS5, Line 29: - Internal eDP LCD. I think I have the cable somewhere. > ... […] Ack https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@30 PS5, Line 30: - Lid. It was brutally damaged, even though the LCD managed to survive. > nope, it's connected to the EC Ack https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@31 PS5, Line 31: - Battery. I have it somewhere. > oh nice! unfortunately I have zero knowlege of ACPI \o/ I will check that as soon as I have some tim […] I'm cleaning up comments on older patchsets. I still have a [WIP] in the commit message because EC support is null https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@32 PS5, Line 32: Keyboard > I had grub running and typed some text and numbers; arrows are fine; dunno: windows key, context me […] Ack https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@33 PS5, Line 33: . > I placed them for consistency with other entries with multiple sentences. Ack https://review.coreboot.org/c/coreboot/+/38978/5//COMMIT_MSG@33 PS5, Line 33: Card reader > works fine Ack https://review.coreboot.org/c/coreboot/+/38978/5/acer_a_thing.defconfig File acer_a_thing.defconfig: https://review.coreboot.org/c/coreboot/+/38978/5/acer_a_thing.defconfig@2 PS5, Line 2: CONFIG_VENDOR_ACER=y > Oh, I'm still carrying this over? I don't need it anymore Gone. https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/Makefile.inc: https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… PS5, Line 16: ramstage-y += ramstage.c > The filename would then be less descriptive. Also, see CB:41106. Did not https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… PS5, Line 17: ramstage-y += hda_verb.c > Only when CONFIG_AZALIA_PLUGIN_SUPPORT=y. […] HDA has no verbs yet https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/4/src/mainboard/acer/es1-572… PS4, Line 129: #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm | > Since we can assume that the NCP81208 supports PS3/4 the whole vr_config can be dropped as soon as c […] Gone. https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/devicetree.cb: https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… PS5, Line 113: PchSerialIoPci > I'll try to use SkipInit and hope it works. […] SkipInit works. https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572… PS5, Line 266: device pci 1f.5 off end # PCH SPI > Off-topic, but presently, lpc_set_lock_enable in the common code locks BIOS write-enable=1. […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Oct 2020 16:06:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: treewide: stop using hexdumps for SPD files
by Angel Pons (Code Review) 01 Oct '20

01 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44775 ) Change subject: treewide: stop using hexdumps for SPD files ...................................................................... Patch Set 27: Code-Review-1 > Patch Set 27: Code-Review+1 > > > Patch Set 27: > > > > > I'd vote for not checking binaries into the coreboot source tree at all. Personally, I'd like to get rid of the vbt binaries and have a tool to compile them as well. My understanding was that there wasn't documentation for the VBT fields, but it seems that maybe this is no longer the case. [1] > > > > In general I agree, but it seems hard to get authoritative sources on the precise format, even for SPD dumps - that ought to be standardized but get repurposed in lots of "wonderful" ways by memory reference code. As far as we know, the "spec" to these files is the reference code, and that's not public. > > > > Some of the SPD tools we use on newer chipsets (for lp4x?) may come close to that. In which case: why ship hex dumps or binaries at all? > > > > > As far as vendors adding custom flags, I don't see how binary vs text solves any problem there. > > The transition here removes the hex-to-bin translation that's been fragile. Michael offers a patch that fixes things for him - that I'm relatively sure breaks building that part of the tree on other UNIX systems, since I vaguely remember having had these issues myself. My guess would be Solaris but it might be some odd BSD as well. > > > > The text files we ship are plain hex dumps. They don't add anything of value, do they? So why should we pretend that they're "source" and make our live miserable? > > > > My proposal is to get this in to remove the pain point that this is dealing with (the fragile hex-to-bin translation) and whoever is motivated to do so looks into providing a higher level description for these files and translating things to that, removing the opaque datasets we have (no matter the format) from the tree. > > spd_tools was already updated to output binary SPD files, so now spd_tools is not usable for adding parts until this change goes in. So this is a 2nd vote for getting this in as is to unblock spd_tools. > > spd_tools generates SPD binaries from a json input. This could certainly be made part of the build so the generated SPD binaries do not need to be checked in. The only blocker is golang support in the build or rewriting the tool in a supported language. Why not revert the change that made spd_tools output binaries instead? I'm not convinced using binaries would help with the issue at hand. -- To view, visit https://review.coreboot.org/c/coreboot/+/44775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f24183a872924cddcfdf7587cc0c126da900f91 Gerrit-Change-Number: 44775 Gerrit-PatchSet: 27 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 01 Oct 2020 08:53:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Override smbios_fill_dimm_locator for type 17
by Angel Pons (Code Review) 01 Oct '20

01 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45799 ) Change subject: mb/ocp/deltalake: Override smbios_fill_dimm_locator for type 17 ...................................................................... Patch Set 5: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/45799/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45799/5//COMMIT_MSG@10 PS5, Line 10: Also remove CONFIG(GENERATE_SMBIOS_TABLES) compile option because SMBIOS : is always enabled and it makes the code cleaner. Another approach is to move all SMBIOS stuff into a `smbios.c` file 😊 https://review.coreboot.org/c/coreboot/+/45799/5/src/mainboard/ocp/deltalak… File src/mainboard/ocp/deltalake/ramstage.c: https://review.coreboot.org/c/coreboot/+/45799/5/src/mainboard/ocp/deltalak… PS5, Line 246: dimm_locator[dimm->channel_num] I would just do: 'A' + dimm->channel_num -- To view, visit https://review.coreboot.org/c/coreboot/+/45799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84531f9ee8bc76d9529aa983bc13e64f40c93138 Gerrit-Change-Number: 45799 Gerrit-PatchSet: 5 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 01 Oct 2020 08:20:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Expand WP_RO region to 8MB in fmap
by Caveh Jalali (Code Review) 01 Oct '20

01 Oct '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45889 ) Change subject: mb/google/volteer: Expand WP_RO region to 8MB in fmap ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/45889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72fe8b6a1f91390c218230c0c20825769ebd1e0b Gerrit-Change-Number: 45889 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Oct 2020 07:07:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Make use of ITSS common block [WIP]
by Subrata Banik (Code Review) 01 Oct '20

01 Oct '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45888 ) Change subject: soc/intel/xeon_sp: Make use of ITSS common block [WIP] ...................................................................... soc/intel/xeon_sp: Make use of ITSS common block [WIP] This patch ensures to have xeon SoC can use common functions from block/itss. This patch is needed to make use of ITSS common code. Change-Id: I612fdbc8e2ae993de47656002d87b6c4d4f3affd Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/xeon_sp/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/45888/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 3b18741..25603b5 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -41,6 +41,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU + select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_LPC select SOC_INTEL_COMMON_BLOCK_RTC -- To view, visit https://review.coreboot.org/c/coreboot/+/45888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I612fdbc8e2ae993de47656002d87b6c4d4f3affd Gerrit-Change-Number: 45888 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: acpi: Support MSDM table signature as SLIC
by Matt DeVillier (Code Review) 01 Oct '20

01 Oct '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44995 ) Change subject: acpi: Support MSDM table signature as SLIC ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3a1374c8a4880111a30662823c3be99008eedd3 Gerrit-Change-Number: 44995 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 01 Oct 2020 01:47:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vc/amd/fsp/picasso: Add bitfields for PSP info in transfer block
by Martin Roth (Code Review) 01 Oct '20

01 Oct '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45804 ) Change subject: vc/amd/fsp/picasso: Add bitfields for PSP info in transfer block ...................................................................... vc/amd/fsp/picasso: Add bitfields for PSP info in transfer block BUG=b:168895748 TEST=None BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I299fdd0f007f7e4a8f597931a52f68dc98acc9ac --- M src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/45804/1 diff --git a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h index 69ada34..684929d 100644 --- a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h @@ -54,6 +54,10 @@ #define SVC_SHA 0x46 #define SVC_RSAPKCS_VERIFY 0x47 +#define PSP_INFO_PRODUCTION_MODE 0x00000001UL +#define PSP_INFO_PRODUCTION_SI 0x00000002UL +#define PSP_INFO_VALID 0x80000000UL + typedef struct _RSAPSS_VERIFY_PARAMS_T { char *pHash; // Message digest to verify the RSA signature -- To view, visit https://review.coreboot.org/c/coreboot/+/45804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I299fdd0f007f7e4a8f597931a52f68dc98acc9ac Gerrit-Change-Number: 45804 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020