coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/cpx_sp: Add DIMM present field and max memory spe...
by Angel Pons (Code Review) 02 Oct '20

02 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45797 ) Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Add DIMM present field and max memory speed function ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/45797/4/src/vendorcode/intel/fsp/f… File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/memory.h: https://review.coreboot.org/c/coreboot/+/45797/4/src/vendorcode/intel/fsp/f… PS4, Line 47: uint16_t get_max_memory_speed(uint32_t commonTck) > It is a simple function, so it is defined inside a header file. It is large, though. I'd move it into its own .c file to avoid having multiple copies in the same binary -- To view, visit https://review.coreboot.org/c/coreboot/+/45797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928 Gerrit-Change-Number: 45797 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Isaac W Oram <isaac.w.oram(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 01 Oct 2020 22:18:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Expand WP_RO region to 8MB in fmap
by Tim Wawrzynczak (Code Review) 02 Oct '20

02 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45889 ) Change subject: mb/google/volteer: Expand WP_RO region to 8MB in fmap ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/45889/2/src/mainboard/google/volte… File src/mainboard/google/volteer/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/45889/2/src/mainboard/google/volte… PS2, Line 9: # SPI flash only the top 16MiB actually gets memory mapped. > +Furquan for details, but I believe you cannot do this due to the issue described in this comment. […] That is correct, x86 only memory maps the top 16 MiB of SPI flash, so in this case RW_SECTION_A ends up at 0x1000000 (16 MiB) up from the bottom of flash, so aligns at the 16MiB boundary and all FW will be memory mapped. Somehow all of the FW has to live up beyond that boundary. I think removing 2MB from each FW_MAIN may work, as we are only using ~1.6MiB from each section, out of the ~5.8. However, that puts us perilously close to not being able to fit a cse lite update in the FW_MAIN regions... -- To view, visit https://review.coreboot.org/c/coreboot/+/45889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72fe8b6a1f91390c218230c0c20825769ebd1e0b Gerrit-Change-Number: 45889 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Oct 2020 22:10:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/cpx_sp: Add DIMM present field and max memory spe...
by Jonathan Zhang (Code Review) 02 Oct '20

02 Oct '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45797 ) Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Add DIMM present field and max memory speed function ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/45797/4/src/vendorcode/intel/fsp/f… File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/memory.h: https://review.coreboot.org/c/coreboot/+/45797/4/src/vendorcode/intel/fsp/f… PS4, Line 47: uint16_t get_max_memory_speed(uint32_t commonTck) > Why is this defined inside the header? It is a simple function, so it is defined inside a header file. -- To view, visit https://review.coreboot.org/c/coreboot/+/45797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928 Gerrit-Change-Number: 45797 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Isaac W Oram <isaac.w.oram(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 01 Oct 2020 22:05:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers: sn65dsi86: Retry link training up to 5 times
by Julius Werner (Code Review) 01 Oct '20

01 Oct '20

Hello Douglas Anderson, Philip Chen, mturney mturney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45882 to review the following change. Change subject: drivers: sn65dsi86: Retry link training up to 5 times ...................................................................... drivers: sn65dsi86: Retry link training up to 5 times The kernel guys have found that automatic link training from this bridge can occasionally fail and needs to be retried. They think 5 retries should be enough but have added up to 10 to be sure. Let's do the same, but since things are synchronous for us and every try takes 500ms, maybe better restrict it to 5. BUG=b:169535092 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I713b6851bd51d3527ed4c6e6407dee6b42d09955 --- M src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c 1 file changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/45882/1 diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c index e0058c4..91e64aa 100644 --- a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c +++ b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c @@ -415,15 +415,18 @@ sn65dsi86_bridge_dpcd_request(bus, chip, DP_BRIDGE_CONFIGURATION_SET, 1, DPCD_WRITE, &buf); - /* semi auto link training mode */ - i2c_writeb(bus, chip, SN_ML_TX_MODE_REG, 0xa); + int i; /* Kernel driver suggests to retry this a few times if it fails. */ + for (i = 0; i < 5; i++) { + i2c_writeb(bus, chip, SN_ML_TX_MODE_REG, SEMI_AUTO_LINK_TRAINING); - if (!wait_ms(500, - !(i2c_readb(bus, chip, SN_ML_TX_MODE_REG, &buf)) && - (buf & NORMAL_MODE))) { - printk(BIOS_ERR, "ERROR: Link training failed"); + wait_ms(500, !(i2c_readb(bus, chip, SN_ML_TX_MODE_REG, &buf)) && + (buf == NORMAL_MODE || buf == MAIN_LINK_OFF)) + + if (buf == NORMAL_MODE) + return; } + printk(BIOS_ERR, "ERROR: Link training failed 5 times\n"); } static enum cb_err sn65dsi86_bridge_get_plug_in_status(uint8_t bus, uint8_t chip) -- To view, visit https://review.coreboot.org/c/coreboot/+/45882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I713b6851bd51d3527ed4c6e6407dee6b42d09955 Gerrit-Change-Number: 45882 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Douglas Anderson <dianders(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Expand WP_RO region to 8MB in fmap
by Julius Werner (Code Review) 01 Oct '20

01 Oct '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45889 ) Change subject: mb/google/volteer: Expand WP_RO region to 8MB in fmap ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/45889/2/src/mainboard/google/volte… File src/mainboard/google/volteer/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/45889/2/src/mainboard/google/volte… PS2, Line 9: # SPI flash only the top 16MiB actually gets memory mapped. +Furquan for details, but I believe you cannot do this due to the issue described in this comment. RW_SECTIONs need to stay below 16MB. Would it be an option to reduce the RW_SECTION sizes by 2MB each instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/45889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72fe8b6a1f91390c218230c0c20825769ebd1e0b Gerrit-Change-Number: 45889 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Oct 2020 21:47:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Expand WP_RO region to 8MB in fmap
by Caveh Jalali (Code Review) 01 Oct '20

01 Oct '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45889 ) Change subject: mb/google/volteer: Expand WP_RO region to 8MB in fmap ...................................................................... Patch Set 2: > Patch Set 2: > > 4 more MiB?? oh my... is that really the lowest resolution we can get away with? FHD support apparently adds 4.5MiB and UHD would add 9.5MiB. i see some other boards already increased WP_RO to 8MiB, so this is in line with those changes. current rendering resolution for volteer specified in boards.yaml is 1200x675. to put things into perspective, we can no longer build coreboot with USB_DEBUG enabled in all the USB drivers due to the space crunch, so getting some headroom back is a P0 to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/45889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72fe8b6a1f91390c218230c0c20825769ebd1e0b Gerrit-Change-Number: 45889 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 01 Oct 2020 21:28:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/acer: Add Acer Aspire ES1-572
by build bot (Jenkins) (Code Review) 01 Oct '20

01 Oct '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 ) Change subject: [WIP] mb/acer: Add Acer Aspire ES1-572 ...................................................................... Patch Set 9: (2 comments) https://review.coreboot.org/c/coreboot/+/38978/9/src/mainboard/acer/es1-572… File src/mainboard/acer/es1-572/romstage.c: https://review.coreboot.org/c/coreboot/+/38978/9/src/mainboard/acer/es1-572… PS9, Line 22: FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV) https://review.coreboot.org/c/coreboot/+/38978/9/src/mainboard/acer/es1-572… PS9, Line 40: FSP_M_TEST_CONFIG *const test_cfg = &mupd->FspmTestConfig; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/38978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id98788a2c5e54f70fd1cacbd70d636f5e63b2619 Gerrit-Change-Number: 38978 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Oct 2020 21:18:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: treewide: stop using hexdumps for SPD files
by Rob Barnes (Code Review) 01 Oct '20

01 Oct '20

Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44775 ) Change subject: treewide: stop using hexdumps for SPD files ...................................................................... Patch Set 27: > Patch Set 27: Code-Review-1 > > > Patch Set 27: Code-Review+1 > > > > > Patch Set 27: > > > > > > > I'd vote for not checking binaries into the coreboot source tree at all. Personally, I'd like to get rid of the vbt binaries and have a tool to compile them as well. My understanding was that there wasn't documentation for the VBT fields, but it seems that maybe this is no longer the case. [1] > > > > > > In general I agree, but it seems hard to get authoritative sources on the precise format, even for SPD dumps - that ought to be standardized but get repurposed in lots of "wonderful" ways by memory reference code. As far as we know, the "spec" to these files is the reference code, and that's not public. > > > > > > Some of the SPD tools we use on newer chipsets (for lp4x?) may come close to that. In which case: why ship hex dumps or binaries at all? > > > > > > > As far as vendors adding custom flags, I don't see how binary vs text solves any problem there. > > > The transition here removes the hex-to-bin translation that's been fragile. Michael offers a patch that fixes things for him - that I'm relatively sure breaks building that part of the tree on other UNIX systems, since I vaguely remember having had these issues myself. My guess would be Solaris but it might be some odd BSD as well. > > > > > > The text files we ship are plain hex dumps. They don't add anything of value, do they? So why should we pretend that they're "source" and make our live miserable? > > > > > > My proposal is to get this in to remove the pain point that this is dealing with (the fragile hex-to-bin translation) and whoever is motivated to do so looks into providing a higher level description for these files and translating things to that, removing the opaque datasets we have (no matter the format) from the tree. > > > > spd_tools was already updated to output binary SPD files, so now spd_tools is not usable for adding parts until this change goes in. So this is a 2nd vote for getting this in as is to unblock spd_tools. > > > > spd_tools generates SPD binaries from a json input. This could certainly be made part of the build so the generated SPD binaries do not need to be checked in. The only blocker is golang support in the build or rewriting the tool in a supported language. > > Why not revert the change that made spd_tools output binaries instead? I'm not convinced using binaries would help with the issue at hand. So revert or patch spd_tools to support both hex and binary with a commandline flag. Michael, do you have a preference? -- To view, visit https://review.coreboot.org/c/coreboot/+/44775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f24183a872924cddcfdf7587cc0c126da900f91 Gerrit-Change-Number: 44775 Gerrit-PatchSet: 27 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 01 Oct 2020 20:53:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/cpx_sp: Add DIMM present field and max memory spe...
by Angel Pons (Code Review) 01 Oct '20

01 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45797 ) Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Add DIMM present field and max memory speed function ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/45797/4/src/vendorcode/intel/fsp/f… File src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/memory.h: https://review.coreboot.org/c/coreboot/+/45797/4/src/vendorcode/intel/fsp/f… PS4, Line 47: uint16_t get_max_memory_speed(uint32_t commonTck) Why is this defined inside the header? -- To view, visit https://review.coreboot.org/c/coreboot/+/45797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I988e7341ddd3b701c698b41451a87890f21cc928 Gerrit-Change-Number: 45797 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Isaac W Oram <isaac.w.oram(a)intel.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 01 Oct 2020 20:46:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
by Angel Pons (Code Review) 01 Oct '20

01 Oct '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45798 ) Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17 ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/… File src/soc/intel/xeon_sp/cpx/romstage.c: https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/… PS4, Line 79: 0x1a Why hardcode? actKeyByte2 might work. https://review.coreboot.org/c/coreboot/+/45798/4/src/soc/intel/xeon_sp/cpx/… PS4, Line 88: 1200 Looks like FSP might store this in the SystemMemoryMapHob struct but headers expose it as reserved. -- To view, visit https://review.coreboot.org/c/coreboot/+/45798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb72d18027d972140828970206834ff55b72022 Gerrit-Change-Number: 45798 Gerrit-PatchSet: 4 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: John Looney <john.looney(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 01 Oct 2020 20:44:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2020