coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3473 discussions

Change in coreboot[master]: soc/intel: deduplicate ACPI timer emulation
by Nico Huber (Code Review) 13 Oct '20

13 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45951 ) Change subject: soc/intel: deduplicate ACPI timer emulation ...................................................................... Patch Set 17: Code-Review+1 (3 comments) https://review.coreboot.org/c/coreboot/+/45951/17/src/soc/intel/alderlake/c… File src/soc/intel/alderlake/cpu.c: https://review.coreboot.org/c/coreboot/+/45951/17/src/soc/intel/alderlake/c… PS17, Line 148: if ACPI PM timer is disabled Will need in update if we decide to drop the condition. https://review.coreboot.org/c/coreboot/+/45951/17/src/soc/intel/apollolake/… File src/soc/intel/apollolake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/45951/17/src/soc/intel/apollolake/… PS17, Line 13: ../../soc/intel/ How about removing a bit of the rendundant path? :) https://review.coreboot.org/c/coreboot/+/45951/17/src/soc/intel/common/bloc… File src/soc/intel/common/block/cpu/pm_timer_emulation.c: https://review.coreboot.org/c/coreboot/+/45951/17/src/soc/intel/common/bloc… PS17, Line 26: msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | Not all versions set this value, are we sure about it? -- To view, visit https://review.coreboot.org/c/coreboot/+/45951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793 Gerrit-Change-Number: 45951 Gerrit-PatchSet: 17 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 13 Oct 2020 20:57:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/poppy/variant/atlas: Reset bluetooth on boot
by Tim Wawrzynczak (Code Review) 13 Oct '20

13 Oct '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46120 ) Change subject: mb/google/poppy/variant/atlas: Reset bluetooth on boot ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/46120/2/src/mainboard/google/poppy… File src/mainboard/google/poppy/variants/atlas/gpio.c: https://review.coreboot.org/c/coreboot/+/46120/2/src/mainboard/google/poppy… PS2, Line 335: early_gpio_table > no, just rw. Then this won't take effect. The early GPIO table is programmed in bootblock. -- To view, visit https://review.coreboot.org/c/coreboot/+/46120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I361caa49e82aa086c3c35962164fb078fa30139e Gerrit-Change-Number: 46120 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 13 Oct 2020 20:55:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: convert XTAL frequency constant to Kconfig
by Nico Huber (Code Review) 13 Oct '20

13 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46018 ) Change subject: soc/intel: convert XTAL frequency constant to Kconfig ...................................................................... Patch Set 10: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/46018/10/src/soc/intel/common/bloc… File src/soc/intel/common/block/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/46018/10/src/soc/intel/common/bloc… PS10, Line 102: config SOC_INTEL_COMMON_BLOCK_XTAL_CLOCK_HZ It reads a bit odd. It's about the CPU block, but you omit `CPU`. So maybe also remove the `COMMON_BLOCK_`? -- To view, visit https://review.coreboot.org/c/coreboot/+/46018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18 Gerrit-Change-Number: 46018 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 20:53:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/poppy/variant/atlas: Reset bluetooth on boot
by Caveh Jalali (Code Review) 13 Oct '20

13 Oct '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46120 ) Change subject: mb/google/poppy/variant/atlas: Reset bluetooth on boot ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/46120/2/src/mainboard/google/poppy… File src/mainboard/google/poppy/variants/atlas/gpio.c: https://review.coreboot.org/c/coreboot/+/46120/2/src/mainboard/google/poppy… PS2, Line 335: early_gpio_table > Are you planning to requal a new RO for this change? no, just rw. -- To view, visit https://review.coreboot.org/c/coreboot/+/46120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I361caa49e82aa086c3c35962164fb078fa30139e Gerrit-Change-Number: 46120 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 13 Oct 2020 20:52:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common: add Kconfig for PM Timer emulation support
by Nico Huber (Code Review) 13 Oct '20

13 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46017 ) Change subject: soc/intel/common: add Kconfig for PM Timer emulation support ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff Gerrit-Change-Number: 46017 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 20:47:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [WIP] soc/intel/skylake: Support NHLT 1ch DMIC
by Benjamin Doron (Code Review) 13 Oct '20

13 Oct '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43072 to look at the new patch set (#7). Change subject: [WIP] soc/intel/skylake: Support NHLT 1ch DMIC ...................................................................... [WIP] soc/intel/skylake: Support NHLT 1ch DMIC Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/nhlt/Makefile.inc M src/soc/intel/skylake/nhlt/dmic.c 5 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/43072/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/43072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Gerrit-Change-Number: 43072 Gerrit-PatchSet: 7 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skylake: Rename PcieRpAspm devicetree config
by Benjamin Doron (Code Review) 13 Oct '20

13 Oct '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45001 ) Change subject: soc/intel/skylake: Rename PcieRpAspm devicetree config ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/45001/3/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.h: https://review.coreboot.org/c/coreboot/+/45001/3/src/soc/intel/skylake/chip… PS3, Line 265: } pcierp_aspm[CONFIG_MAX_ROOT_PORTS]; > This should be named `pcie_rp_aspm` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Gerrit-Change-Number: 45001 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 20:26:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Rename PcieRpAspm devicetree config
by Benjamin Doron (Code Review) 13 Oct '20

13 Oct '20

Hello build bot (Jenkins), Nico Huber, Frans Hendriks, Angel Pons, Patrick Rudolph, Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45001 to look at the new patch set (#4). Change subject: soc/intel/skylake: Rename PcieRpAspm devicetree config ...................................................................... soc/intel/skylake: Rename PcieRpAspm devicetree config This configuration option shares a name with the FSP UPD, but is enumerated differently. Change its name to minimise confusion about the options. Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/mainboard/facebook/monolith/devicetree.cb M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 3 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/45001/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/45001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Gerrit-Change-Number: 45001 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports
by Benjamin Doron (Code Review) 13 Oct '20

13 Oct '20

Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39538 to look at the new patch set (#27). Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports ...................................................................... soc/intel/skylake: Configure L1 substates for PCH root ports Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration. Tested on an Acer Aspire VN7-572G (Skylake-U). Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 27 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: [WIP] skl: PEG for Optimus
by Benjamin Doron (Code Review) 13 Oct '20

13 Oct '20

Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40625 to look at the new patch set (#12). Change subject: [WIP] skl: PEG for Optimus ...................................................................... [WIP] skl: PEG for Optimus Creates PEG ACPI device for Optimus. Bugs: - "Data Link Layer Link Active not set in 1000ms" Tested, nouveau driver works on an Acer Aspire VN7-572G (Skylake-U) and `DRI_PRIME=1 glxinfo` reports the dGPU as renderer. Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/acpi/pch.asl A src/soc/intel/skylake/acpi/peg.asl 2 files changed, 238 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/40625/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/40625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Gerrit-Change-Number: 40625 Gerrit-PatchSet: 12 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020