Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46299 )
Change subject: vendorcode/google/dram_part_num: Fix the severity of debug statement
......................................................................
vendorcode/google/dram_part_num: Fix the severity of debug statement
DRAM part number may not be provisioned in CBI during early stages of
development. Logging the debug statement with error severity interferes
with some of the test tools. Update the severity of the debug statement
to just DEBUG severity
BUG=b:170529094
TEST=Build and boot to ChromeOS in Drawlat.
Change-Id: Ib0c707ec6478060d6e18ea01cc467dfda00a6d42
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/vendorcode/google/chromeos/dram_part_num_override.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/46299/1
diff --git a/src/vendorcode/google/chromeos/dram_part_num_override.c b/src/vendorcode/google/chromeos/dram_part_num_override.c
index d624e13..4b934fe 100644
--- a/src/vendorcode/google/chromeos/dram_part_num_override.c
+++ b/src/vendorcode/google/chromeos/dram_part_num_override.c
@@ -16,8 +16,8 @@
if (part_num_state == PART_NUM_NOT_READ) {
if (google_chromeec_cbi_get_dram_part_num(part_num_store,
sizeof(part_num_store)) < 0) {
- printk(BIOS_ERR,
- "ERROR: Couldn't obtain DRAM part number from CBI\n");
+ printk(BIOS_DEBUG,
+ "Couldn't obtain DRAM part number from CBI\n");
part_num_state = PART_NUM_NOT_IN_CBI;
} else {
part_num_state = PART_NUM_AVAILABLE;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib0c707ec6478060d6e18ea01cc467dfda00a6d42
Gerrit-Change-Number: 46299
Gerrit-PatchSet: 1
Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-MessageType: newchange
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46272 )
Change subject: soc/intel/skl + cpu/intel/common: move AES-NI locking to common cpu code
......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46272/4/src/include/cpu/intel/msr.h
File src/include/cpu/intel/msr.h:
https://review.coreboot.org/c/coreboot/+/46272/4/src/include/cpu/intel/msr.…
PS4, Line 8: #define MSR_FEATURE_CONFIG 0x13c
> did you mean "the other header[s]"? […]
I meant the one that is close to this change and was used in the moved
code `src/soc/intel/common/block/include/intelblocks/msr.h`.
Not a requirement, though.
https://review.coreboot.org/c/coreboot/+/46272/4/src/include/cpu/intel/msr.…
PS4, Line 9: #define AESNI_LOCK_BIT 0
> Hmm, indeed it's only used a few times in cpu/intel and once in soc/intel. […]
I would replace msr_set_bit() with _unset and _set versions like we have
them for other registers like CB:42134.
--
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Gerrit-Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e
Gerrit-Change-Number: 46272
Gerrit-PatchSet: 4
Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
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Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46039 )
Change subject: wifi: Move addition of CBFS SAR file to wifi/generic/Makefile.inc
......................................................................
wifi: Move addition of CBFS SAR file to wifi/generic/Makefile.inc
This change moves the addition of CBFS SAR file from
intel/wifi/Makefile.inc to wifi/generic/Makefile.inc to keep it in the
same sub-directory as the Kconfig definition.
BUG=b:169802515
BRANCH=zork
Change-Id: I7ee33232b6a07bbf929f3a79fabe89130fb6fa6f
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/drivers/intel/wifi/Makefile.inc
M src/drivers/wifi/generic/Makefile.inc
2 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/46039/1
diff --git a/src/drivers/intel/wifi/Makefile.inc b/src/drivers/intel/wifi/Makefile.inc
index 57f60af..9bfdd79 100644
--- a/src/drivers/intel/wifi/Makefile.inc
+++ b/src/drivers/intel/wifi/Makefile.inc
@@ -1,7 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
ramstage-$(CONFIG_DRIVERS_INTEL_WIFI) += wifi.c
-
-cbfs-files-$(CONFIG_WIFI_SAR_CBFS) += wifi_sar_defaults.hex
-wifi_sar_defaults.hex-file := $(call strip_quotes,$(CONFIG_WIFI_SAR_CBFS_FILEPATH))
-wifi_sar_defaults.hex-type := raw
diff --git a/src/drivers/wifi/generic/Makefile.inc b/src/drivers/wifi/generic/Makefile.inc
index 6240c71..407041a 100644
--- a/src/drivers/wifi/generic/Makefile.inc
+++ b/src/drivers/wifi/generic/Makefile.inc
@@ -1 +1,5 @@
ramstage-$(CONFIG_DRIVERS_WIFI_GENERIC) += generic.c
+
+cbfs-files-$(CONFIG_WIFI_SAR_CBFS) += wifi_sar_defaults.hex
+wifi_sar_defaults.hex-file := $(call strip_quotes,$(CONFIG_WIFI_SAR_CBFS_FILEPATH))
+wifi_sar_defaults.hex-type := raw
--
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Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33640 )
Change subject: superio/nuvoton/nct6791d: Add symbol to select COM port
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Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33640/1/src/superio/nuvoton/common…
File src/superio/nuvoton/common/early_serial.c:
https://review.coreboot.org/c/coreboot/+/33640/1/src/superio/nuvoton/common…
PS1, Line 74: pnp_write_config(dev, 0x2a, 0x00);
> yeah, it probably shouldn't matter too much here. […]
Oh, past me, how mistaken you were...
--
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