coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries
by Nico Huber (Code Review) 13 Oct '20

13 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45536 ) Change subject: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/45536/10/src/soc/intel/alderlake/a… File src/soc/intel/alderlake/acpi.c: https://review.coreboot.org/c/coreboot/+/45536/10/src/soc/intel/alderlake/a… PS10, Line 162: generate_cppc_entries(core_id); Why jump through so many hoops here? soc calls generate_cpu_entries(), calls back here, calls back there. I guess the hardware involves the soc-specific config struct, but then again, why is it a devicetree config? -- To view, visit https://review.coreboot.org/c/coreboot/+/45536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Gerrit-Change-Number: 45536 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 16:11:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/acpi: add code for CPPC entries generation
by Nico Huber (Code Review) 13 Oct '20

13 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/common/block/acpi: add code for CPPC entries generation ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/c/coreboot/+/45535/8/src/soc/intel/common/block… File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/45535/8/src/soc/intel/common/block… PS8, Line 370: core Is this `virtual core` aka. thread? Otherwise it would seem that this is run twice per package in the HT case. If it's going to be the apic id, we could also name it like that. https://review.coreboot.org/c/coreboot/+/45535/8/src/soc/intel/common/block… PS8, Line 372: /* version 2 */ Is the comment really necessary? If you want to name arguments, you could pass a struct. -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 13 Oct 2020 15:54:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/icl: enable common CPU code
by Nico Huber (Code Review) 13 Oct '20

13 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45826 ) Change subject: soc/intel/icl: enable common CPU code ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/45826/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45826/5//COMMIT_MSG@13 PS5, Line 13: like done for SKL,ICL,... already. This isn't quite clear, IMHO. "like done for [...]ICL"? but this is ICL. I see that the config value is already used in code. That could be clearer. Also, there is another Kconfig prompt (locking) enabled by this which is not used, AFAICS. If that is the case, its prompt should be disabled. Either via another Kconfig (HAVE...LOCKING_OPTION?) or at least select it (prompt would show but can't be changed, which I assume is what the code does). -- To view, visit https://review.coreboot.org/c/coreboot/+/45826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb Gerrit-Change-Number: 45826 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 15:49:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/l140cu: add CMOS layout and defaults
by Michael Niewöhner (Code Review) 13 Oct '20

13 Oct '20

Hello Felix Singer, build bot (Jenkins), Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46311 to look at the new patch set (#4). Change subject: mb/clevo/l140cu: add CMOS layout and defaults ...................................................................... mb/clevo/l140cu: add CMOS layout and defaults Add CMOS layout and defaults files and enable CMOS options in Kconfig. Change-Id: Ia1a27818b2d12fb7578189e5748b8073c8f928e3 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/clevo/cml-u/Kconfig A src/mainboard/clevo/cml-u/cmos.default A src/mainboard/clevo/cml-u/cmos.layout 3 files changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46311/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/46311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1a27818b2d12fb7578189e5748b8073c8f928e3 Gerrit-Change-Number: 46311 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: rewrite and clarify the Legacy 8254 Timer Kconfig
by Nico Huber (Code Review) 13 Oct '20

13 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46302 ) Change subject: soc/intel/common: rewrite and clarify the Legacy 8254 Timer Kconfig ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46302 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9637c549db1ce29f259708f316852fc2ae9e7c38 Gerrit-Change-Number: 46302 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 15:14:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: drop default to enable the PIT if SeaBIOS is chosen
by Nico Huber (Code Review) 13 Oct '20

13 Oct '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46301 ) Change subject: soc/intel/common: drop default to enable the PIT if SeaBIOS is chosen ...................................................................... Patch Set 1: (1 comment) Do we really want this, though? I guess we should add a big fat warning that this might break any option rom. https://review.coreboot.org/c/coreboot/+/46301/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46301/1//COMMIT_MSG@11 PS1, Line 11: enable it by default anymore, when SeaBIOS gets enabled. Looking at its code, this doesn't seem fully true. I assume, I hope your tests can confirm, that it always uses the PM timer if advertised by coreboot. If that is true, please just mention that. -- To view, visit https://review.coreboot.org/c/coreboot/+/46301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd75800678707a92110682347c7cfb93e25109a4 Gerrit-Change-Number: 46301 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 15:12:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [test] asus/p2b
by HAOUAS Elyes (Code Review) 13 Oct '20

13 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46335 ) Change subject: [test] asus/p2b ...................................................................... [test] asus/p2b Change-Id: I8828dadcc05be30c131944b5f11460f1c0c9ebdc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asus/p2b/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/46335/1 diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 1d3d3b9..d73f7a8 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only + if BOARD_ASUS_P2B || BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS || BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS || BOARD_ASUS_P3B_F config BASE_ASUS_P2B_D -- To view, visit https://review.coreboot.org/c/coreboot/+/46335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8828dadcc05be30c131944b5f11460f1c0c9ebdc Gerrit-Change-Number: 46335 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: device: Rework bus master option
by Felix Singer (Code Review) 13 Oct '20

13 Oct '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45149 ) Change subject: device: Rework bus master option ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/45149/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45149/1//COMMIT_MSG@8 PS1, Line 8: > can I haz more text please? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33b37a79022007a16e97350db61575b63fa8256b Gerrit-Change-Number: 45149 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 13 Oct 2020 14:19:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: device: Enable bus mastering on "system" class devices conditionally
by Felix Singer (Code Review) 13 Oct '20

13 Oct '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45151 ) Change subject: device: Enable bus mastering on "system" class devices conditionally ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/45151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia04e83606a0a081c0758ec59e52627aa1dbd2622 Gerrit-Change-Number: 45151 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 13 Oct 2020 14:19:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device: Allow configuring bus mastering for PCI bridges conditionally
by Felix Singer (Code Review) 13 Oct '20

13 Oct '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45150 ) Change subject: device: Allow configuring bus mastering for PCI bridges conditionally ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/45150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7cacce28f473dda76ca203016dbb8e00149a990 Gerrit-Change-Number: 45150 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 13 Oct 2020 14:19:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit October 2020