coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: mb/asrock/h110m/romstage.c: Drop invalid SPD addresses
by Angel Pons (Code Review) 13 Oct '20

13 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46247 ) Change subject: mb/asrock/h110m/romstage.c: Drop invalid SPD addresses ...................................................................... mb/asrock/h110m/romstage.c: Drop invalid SPD addresses Pictures on the internet show that the Asrock H110M-DVS (Kconfig.name) only has two DIMM slots. Since the vendor's website advertises support for dual channel memory, drop the SPD addresses for the second slot of each channel. The result is the same as several other two-slot boards. Change-Id: I4b62e9196bfa3a688016399d7e025ca995f3c12c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/h110m/romstage.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/46247/1 diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c index 8e72e8e..ca3058f 100644 --- a/src/mainboard/asrock/h110m/romstage.c +++ b/src/mainboard/asrock/h110m/romstage.c @@ -15,7 +15,7 @@ FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; struct spd_block blk = { - .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + .addr_map = { 0x50, 0x52 }, }; assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); @@ -25,9 +25,7 @@ get_spd_smbus(&blk); mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; - mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; - mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; - mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; dump_spd_info(&blk); memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); -- To view, visit https://review.coreboot.org/c/coreboot/+/46247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b62e9196bfa3a688016399d7e025ca995f3c12c Gerrit-Change-Number: 46247 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/asrock/h110m/romstage.c: Correct FSP-M UPDs
by Angel Pons (Code Review) 13 Oct '20

13 Oct '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46246 ) Change subject: mb/asrock/h110m/romstage.c: Correct FSP-M UPDs ...................................................................... mb/asrock/h110m/romstage.c: Correct FSP-M UPDs The DQ and DQS byte maps do not apply to DDR4 configurations, and the RCOMP resistor and target values are not correct for SKL-S (or KBL-S). Drop the byte maps and use RCOMP values for the correct platform type. These can be found using Intel Document #573387 and the RCOMP resistor values for SKL-S have been confirmed by measuring them on an i5-6400. Change-Id: I699d46b9b516be8946367e6d9b24883ae1e78d03 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/h110m/romstage.c 1 file changed, 13 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/46246/1 diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c index 7a17915..8e72e8e 100644 --- a/src/mainboard/asrock/h110m/romstage.c +++ b/src/mainboard/asrock/h110m/romstage.c @@ -1,61 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <soc/romstage.h> +#include <stdint.h> #include <string.h> #include <spd_bin.h> -static void mainboard_fill_dq_map_data(void *dq_map_ch0, void *dq_map_ch1) -{ - /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, - 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); - memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); -} - -static void mainboard_fill_dqs_map_data(void *dqs_map_ch0, void *dqs_map_ch1) -{ - /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); - memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); -} - -static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 200, 81, 162 }; - memcpy(rcomp_ptr, RcompResistor, - sizeof(RcompResistor)); -} - -static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) -{ - /* Rcomp target */ - static const u16 RcompTarget[5] = { - 100, 40, 40, 23, 40 }; - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); -} - void mainboard_memory_init_params(FSPM_UPD *mupd) { - FSP_M_CONFIG *mem_cfg; + const u16 rcomp_resistors[3] = { 121, 75, 100 }; + + const u16 rcomp_targets[5] = { 50, 26, 20, 20, 26 }; + + FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig; + struct spd_block blk = { .addr_map = { 0x50, 0x51, 0x52, 0x53, }, }; - mem_cfg = &mupd->FspmConfig; - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, - &mem_cfg->DqByteMapCh1); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, - &mem_cfg->DqsMapCpu2DramCh1); - mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); - mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); mem_cfg->DqPinsInterleaved = 1; get_spd_smbus(&blk); @@ -66,6 +30,9 @@ mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; dump_spd_info(&blk); + memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); + memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); + /* use virtual channel 1 for the dmi interface of the PCH */ mupd->FspmTestConfig.DmiVc1 = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/46246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I699d46b9b516be8946367e6d9b24883ae1e78d03 Gerrit-Change-Number: 46246 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376
by Ronak Kanabar (Code Review) 13 Oct '20

13 Oct '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45899 ) Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376 ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/45899/5/src/vendorcode/intel/fsp/f… File src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h: https://review.coreboot.org/c/coreboot/+/45899/5/src/vendorcode/intel/fsp/f… PS5, Line 2715: Level 1 > I will try to check with FSP team regarding this. […] check this in TGL there is 2 level. Right now in JSL there is only one level. https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… -- To view, visit https://review.coreboot.org/c/coreboot/+/45899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65c03d8eda11664541479983c7be11854410e1c6 Gerrit-Change-Number: 45899 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 10:29:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/clevo/l140cu: add CMOS layout and defaults
by Michael Niewöhner (Code Review) 13 Oct '20

13 Oct '20

Hello Felix Singer, build bot (Jenkins), Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46311 to look at the new patch set (#3). Change subject: mb/clevo/l140cu: add CMOS layout and defaults ...................................................................... mb/clevo/l140cu: add CMOS layout and defaults Add CMOS layout and defaults files and enable CMOS options in Kconfig. Change-Id: Ia1a27818b2d12fb7578189e5748b8073c8f928e3 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/clevo/cml-u/Kconfig A src/mainboard/clevo/cml-u/variants/l140cu/cmos.default A src/mainboard/clevo/cml-u/variants/l140cu/cmos.layout 3 files changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46311/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/46311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1a27818b2d12fb7578189e5748b8073c8f928e3 Gerrit-Change-Number: 46311 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: drop duplicate PM ACPI ti...
by Michael Niewöhner (Code Review) 13 Oct '20

13 Oct '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45958 to look at the new patch set (#24). Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: drop duplicate PM ACPI timer disabling ...................................................................... [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: drop duplicate PM ACPI timer disabling FSP already disables the PM ACPI timer, when EnableTcoTimer=0, so there is no need to do it again in coreboot. Change-Id: I5594ac423d6dff4c3212d657c242137492dc5d2a Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/finalize.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/finalize.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/chip.h M src/soc/intel/icelake/finalize.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/finalize.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/finalize.c 17 files changed, 4 insertions(+), 107 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45958/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/45958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5594ac423d6dff4c3212d657c242137492dc5d2a Gerrit-Change-Number: 45958 Gerrit-PatchSet: 24 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries
by Michael Niewöhner (Code Review) 13 Oct '20

13 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45536 ) Change subject: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries ...................................................................... Patch Set 10: > Patch Set 9: > > Can you please add ADL too ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/45536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Gerrit-Change-Number: 45536 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 10:23:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries
by Michael Niewöhner (Code Review) 13 Oct '20

13 Oct '20

Hello Elyes HAOUAS, build bot (Jenkins), Nico Huber, Paul Menzel, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/45536 to look at the new patch set (#10). Change subject: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries ...................................................................... soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries Make use of the previously added common function for generating CPPC entries, when Intel SpeedShift is enabled. Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/alderlake/acpi.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/tigerlake/acpi.c 6 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/45536/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/45536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e Gerrit-Change-Number: 45536 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skl + cpu/intel/common: move AES-NI locking to common cpu code
by Michael Niewöhner (Code Review) 13 Oct '20

13 Oct '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46272 ) Change subject: soc/intel/skl + cpu/intel/common: move AES-NI locking to common cpu code ...................................................................... Patch Set 4: (3 comments) https://review.coreboot.org/c/coreboot/+/46272/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46272/4//COMMIT_MSG@7 PS4, Line 7: soc/intel/skl + cpu/intel/common: move AES-NI locking to common cpu code > In case you think too, that this is much too long, how about: […] ack https://review.coreboot.org/c/coreboot/+/46272/4/src/include/cpu/intel/msr.h File src/include/cpu/intel/msr.h: https://review.coreboot.org/c/coreboot/+/46272/4/src/include/cpu/intel/msr.… PS4, Line 8: #define MSR_FEATURE_CONFIG 0x13c > Should this be removed from the other header? Users could include this […] did you mean "the other header[s]"? src/cpu/intel/model_2065x/model_2065x.h src/cpu/intel/model_206ax/model_206ax.h src/soc/intel/common/block/include/intelblocks/msr.h src/soc/intel/denverton_ns/include/soc/msr.h src/soc/intel/broadwell/include/soc/msr.h https://review.coreboot.org/c/coreboot/+/46272/4/src/include/cpu/intel/msr.… PS4, Line 9: #define AESNI_LOCK_BIT 0 > As we mostly use bit masks in coreboot, this seems highly error-prone. […] Hmm, indeed it's only used a few times in cpu/intel and once in soc/intel. I agree, that we shouldn't mix bits and bit masks. However, dropping msr_set_bit() would require dropping the simplification in CB:46275. What do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/46272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e Gerrit-Change-Number: 46272 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 10:17:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/ocp/deltalake: Update SMBIOS type 9 information
by Patrick Georgi (Code Review) 13 Oct '20

13 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46125 ) Change subject: mb/ocp/deltalake: Update SMBIOS type 9 information ...................................................................... mb/ocp/deltalake: Update SMBIOS type 9 information Update Slot Designation strings and add SSD0_M2_Boot_Drive for config A. TEST="dmidecode -t 9" to verify the results are expected. Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com> Change-Id: I3fc03a14ff7dc43d6ddf5aa36710c99dbc648afa Reviewed-on: https://review.coreboot.org/c/coreboot/+/46125 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/ocp/deltalake/ramstage.c 1 file changed, 15 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index c03ad68..74a4468 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -54,20 +54,20 @@ } slot_info; slot_info slotinfo[] = { - {CSTACK, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0xE8, "DL on board M.2 #1 - boot"}, - {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "DL on board M.2 #2"}, - {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "Mezz Card"}, - {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "1ou expansion M.2 #1"}, - {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "1ou expansion M.2 #2"}, - {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "1ou expansion M.2 #3"}, - {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "1ou expansion M.2 #4"}, - {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "2ou expansion M.2 #1"}, - {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "2ou expansion M.2 #2"}, - {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "2ou expansion M.2 #3"}, - {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "2ou expansion M.2 #4"}, - {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "2ou expansion M.2 #5"}, - {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "2ou expansion M.2 #6"}, - {PSTACK2, SlotTypePciExpressGen3X16, SlotDataBusWidth16X, 0x00, "Mezz Card(Class-2)"}, + {CSTACK, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0xE8, "SSD1_M2_Data_Drive"}, + {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "SSD0_M2_Boot_Drive"}, + {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "BB_OCP_NIC"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "1OU_JD2_M2_3"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "1OU_JD2_M2_2"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "1OU_JD1_M2_1"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "1OU_JD1_M2_0"}, + {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "2OU_JD1_M2_0"}, + {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "2OU_JD1_M2_1"}, + {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "2OU_JD3_M2_4"}, + {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "2OU_JD3_M2_5"}, + {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "2OU_JD2_M2_3"}, + {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "2OU_JD2_M2_2"}, + {PSTACK2, SlotTypePciExpressGen3X16, SlotDataBusWidth16X, 0x00, "1OU_OCP_NIC"}, }; #define SPD_REGVID_LEN 6 @@ -151,7 +151,7 @@ for (index = 0; index < ARRAY_SIZE(slotinfo); index++) { if (pcie_config == PCIE_CONFIG_A) { - if (index == 0 || index == 2) + if (index == 0 || index == 1 || index == 2) printk(BIOS_INFO, "Find Config-A slot: %s\n", slotinfo[index].slot_designator); else -- To view, visit https://review.coreboot.org/c/coreboot/+/46125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fc03a14ff7dc43d6ddf5aa36710c99dbc648afa Gerrit-Change-Number: 46125 Gerrit-PatchSet: 4 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: acpi: Support MSDM table signature as SLIC
by Patrick Georgi (Code Review) 13 Oct '20

13 Oct '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44995 ) Change subject: acpi: Support MSDM table signature as SLIC ...................................................................... acpi: Support MSDM table signature as SLIC Accept an MSDM table (a newer revision of SLIC, with similar ACPI structure) to advertise SLIC support. Tested, Windows registers the digital license. Change-Id: Ic3a1374c8a4880111a30662823c3be99008eedd3 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44995 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/acpi.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 0b65459..89f2a46 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1367,7 +1367,8 @@ if (slic_file && (slic_file->length > slic_size || slic_file->length < sizeof(acpi_header_t) - || memcmp(slic_file->signature, "SLIC", 4) != 0)) { + || (memcmp(slic_file->signature, "SLIC", 4) != 0 + && memcmp(slic_file->signature, "MSDM", 4) != 0))) { slic_file = 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3a1374c8a4880111a30662823c3be99008eedd3 Gerrit-Change-Number: 44995 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020