Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45899 )
Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45899/5/src/vendorcode/intel/fsp/f…
File src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/45899/5/src/vendorcode/intel/fsp/f…
PS5, Line 2715: Level 1
> I will try to check with FSP team regarding this. […]
check this in TGL there is 2 level. Right now in JSL there is only one level.
https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr…
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Hello Felix Singer, build bot (Jenkins), Paul Menzel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46311
to look at the new patch set (#3).
Change subject: mb/clevo/l140cu: add CMOS layout and defaults
......................................................................
mb/clevo/l140cu: add CMOS layout and defaults
Add CMOS layout and defaults files and enable CMOS options in Kconfig.
Change-Id: Ia1a27818b2d12fb7578189e5748b8073c8f928e3
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/clevo/cml-u/Kconfig
A src/mainboard/clevo/cml-u/variants/l140cu/cmos.default
A src/mainboard/clevo/cml-u/variants/l140cu/cmos.layout
3 files changed, 66 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/46311/3
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Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Subrata Banik, Aamir Bohra, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45958
to look at the new patch set (#24).
Change subject: [UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: drop duplicate PM ACPI timer disabling
......................................................................
[UNTESTED] soc/intel/{icl,tgl,jsl,ehl,adl}: drop duplicate PM ACPI timer disabling
FSP already disables the PM ACPI timer, when EnableTcoTimer=0, so there
is no need to do it again in coreboot.
Change-Id: I5594ac423d6dff4c3212d657c242137492dc5d2a
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/finalize.c
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/Kconfig
M src/soc/intel/common/block/pmc/pmclib.c
M src/soc/intel/elkhartlake/Kconfig
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/finalize.c
M src/soc/intel/icelake/Kconfig
M src/soc/intel/icelake/chip.h
M src/soc/intel/icelake/finalize.c
M src/soc/intel/jasperlake/Kconfig
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/finalize.c
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/finalize.c
17 files changed, 4 insertions(+), 107 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45958/24
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45536 )
Change subject: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries
......................................................................
Patch Set 10:
> Patch Set 9:
>
> Can you please add ADL too ?
Done
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Hello Elyes HAOUAS, build bot (Jenkins), Nico Huber, Paul Menzel, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45536
to look at the new patch set (#10).
Change subject: soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries
......................................................................
soc/intel/{cnl,icl,tgl,jsl,ehl,adl}/acpi: generate CPPC entries
Make use of the previously added common function for generating CPPC
entries, when Intel SpeedShift is enabled.
Change-Id: I40d47d18a35002bc9ec55473e94277d89fc5797e
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/alderlake/acpi.c
M src/soc/intel/cannonlake/acpi.c
M src/soc/intel/elkhartlake/acpi.c
M src/soc/intel/icelake/acpi.c
M src/soc/intel/jasperlake/acpi.c
M src/soc/intel/tigerlake/acpi.c
6 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/45536/10
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46272 )
Change subject: soc/intel/skl + cpu/intel/common: move AES-NI locking to common cpu code
......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/46272/4//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/46272/4//COMMIT_MSG@7
PS4, Line 7: soc/intel/skl + cpu/intel/common: move AES-NI locking to common cpu code
> In case you think too, that this is much too long, how about: […]
ack
https://review.coreboot.org/c/coreboot/+/46272/4/src/include/cpu/intel/msr.h
File src/include/cpu/intel/msr.h:
https://review.coreboot.org/c/coreboot/+/46272/4/src/include/cpu/intel/msr.…
PS4, Line 8: #define MSR_FEATURE_CONFIG 0x13c
> Should this be removed from the other header? Users could include this […]
did you mean "the other header[s]"?
src/cpu/intel/model_2065x/model_2065x.h
src/cpu/intel/model_206ax/model_206ax.h
src/soc/intel/common/block/include/intelblocks/msr.h
src/soc/intel/denverton_ns/include/soc/msr.h
src/soc/intel/broadwell/include/soc/msr.h
https://review.coreboot.org/c/coreboot/+/46272/4/src/include/cpu/intel/msr.…
PS4, Line 9: #define AESNI_LOCK_BIT 0
> As we mostly use bit masks in coreboot, this seems highly error-prone. […]
Hmm, indeed it's only used a few times in cpu/intel and once in soc/intel. I agree, that we shouldn't mix bits and bit masks. However, dropping msr_set_bit() would require dropping the simplification in CB:46275. What do you think?
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Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45899 )
Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45899/5/src/vendorcode/intel/fsp/f…
File src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/45899/5/src/vendorcode/intel/fsp/f…
PS5, Line 2715: Level 1
> Alright. When there are multiple levels, it would be good to know what they mean.
I will try to check with FSP team regarding this. Is there any near future plan to expand levels this levels. what does this level means here.
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