coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: soc/intel/skylake: Rename PcieRpAspm devicetree config
by Frans Hendriks (Code Review) 13 Oct '20

13 Oct '20

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45001 ) Change subject: soc/intel/skylake: Rename PcieRpAspm devicetree config ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/45001/3/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.h: https://review.coreboot.org/c/coreboot/+/45001/3/src/soc/intel/skylake/chip… PS3, Line 265: } pcierp_aspm[CONFIG_MAX_ROOT_PORTS]; Would PcieRp_Aspem better match other element names? -- To view, visit https://review.coreboot.org/c/coreboot/+/45001 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057 Gerrit-Change-Number: 45001 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 08:31:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: lib/cbfs: deserialize cbfs_stage objects correctly
by Aaron Durbin (Code Review) 13 Oct '20

13 Oct '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46227 ) Change subject: lib/cbfs: deserialize cbfs_stage objects correctly ...................................................................... lib/cbfs: deserialize cbfs_stage objects correctly cbfstool emits cbfs_stage objects in little endian encoding. However, big endian targets then read the wrong values from these objects. To maintain backwards compatibility with existing cbfs objects add in the little endian deserialization. Change-Id: Ia113f7ddfa93f0ba5a76e0397f06f9b84c833727 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/lib/cbfs.c 1 file changed, 9 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/46227/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index cb66f81..35193d0 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -4,8 +4,8 @@ #include <boot_device.h> #include <cbfs.h> #include <commonlib/bsd/compression.h> +#include <commonlib/endian.h> #include <console/console.h> -#include <endian.h> #include <fmap.h> #include <lib.h> #include <security/tpm/tspi/crtm.h> @@ -296,10 +296,16 @@ foffset = 0; foffset += sizeof(stage); + /* cbfs_stage fields are written in little endian despite the other + cbfs data types being encoded in big endian. */ + stage.compression = read_le32(&stage.compression); + stage.entry = read_le64(&stage.entry); + stage.load = read_le64(&stage.load); + stage.len = read_le32(&stage.len); + stage.memlen = read_le32(&stage.memlen); + assert(fsize == stage.len); - /* Note: cbfs_stage fields are currently in the endianness of the - * running processor. */ load = (void *)(uintptr_t)stage.load; entry = (void *)(uintptr_t)stage.entry; -- To view, visit https://review.coreboot.org/c/coreboot/+/46227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia113f7ddfa93f0ba5a76e0397f06f9b84c833727 Gerrit-Change-Number: 46227 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/mainboard/dedede: Add P-sensor for Boten
by Yan Liu (Code Review) 13 Oct '20

13 Oct '20

Yan Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43478 ) Change subject: mb/mainboard/dedede: Add P-sensor for Boten ...................................................................... mb/mainboard/dedede: Add P-sensor for Boten Add devicetree and device ID for P-sensor BUG=b:161217096 BRANCH=NONE TEST=We can get the data from P-sensor if touch the SAR antenna. Signed-off-by: Yan Liu <yan.liu(a)bitland.corp-partner.google.com> Change-Id: I8e02c2cf477aa83b3d4c69ce84d48a8ad1a2560f --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/boten/overridetree.cb 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/43478/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index dcea3fa..0658e66 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -17,6 +17,7 @@ select MAINBOARD_HAS_SPI_TPM_CR50 select MAINBOARD_HAS_TPM2 select SOC_INTEL_JASPERLAKE + select DRIVERS_I2C_SX9310 if BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 46fe20e..e743abe 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -140,6 +140,15 @@ device i2c 29 on end end end # I2C 4 + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""sx932x"" + register "name" = ""Semtech sx932x"" + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)" + device i2c 28 on end + end + end # I2C 5 device pci 1f.3 on end # Intel HDA/cAVS end end -- To view, visit https://review.coreboot.org/c/coreboot/+/43478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e02c2cf477aa83b3d4c69ce84d48a8ad1a2560f Gerrit-Change-Number: 43478 Gerrit-PatchSet: 1 Gerrit-Owner: Yan Liu <yan.liu(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

9 31

Change in coreboot[master]: mb/google/slippy: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 13 Oct '20

13 Oct '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46179 ) Change subject: mb/google/slippy: Convert to ASL 2.0 syntax ...................................................................... mb/google/slippy: Convert to ASL 2.0 syntax Change-Id: I6a0b0e53cfccc1715f236bd6700b42d1147b74b3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/slippy/acpi/platform.asl M src/mainboard/google/slippy/acpi/thermal.asl M src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl M src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl M src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl M src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl 6 files changed, 41 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/46179/1 diff --git a/src/mainboard/google/slippy/acpi/platform.asl b/src/mainboard/google/slippy/acpi/platform.asl index 2813078..a5f343d 100644 --- a/src/mainboard/google/slippy/acpi/platform.asl +++ b/src/mainboard/google/slippy/acpi/platform.asl @@ -15,16 +15,16 @@ Method(_WAK,1) { /* Update AC status */ - Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0) - if (LNotEqual (Local0, \PWRS)) { - Store (Local0, \PWRS) + Local0 = \_SB.PCI0.LPCB.EC0.ACEX + if (Local0 != \PWRS) { + \PWRS = Local0 Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) } /* Update LID status */ Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0) - if (LNotEqual (Local0, \LIDS)) { - Store (Local0, \LIDS) + if (Local0 != \LIDS) { + \LIDS = Local0 Notify (\_SB.PCI0.LPCB.EC0.LID0, 0x80) } diff --git a/src/mainboard/google/slippy/acpi/thermal.asl b/src/mainboard/google/slippy/acpi/thermal.asl index 74e73a2..838565b 100644 --- a/src/mainboard/google/slippy/acpi/thermal.asl +++ b/src/mainboard/google/slippy/acpi/thermal.asl @@ -12,7 +12,7 @@ // 1 = Start throttling Method (THRT, 1, Serialized) { - If (LEqual (Arg0, 0)) { + If (Arg0 == 0) { /* Disable Power Limit */ \_SB.PCI0.MCHC.CTLD () } Else { @@ -35,10 +35,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -64,56 +64,56 @@ Method (TCHK, 0, Serialized) { // Get Temperature from TIN# set in NVS - Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TINS (TMPS) // Check for sensor not calibrated - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNCA) { Return (CTOK(0)) } // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNPR) { Return (CTOK(0)) } // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNOP) { Return (CTOK(0)) } // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TBAD) { Return (CTOK(0)) } // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + Local0 += \_SB.PCI0.LPCB.EC0.TOFS // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) + Local0 *= 10 Return (Local0) } Method (_TMP, 0, Serialized) { // Get temperature from EC in deci-kelvin - Store (TCHK (), Local0) + Local0 = TCHK () // Critical temperature in deci-kelvin - Store (CTOK (\TCRT), Local1) + Local1 = CTOK (\TCRT) - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 // Wait 1 second for EC to re-poll Sleep (1000) // Re-read temperature from EC - Store (TCHK (), Local0) + Local0 = TCHK () - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Debug = "RE-READ TEMPERATURE" + Debug = Local0 } Return (Local0) diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl index d395a31..49f146c 100644 --- a/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl @@ -26,7 +26,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -37,8 +37,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GWAK (Local0) } diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl index bf4adfd..e5af385 100644 --- a/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl @@ -26,7 +26,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -37,8 +37,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GWAK (Local0) } diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl index 8bbb19a..5a7d294 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl @@ -26,7 +26,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -37,8 +37,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GWAK (Local0) } @@ -68,7 +68,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -79,8 +79,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GWAK (Local0) } @@ -119,8 +119,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TOUCHSCREEN_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GWAK (Local0) } @@ -135,7 +135,7 @@ Method (_STA) { - If (LEqual (\S2EN, 1)) { + If (\S2EN == 1) { Return (0xF) } Else { Return (0x0) diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl index bf4adfd..e5af385 100644 --- a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl @@ -26,7 +26,7 @@ Method (_STA) { - If (LEqual (\S1EN, 1)) { + If (\S1EN == 1) { Return (0xF) } Else { Return (0x0) @@ -37,8 +37,8 @@ Method (_DSW, 3, NotSerialized) { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) - If (LEqual (Arg0, 1)) { + Local0 = BOARD_TRACKPAD_WAKE_GPIO + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GWAK (Local0) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a0b0e53cfccc1715f236bd6700b42d1147b74b3 Gerrit-Change-Number: 46179 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376
by Ronak Kanabar (Code Review) 13 Oct '20

13 Oct '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45899 ) Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376 ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/45899/5/src/vendorcode/intel/fsp/f… File src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h: https://review.coreboot.org/c/coreboot/+/45899/5/src/vendorcode/intel/fsp/f… PS5, Line 2715: Level 1 > Are there more levels? Right now there is only one level. It is kind of place holder here, if in future revisions if FSP teams feels need to break it in some more levels they can add level in same UPD give some more flexibility. -- To view, visit https://review.coreboot.org/c/coreboot/+/45899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65c03d8eda11664541479983c7be11854410e1c6 Gerrit-Change-Number: 45899 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 07:30:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/i2c: Add chip driver for GPIO based I2C multiplexer
by Furquan Shaikh (Code Review) 13 Oct '20

13 Oct '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45911 ) Change subject: drivers/i2c: Add chip driver for GPIO based I2C multiplexer ...................................................................... Patch Set 7: Code-Review+2 (2 comments) https://review.coreboot.org/c/coreboot/+/45911/7/src/drivers/i2c/gpiomux/mu… File src/drivers/i2c/gpiomux/mux/mux.c: https://review.coreboot.org/c/coreboot/+/45911/7/src/drivers/i2c/gpiomux/mu… PS7, Line 30: config Checking config for NULL is not required since config_of() guarantees that you don't have a NULL pointer for config. https://review.coreboot.org/c/coreboot/+/45911/7/src/drivers/i2c/gpiomux/mu… PS7, Line 30: !dev Probably weird to check dev after it is already referenced in config_of() above? -- To view, visit https://review.coreboot.org/c/coreboot/+/45911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b Gerrit-Change-Number: 45911 Gerrit-PatchSet: 7 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 13 Oct 2020 06:50:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/puff/var/dooly: Update devicetree for audio configuration
by Tony Huang (Code Review) 13 Oct '20

13 Oct '20

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46289 ) Change subject: mb/google/puff/var/dooly: Update devicetree for audio configuration ...................................................................... mb/google/puff/var/dooly: Update devicetree for audio configuration 1. Add speaker amplifier ALC1015 2. Enable dmic+ssp registers for speaker and camera DMIC BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: I5f6f19b40c6fcce8dca9b010ae97ea6e3eeb1473 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/dooly/overridetree.cb 1 file changed, 21 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46289/1 diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index 21bbc3c..ee91dd3 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -105,10 +105,6 @@ # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" - # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkDmic0" = "0" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -117,10 +113,10 @@ #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | - #| I2C0 | RFU | - #| I2C2 | PS175 | - #| I2C3 | MST | - #| I2C4 | Audio | + #| I2C0 | ALC 1015 | + #| I2C2 | Lvds | + #| I2C3 | Touchscreen | + #| I2C4 | RT5682 | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { @@ -299,27 +295,24 @@ end end # USB xHCI device pci 14.5 off end # SDCard - device pci 15.0 off - # RFU - Reserved for Future Use. - end # I2C #0 + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end # I2C #0 ALC1015 device pci 15.1 off end # I2C #1 - device pci 15.2 on - chip drivers/i2c/generic - register "hid" = ""1AF80175"" - register "name" = ""PS17"" - register "desc" = ""Parade PS175"" - device i2c 4a on end - end - end # I2C #2, PCON PS175. - device pci 15.3 on - chip drivers/i2c/generic - register "hid" = ""10EC2142"" - register "name" = ""RTD2"" - register "desc" = ""Realtek RTD2142"" - device i2c 4a on end - end - end # I2C #3, Realtek RTD2142. - device pci 16.0 on end # Management Engine Interface 1 + device pci 15.2 on end # I2C #2 LVDS + device pci 15.3 on end # I2C #3 Touchscreen + device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic register "hid" = ""10EC5682"" -- To view, visit https://review.coreboot.org/c/coreboot/+/46289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f6f19b40c6fcce8dca9b010ae97ea6e3eeb1473 Gerrit-Change-Number: 46289 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: mb/google/puff/var/dooly: Update devicetree to remove unused devices
by Tony Huang (Code Review) 13 Oct '20

13 Oct '20

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46288 ) Change subject: mb/google/puff/var/dooly: Update devicetree to remove unused devices ...................................................................... mb/google/puff/var/dooly: Update devicetree to remove unused devices Remove unused device in Dooly no SD card reader no built-in LAN BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: I8ab1e156031bfb4d5ea30048d8a10400f2a49411 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/dooly/overridetree.cb 1 file changed, 1 insertion(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/46288/1 diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index 9d7cf1f..21bbc3c 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -149,9 +149,6 @@ }, }" - # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" @@ -159,9 +156,6 @@ register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - # SATA port 1 Gen3 Strength # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB register "sata_port[1].TxGen3DeEmphEnable" = "1" @@ -304,6 +298,7 @@ end end end # USB xHCI + device pci 14.5 off end # SDCard device pci 15.0 off # RFU - Reserved for Future Use. end # I2C #0 @@ -340,19 +335,6 @@ end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1c.6 on - chip drivers/net - register "customized_leds" = "0x05af" - register "wake" = "GPE0_DW1_07" # GPP_C7 - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" - register "stop_delay_ms" = "12" # NIC needs time to quiesce - register "stop_off_delay_ms" = "1" - register "has_power_resource" = "1" - register "device_index" = "0" - device pci 00.0 on end - end - register "PcieRpSlotImplemented[6]" = "1" - end # RTL8111H Ethernet NIC device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) register "PcieRpSlotImplemented[10]" = "1" end -- To view, visit https://review.coreboot.org/c/coreboot/+/46288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ab1e156031bfb4d5ea30048d8a10400f2a49411 Gerrit-Change-Number: 46288 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/puff/var/dooly: Update devicetree for project change
by Tony Huang (Code Review) 13 Oct '20

13 Oct '20

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46126 ) Change subject: mb/google/puff/var/dooly: Update devicetree for project change ...................................................................... mb/google/puff/var/dooly: Update devicetree for project change 1. Update USB configuration USBA*2 USBC*2 2. Remove unused device no SD card reader no built-in LAN 3. Add audio configuration ALC1015 speaker amplifier 4. Enable dmic+ssp registers DMIC for camera module BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: Icb66a8d5382ca9664e7f0b3660f446aeb3cf1dd3 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/dooly/overridetree.cb 1 file changed, 60 insertions(+), 129 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/46126/1 diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index 8a603f7..2260ba6 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -21,13 +21,14 @@ # USB configuration register "usb2_ports[0]" = "{ .enable = 1, - .ocpin = OC2, + .ocpin = OC0, .tx_bias = USB2_BIAS_0MV, .tx_emp_enable = USB2_PRE_EMP_ON, .pre_emp_bias = USB2_BIAS_11P25MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 2 - register "usb2_ports[1]" = "{ + }" # Type-A Port 0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 0 + register "usb2_ports[2]" = "{ .enable = 1, .ocpin = OC1, .tx_bias = USB2_BIAS_0MV, @@ -35,61 +36,26 @@ .pre_emp_bias = USB2_BIAS_28P15MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 1 - register "usb2_ports[2]" = "{ - .enable = 1, - .ocpin = OC3, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 3 - register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port - register "usb2_ports[4]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A Port 4 - register "usb2_ports[5]" = "{ - .enable = 1, - .ocpin = OC0, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # Type-A port 0 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1 + register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # USB cam register "usb2_ports[6]" = "USB2_PORT_EMPTY" register "usb2_ports[7]" = "USB2_PORT_EMPTY" register "usb2_ports[8]" = "USB2_PORT_EMPTY" - register "usb2_ports[9]" = "{ - .enable = 1, - .ocpin = OC_SKIP, - .tx_bias = USB2_BIAS_0MV, - .tx_emp_enable = USB2_PRE_EMP_ON, - .pre_emp_bias = USB2_BIAS_28P15MV, - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, - }" # BT + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port 0 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Bitmap for Wake Enable on USB attach/detach register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" + USB_PORT_WAKE_ENABLE(3)" register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ - USB_PORT_WAKE_ENABLE(2) | \ - USB_PORT_WAKE_ENABLE(3) | \ - USB_PORT_WAKE_ENABLE(5) | \ - USB_PORT_WAKE_ENABLE(6)" + USB_PORT_WAKE_ENABLE(2)" # Enable eMMC HS400 register "ScsEmmcHs400Enabled" = "1" @@ -139,10 +105,6 @@ # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515" - # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them. - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkDmic0" = "0" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -151,9 +113,9 @@ #| | required to set up a BAR | #| | for TPM communication | #| | before memory is up | - #| I2C0 | RFU | - #| I2C2 | PS175 | - #| I2C3 | MST | + #| I2C0 | ALC 1015 | + #| I2C2 | Lvds | + #| I2C3 | Touchscreen | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ @@ -183,9 +145,6 @@ }, }" - # PCIe port 7 for LAN - register "PcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" # PCIe port 11 (x2) for NVMe hybrid storage devices register "PcieRpEnable[10]" = "1" register "PcieRpLtrEnable[10]" = "1" @@ -193,9 +152,6 @@ register "PcieClkSrcUsage[0]" = "6" register "PcieClkSrcClkReq[0]" = "0" - # GPIO for SD card detect - register "sdcard_cd_gpio" = "vSD3_CD_B" - # SATA port 1 Gen3 Strength # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB register "sata_port[1].TxGen3DeEmphEnable" = "1" @@ -271,103 +227,91 @@ chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Left"" + register "desc" = ""USB2 Type-A Port 0"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" + register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 2.0 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port Rear"" + register "desc" = ""USB2 Type-C Port 0"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" + register "group" = "ACPI_PLD_GROUP(2, 1)" device usb 2.1 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Front Right"" + register "desc" = ""USB2 Type-A Port 1"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" + register "group" = "ACPI_PLD_GROUP(1, 2)" device usb 2.2 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Right"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" - device usb 2.3 on end - end + device usb 2.3 off end + end chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Middle"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "desc" = ""USB2 Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" device usb 2.4 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Rear Left"" - register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" device usb 2.5 on end end chip drivers/usb/acpi device usb 2.6 off end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Left"" + register "desc" = ""USB3 Type-A Port 0"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 0)" + register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 3.0 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Front Right"" + register "desc" = ""USB3 Type-A Port 1"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(0, 1)" + register "group" = "ACPI_PLD_GROUP(1, 2)" device usb 3.1 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Right"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "desc" = ""USB3 Type-C Port 1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" device usb 3.2 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Rear"" + register "desc" = ""USB3 Type-C Port 0"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 3)" + register "group" = "ACPI_PLD_GROUP(2, 1)" device usb 3.3 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Left"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 0)" - device usb 3.4 on end + device usb 3.4 off end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Rear Middle"" - register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 1)" - device usb 3.5 on end + device usb 3.5 off end end end end end # USB xHCI - device pci 15.0 off - # RFU - Reserved for Future Use. - end # I2C #0 + device pci 14.5 off end # SDCard + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end # I2C #0 ALC1015 device pci 15.1 off end # I2C #1 - device pci 15.2 on - chip drivers/i2c/generic - register "hid" = ""1AF80175"" - register "name" = ""PS17"" - register "desc" = ""Parade PS175"" - device i2c 4a on end - end - end # I2C #2, PCON PS175. - device pci 15.3 on - chip drivers/i2c/generic - register "hid" = ""10EC2142"" - register "name" = ""RTD2"" - register "desc" = ""Realtek RTD2142"" - device i2c 4a on end - end - end # I2C #3, Realtek RTD2142. + device pci 15.2 on end # I2C #2 LVDS + device pci 15.3 on end # I2C #3 Touchscrren device pci 16.0 on end # Management Engine Interface 1 device pci 19.0 on chip drivers/i2c/generic @@ -384,19 +328,6 @@ end end #I2C #4 device pci 1a.0 on end # eMMC - device pci 1c.6 on - chip drivers/net - register "customized_leds" = "0x05af" - register "wake" = "GPE0_DW1_07" # GPP_C7 - register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" - register "stop_delay_ms" = "12" # NIC needs time to quiesce - register "stop_off_delay_ms" = "1" - register "has_power_resource" = "1" - register "device_index" = "0" - device pci 00.0 on end - end - register "PcieRpSlotImplemented[6]" = "1" - end # RTL8111H Ethernet NIC device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) register "PcieRpSlotImplemented[10]" = "1" end -- To view, visit https://review.coreboot.org/c/coreboot/+/46126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb66a8d5382ca9664e7f0b3660f446aeb3cf1dd3 Gerrit-Change-Number: 46126 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: mb/google/puff/var/dooly: Update GPIO table for project use
by Tony Huang (Code Review) 13 Oct '20

13 Oct '20

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46128 ) Change subject: mb/google/puff/var/dooly: Update GPIO table for project use ...................................................................... mb/google/puff/var/dooly: Update GPIO table for project use Override unused device SD card reader, built-in LAN ALC1015 speaker amplifier SPK_AMP_ON Update touchscreen/lvds gpio pin BUG=b:170273526 BRANCH=puff TEST=Build and check DUT function status Change-Id: Ife14adf59609870abe9f4ba1eabe2573cb6e92dd Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/dooly/gpio.c 1 file changed, 57 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/46128/1 diff --git a/src/mainboard/google/hatch/variants/dooly/gpio.c b/src/mainboard/google/hatch/variants/dooly/gpio.c index 5a911fc..4406c06 100644 --- a/src/mainboard/google/hatch/variants/dooly/gpio.c +++ b/src/mainboard/google/hatch/variants/dooly/gpio.c @@ -5,38 +5,56 @@ #include <commonlib/helpers.h> static const struct pad_config gpio_table[] = { - /* A16 : SD_OC_ODL */ - PAD_CFG_GPI(GPP_A16, NONE, DEEP), - /* A18 : LAN_PE_ISOLATE_ODL */ - PAD_CFG_GPO(GPP_A18, 1, DEEP), + /* A17 : SD_VDD1_PWR_EN */ + PAD_NC(GPP_A17, NONE), + /* A18 : GPP_A18 */ + PAD_NC(GPP_A18, NONE), + /* A19 : GPP_A19 */ + PAD_NC(GPP_A19, NONE), + /* A20 : TOUCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, NONE), + /* A21 : FPMCU_PCH_BOOT0 */ + PAD_NC(GPP_A21, NONE), + /* A22 : FPMCU_PCH_INT_L */ + PAD_NC(GPP_A22, NONE), /* A23 : M2_WLAN_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT), - /* B5 : LAN_CLKREQ_ODL */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), - /* C0 : SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* C1 : SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* C3 : GPP_C3 */ + PAD_NC(GPP_C3, NONE), + /* C4 : GPP_C4 */ + PAD_NC(GPP_C4, NONE), /* C6: M2_WLAN_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), /* C7 : LAN_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), - /* C10 : PCH_PCON_RST_ODL */ - PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : PCH_PCON_PDB_ODL */ - PAD_CFG_GPO(GPP_C11, 1, DEEP), + PAD_NC(GPP_C7, NONE), + /* C11 : GPP_C11 */ + PAD_NC(GPP_C11, NONE), /* C15 : WLAN_OFF_L */ PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* C18 : GPP_C18 */ + PAD_NC(GPP_C18, NONE), + /* C19 : GPP_C19 */ + PAD_NC(GPP_C19, NONE), + + /* D16 : DMIC_ON_OFF MIC_SWITCH_L */ + PAD_CFG_GPI(GPP_D16, NONE, DEEP), /* E2 : EN_PP_MST_OD */ PAD_CFG_GPO(GPP_E2, 1, DEEP), - /* E9 : USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* E10 : USB_A1_OC_ODL */ - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + /* F0 : GPP_F0 */ + PAD_NC(GPP_F0, NONE), + /* F1 : GPP_F1 */ + PAD_NC(GPP_F1, NONE), + /* F8 : GPP_F8 */ + PAD_NC(GPP_F8, NONE), + /* F9 : GPP_F9 */ + PAD_NC(GPP_F9, NONE), /* F11 : EMMC_CMD */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), /* F12 : EMMC_DATA0 */ @@ -62,12 +80,31 @@ /* F22 : EMMC_RST_L */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - /* H4: PCH_I2C_PCON_SDA */ + /* G0 : SD_CMD */ + PAD_NC(GPP_G0, NONE), + /* G1 : SD_DATA0 */ + PAD_NC(GPP_G1, NONE), + /* G2 : SD_DATA1 */ + PAD_NC(GPP_G2, NONE), + /* G3 : SD_DATA2 */ + PAD_NC(GPP_G3, NONE), + /* G4 : SD_DATA3 */ + PAD_NC(GPP_G4, NONE), + /* G5 : SD_CD */ + PAD_NC(GPP_G5, NONE), + /* G6 : SD_CLK */ + PAD_NC(GPP_G6, NONE), + + /* H3 : SPK_AMP_ON */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4: LVDS_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5: PCH_I2C_PCON_SCL */ + /* H5: LVDS_SDL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H22 : PWM_PP3300_BIOZZER */ - PAD_CFG_GPO(GPP_H22, 0, DEEP), + /* H6 : PCH_I2C_TOUCH_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : PCH_I2C_TOUCH_SDL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), }; const struct pad_config *override_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/46128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife14adf59609870abe9f4ba1eabe2573cb6e92dd Gerrit-Change-Number: 46128 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 3

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020